Update_SR_Register64 sets SR_TOP2BITS based on m, not h (does someone have tests saying otherwise?)
clean up dsp_base.inc a little, use some irom funcs where possible git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@5069 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
Shawn Hoffman
parent
dc76856736
commit
e0e5a25bcd
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@ -112,6 +112,7 @@
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#define DSP_DSMAL 0xcf // DSP DMA Address Low (External)
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#define DSP_FORMAT 0xd1 // Sample format
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#define DSP_ACUNK 0xd2 // Set to 3 on my dumps
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#define DSP_ACDATA1 0xd3 // used only by Zelda ucodes
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#define DSP_ACSAH 0xd4 // Start of loop
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#define DSP_ACSAL 0xd5
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@ -124,8 +125,9 @@
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#define DSP_YN2 0xdc
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#define DSP_ACCELERATOR 0xdd // ADPCM accelerator read. Used by AX.
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#define DSP_GAIN 0xde
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#define DSP_ACUNK2 0xdf // Set to 0xc on my dumps
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#define DSP_DREQ_MASK 0xef // ARAM DMA Request Mask
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#define DSP_AMDM 0xef // ARAM DMA Request Mask 0: DMA with ARAM unmasked 1: masked
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#define DSP_DIRQ 0xfb // DSP Irq Rest
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#define DSP_DMBH 0xfc // DSP Mailbox H
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@ -51,9 +51,9 @@ void Update_SR_Register64(s64 _Value, bool carry, bool overflow)
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g_dsp.r[DSP_REG_SR] |= SR_OVERFLOW;
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}
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// Checks if top bits are equal, what is it good for?
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if (((_Value >> 62) == 0) || (_Value >> 62 == 3))
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{
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// Checks if top bits of m are equal, what is it good for?
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if (((_Value & 0xc0000000) == 0) || ((_Value & 0xc0000000) == 0xc0000000))
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{
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g_dsp.r[DSP_REG_SR] |= SR_TOP2BITS;
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}
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}
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@ -551,7 +551,7 @@ bool DSPAssembler::VerifyParams(const opc_t *opc, param_t *par, int count, bool
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{
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if (ext) fprintf(stderr, "(ext) ");
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if (par[i].val >= 0x1e && par[i].val <= 0x1f) {
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fprintf(stderr, "%i : %s", code_line, cur_line.c_str());
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fprintf(stderr, "%i : %s ", code_line, cur_line.c_str());
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fprintf(stderr, "WARNING: $ACM%d register used instead of $ACC%d register Line: %d Param: %d Ext: %d\n",
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(par[i].val & 1), (par[i].val & 1), code_line, current_param, ext);
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}
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@ -584,12 +584,12 @@ bool DSPAssembler::VerifyParams(const opc_t *opc, param_t *par, int count, bool
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if (ext) fprintf(stderr, "(ext) ");
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if (par[i].val >= 0x1e && par[i].val <= 0x1f)
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{
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fprintf(stderr, "%s", cur_line.c_str());
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fprintf(stderr, "%s ", cur_line.c_str());
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fprintf(stderr, "WARNING: $ACM%d register used instead of $ACL%d register Line: %d Param: %d\n",
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(par[i].val & 1), (par[i].val & 1), code_line, current_param);
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}
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else if (par[i].val >= 0x20 && par[i].val <= 0x21) {
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fprintf(stderr, "%s", cur_line.c_str());
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fprintf(stderr, "%s ", cur_line.c_str());
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fprintf(stderr, "WARNING: $ACC%d register used instead of $ACL%d register Line: %d Param: %d\n",
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(par[i].val & 1), (par[i].val & 1), code_line, current_param);
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}
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@ -3,11 +3,8 @@ REGS_BASE: equ 0x0f80
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MEM_HI: equ 0x0f7E
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MEM_LO: equ 0x0f7F
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;
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; CODE STARTS HERE.
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; Interrupt vectors 8 vectors, 2 opcodes each
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jmp irq0
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jmp irq1
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jmp irq2
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@ -16,8 +13,8 @@ MEM_LO: equ 0x0f7F
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jmp irq5
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jmp irq6
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jmp irq7
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; Main code at 0x10
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; Main code (and normal entrypoint) at 0x10
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sbset #0x02
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sbset #0x03
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sbclr #0x04
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@ -27,24 +24,21 @@ MEM_LO: equ 0x0f7F
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s16
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lri $CR, #0x00ff
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; Why do we have a main label here?
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main:
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clr $acc1
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clr $acc0
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; get address of memory dump and copy it to DRAM
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call wait_for_dsp_mbox
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call 0x807e
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si @DMBH, #0x8888
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si @DMBL, #0xdead
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si @DIRQ, #0x0001
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call wait_for_cpu_mbox
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lrs $ac0.m, @CMBL
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andi $ac1.m, #0x7fff
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call 0x8078
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andi $ac0.m, #0x7fff
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lrs $ac1.m, @CMBL
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sr @MEM_HI, $ac1.m
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sr @MEM_LO, $ac0.m
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sr @MEM_HI, $ac0.m
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sr @MEM_LO, $ac1.m
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lri $ax0.l, #0
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lri $ax1.l, #0 ;(DSP_CR_IMEM | DSP_CR_TO_CPU)
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@ -55,18 +49,17 @@ main:
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; get address of registers and DMA them to ram
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call wait_for_dsp_mbox
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call 0x807e
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si @DMBH, #0x8888
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si @DMBL, #0xbeef
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si @DIRQ, #0x0001
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call wait_for_cpu_mbox
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lrs $ac0.m, @CMBL
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andi $ac1.m, #0x7fff
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call 0x8078
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andi $ac0.m, #0x7fff
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lrs $ac1.m, @CMBL
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sr @MEM_HI, $ac1.m
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sr @MEM_LO, $ac0.m
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sr @MEM_HI, $ac0.m
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sr @MEM_LO, $ac1.m
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lri $ax0.l, #REGS_BASE
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lri $ax1.l, #0 ;(DSP_CR_IMEM | DSP_CR_TO_CPU)
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@ -76,7 +69,6 @@ main:
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call do_dma
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; Read in all the registers from RAM
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lri $ar0, #REGS_BASE+1
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lrri $ar1, @$ar0
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lrri $ar2, @$ar0
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@ -114,51 +106,21 @@ main:
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jmp start_of_test
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; This is where we jump when we're done testing, see above.
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end_of_test:
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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; We just fall into a loop, playing dead until someone resets the DSP.
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dead_loop:
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jmp dead_loop
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end_of_test:
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jmp end_of_test
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; Utility function to do DMA.
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; ac0.l:ac0.m - external address.
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; ax0.l - address in DSP
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do_dma:
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sr @DSMAH, $ac0.l
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sr @DSMAL, $ac0.m
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sr @DSPA, $ax0.l
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sr @DSCR, $ax1.l
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sr @DSBL, $ax0.h ; This kicks off the DMA.
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; Waits for said DMA to complete by watching a bit in DSCR.
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wait_dma:
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lrs $ac1.m, @DSCR
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andcf $ac1.m, #0x0004
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jlz wait_dma
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sr @DSBL, $ax0.h ; This kicks off the DMA.
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call 0x863d ; Wait for DMA to complete by watching a bit in DSCR.
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ret
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; This waits for a mail to arrive in the DSP in-mailbox.
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wait_for_dsp_mbox:
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lrs $ac1.m, @DMBH
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andcf $ac1.m, #0x8000
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jlz wait_for_dsp_mbox
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ret
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; This waits for the CPU to grab a mail that we just sent from the DSP.
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wait_for_cpu_mbox:
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lrs $ac1.m, @CMBH
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andcf $ac1.m, #0x8000
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jlnz wait_for_cpu_mbox
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ret
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; IRQ handlers. Not entirely sure what good they do currently.
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; IRQ handlers. Just send back exception# and die
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irq0:
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lri $ac0.m, #0x0000
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jmp irq
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@ -175,21 +137,6 @@ irq4:
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lri $ac0.m, #0x0004
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jmp irq
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irq5:
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; No idea what this code is doing.
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s16
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mrr $st1, $ac0.l
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mrr $st1, $ac0.m
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clr $acc0
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mrr $ac0.m, $st1
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mrr $ac0.l, $st1
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nop ; Or why there's a nop sled here.
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nop
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nop
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nop
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nop
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nop
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rti
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lri $ac0.m, #0x0005
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jmp irq
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irq6:
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@ -197,7 +144,6 @@ irq6:
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jmp irq
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irq7:
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lri $ac0.m, #0x0007
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jmp irq
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irq:
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lrs $ac1.m, @DMBH
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@ -259,30 +205,26 @@ send_back:
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lr $ac0.l, @MEM_HI
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lr $ac0.m, @MEM_LO
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lri $ar1, #8+8
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; Now, why are we looping here?
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lri $ar1, #8+8
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bloop $ar1, dma_copy
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call do_dma
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addi $ac0.m, #0x200
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mrr $ac1.m, $ax0.l
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addi $ac1.m, #0x100
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dma_copy:
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mrr $ax0.l, $ac1.m
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nop
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dma_copy:
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nop
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; Wait for the CPU to send us a mail.
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call wait_for_dsp_mbox
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call 0x807e
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si @DMBH, #0x8888
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si @DMBL, #0xfeeb
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si @DIRQ, #0x0001
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; wait for the CPU to recieve our response before we execute the next op
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call wait_for_cpu_mbox
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lrs $ac0.m, @CMBL
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andi $ac1.m, #0x7fff
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call 0x8078
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andi $ac0.m, #0x7fff
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lrs $ac1.m, @CMBL
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; Restore all regs again so we're ready to execute another op.
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lri $ar0, #REGS_BASE+1
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@ -329,30 +271,5 @@ send_back_40:
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set40
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ret
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; This one's odd. Doesn't look like it should work since it uses ac0.m but
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; increments acm0... (acc0)
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; -- It's ok as addis adds short immediate to mid accumulator $acD.hm
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dump_memory:
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lri $ar2, #0x0000
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lri $ac0.m, #0x1000
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lri $ar1, #0x1000
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bloop $ar1, _fill_loop2
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mrr $ar3, $ac0.m
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nx'ld : $ax0.h, $ax1.h, @$ar0
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mrr $ac1.m, $ar0
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mrr $ar0, $ar2
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srri @$ar0, $ax1.h
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mrr $ar2, $ar0
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mrr $ar0, $ac1.m
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addis $ac0.m, #0x1
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_fill_loop2:
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nop
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ret ; from dump_memory
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; Obviously this must be included directly before your test code
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start_of_test:
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@ -59,9 +59,6 @@ bool DSPHost_Running()
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void DSPHost_InterruptRequest()
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{
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#if defined(_DEBUG) || defined(DEBUGFAST)
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NOTICE_LOG(DSPLLE, "Firing an interrupt on the PPC ASAP");
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#endif
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// Fire an interrupt on the PPC ASAP.
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g_dspInitialize.pGenerateDSPInterrupt();
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}
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