diff --git a/Source/Core/Core/PowerPC/JitArm64/Jit.cpp b/Source/Core/Core/PowerPC/JitArm64/Jit.cpp
index 1a5a8e36a9..da434b90d4 100644
--- a/Source/Core/Core/PowerPC/JitArm64/Jit.cpp
+++ b/Source/Core/Core/PowerPC/JitArm64/Jit.cpp
@@ -68,8 +68,8 @@ void JitArm64::Shutdown()
 
 void JitArm64::FallBackToInterpreter(UGeckoInstruction inst)
 {
-	gpr.Flush(FlushMode::FLUSH_INTERPRETER, js.op);
-	fpr.Flush(FlushMode::FLUSH_INTERPRETER, js.op);
+	gpr.Flush(FlushMode::FLUSH_ALL, js.op);
+	fpr.Flush(FlushMode::FLUSH_ALL, js.op);
 
 	if (js.op->opinfo->flags & FL_ENDBLOCK)
 	{
diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp
index befcf84643..ff02a7c558 100644
--- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp
+++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp
@@ -867,9 +867,6 @@ void JitArm64::subfic(UGeckoInstruction inst)
 
 		gpr.SetImmediate(d, imm - a_imm);
 		ComputeCarry(a_imm == 0 || Interpreter::Helper_Carry(imm, 0u - a_imm));
-
-		if (inst.Rc)
-			ComputeRC(gpr.GetImm(d), 0);
 	}
 	else
 	{
@@ -882,9 +879,6 @@ void JitArm64::subfic(UGeckoInstruction inst)
 		gpr.Unlock(WA);
 
 		ComputeCarry();
-
-		if (inst.Rc)
-			ComputeRC(gpr.R(d), 0);
 	}
 }
 
diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStore.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStore.cpp
index 52cf6ce94f..ee73a622bc 100644
--- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStore.cpp
+++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStore.cpp
@@ -327,32 +327,29 @@ void JitArm64::lXX(UGeckoInstruction inst)
 	switch (inst.OPCD)
 	{
 		case 31:
+			offsetReg = b;
 			switch (inst.SUBOP10)
 			{
 				case 55: // lwzux
 					update = true;
 				case 23: // lwzx
 					flags |= BackPatchInfo::FLAG_SIZE_32;
-					offsetReg = b;
 				break;
 				case 119: //lbzux
 					update = true;
 				case 87: // lbzx
 					flags |= BackPatchInfo::FLAG_SIZE_8;
-					offsetReg = b;
 				break;
 				case 311: // lhzux
 					update = true;
 				case 279: // lhzx
 					flags |= BackPatchInfo::FLAG_SIZE_16;
-					offsetReg = b;
 				break;
 				case 375: // lhaux
 					update = true;
 				case 343: // lhax
 					flags |= BackPatchInfo::FLAG_EXTEND |
 					         BackPatchInfo::FLAG_SIZE_16;
-					offsetReg = b;
 				break;
 				case 534: // lwbrx
 					flags |= BackPatchInfo::FLAG_REVERSE |
diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStoreFloating.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStoreFloating.cpp
index 08f3550050..c37da385a2 100644
--- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStoreFloating.cpp
+++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStoreFloating.cpp
@@ -73,12 +73,12 @@ void JitArm64::lfXX(UGeckoInstruction inst)
 
 	RegType type = !!(flags & BackPatchInfo::FLAG_SIZE_F64) ? REG_LOWER_PAIR : REG_DUP;
 
-	ARM64Reg VD = fpr.RW(inst.FD, type);
-	ARM64Reg addr_reg = W0;
-
 	gpr.Lock(W0, W30);
 	fpr.Lock(Q0);
 
+	ARM64Reg VD = fpr.RW(inst.FD, type);
+	ARM64Reg addr_reg = W0;
+
 	if (update)
 	{
 		// Always uses RA
@@ -262,12 +262,12 @@ void JitArm64::stfXX(UGeckoInstruction inst)
 	u32 imm_addr = 0;
 	bool is_immediate = false;
 
-	ARM64Reg V0 = fpr.R(inst.FS, REG_IS_LOADED);
-	ARM64Reg addr_reg = W1;
-
 	gpr.Lock(W0, W1, W30);
 	fpr.Lock(Q0);
 
+	ARM64Reg V0 = fpr.R(inst.FS, REG_IS_LOADED);
+	ARM64Reg addr_reg = W1;
+
 	if (update)
 	{
 		// Always uses RA
diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_RegCache.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_RegCache.cpp
index b916c7d2a6..b103f95ed6 100644
--- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_RegCache.cpp
+++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_RegCache.cpp
@@ -167,15 +167,6 @@ void Arm64GPRCache::Flush(FlushMode mode, PPCAnalyst::CodeOp* op)
 	for (int i = 0; i < 32; ++i)
 	{
 		bool flush = true;
-		if (mode == FLUSH_INTERPRETER)
-		{
-			if (!(op->regsOut[i] || op->regsIn[i]))
-			{
-				// This interpreted instruction doesn't use this register
-				flush = false;
-			}
-		}
-
 		if (m_guest_registers[i].GetType() == REG_REG)
 		{
 			// Has to be flushed if it isn't in a callee saved register
diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_RegCache.h b/Source/Core/Core/PowerPC/JitArm64/JitArm64_RegCache.h
index 613b06478f..09f86523ff 100644
--- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_RegCache.h
+++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_RegCache.h
@@ -31,8 +31,6 @@ enum FlushMode
 	// Flushes registers in a conditional branch
 	// Doesn't wipe the state of the registers from the cache
 	FLUSH_MAINTAIN_STATE,
-	// Flushes only the required registers for an interpreter call
-	FLUSH_INTERPRETER,
 };
 
 class OpArg
diff --git a/Source/Core/DolphinWX/MainAndroid.cpp b/Source/Core/DolphinWX/MainAndroid.cpp
index 1d48f5c103..1f6edfe6b3 100644
--- a/Source/Core/DolphinWX/MainAndroid.cpp
+++ b/Source/Core/DolphinWX/MainAndroid.cpp
@@ -397,7 +397,7 @@ JNIEXPORT void JNICALL Java_org_dolphinemu_dolphinemu_NativeLibrary_PauseEmulati
 JNIEXPORT void JNICALL Java_org_dolphinemu_dolphinemu_NativeLibrary_StopEmulation(JNIEnv *env, jobject obj)
 {
 	Core::SaveScreenShot("thumb");
-	Renderer::s_screenshotCompleted.Wait();
+	Renderer::s_screenshotCompleted.WaitFor(std::chrono::seconds(2));
 	Core::Stop();
 	updateMainFrameEvent.Set(); // Kick the waiting event
 }