Merge pull request #10288 from JosJuice/jit64-safe-paired-load
Jit64: Make paired loads always safe
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commit
ddb3bad9c9
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@ -130,22 +130,6 @@ FixupBranch EmuCodeBlock::CheckIfSafeAddress(const OpArg& reg_value, X64Reg reg_
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return J_CC(CC_Z, m_far_code.Enabled());
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}
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void EmuCodeBlock::UnsafeLoadRegToReg(X64Reg reg_addr, X64Reg reg_value, int accessSize, s32 offset,
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bool signExtend)
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{
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OpArg src = MComplex(RMEM, reg_addr, SCALE_1, offset);
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LoadAndSwap(accessSize, reg_value, src, signExtend);
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}
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void EmuCodeBlock::UnsafeLoadRegToRegNoSwap(X64Reg reg_addr, X64Reg reg_value, int accessSize,
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s32 offset, bool signExtend)
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{
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if (signExtend)
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MOVSX(32, accessSize, reg_value, MComplex(RMEM, reg_addr, SCALE_1, offset));
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else
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MOVZX(32, accessSize, reg_value, MComplex(RMEM, reg_addr, SCALE_1, offset));
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}
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void EmuCodeBlock::UnsafeWriteRegToReg(OpArg reg_value, X64Reg reg_addr, int accessSize, s32 offset,
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bool swap, MovInfo* info)
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{
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@ -55,10 +55,6 @@ public:
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Gen::FixupBranch CheckIfSafeAddress(const Gen::OpArg& reg_value, Gen::X64Reg reg_addr,
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BitSet32 registers_in_use);
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void UnsafeLoadRegToReg(Gen::X64Reg reg_addr, Gen::X64Reg reg_value, int accessSize,
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s32 offset = 0, bool signExtend = false);
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void UnsafeLoadRegToRegNoSwap(Gen::X64Reg reg_addr, Gen::X64Reg reg_value, int accessSize,
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s32 offset, bool signExtend = false);
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// these return the address of the MOV, for backpatching
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void UnsafeWriteRegToReg(Gen::OpArg reg_value, Gen::X64Reg reg_addr, int accessSize,
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s32 offset = 0, bool swap = true, Gen::MovInfo* info = nullptr);
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@ -573,7 +573,6 @@ void QuantizedMemoryRoutines::GenQuantizedLoad(bool single, EQuantizeType type,
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int size = sizes[type] * (single ? 1 : 2);
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bool isInline = quantize != -1;
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bool safe_access = m_jit.jo.memcheck || !m_jit.jo.fastmem;
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// illegal
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if (type == QUANTIZE_INVALID1 || type == QUANTIZE_INVALID2 || type == QUANTIZE_INVALID3)
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@ -591,8 +590,6 @@ void QuantizedMemoryRoutines::GenQuantizedLoad(bool single, EQuantizeType type,
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bool extend = single && (type == QUANTIZE_S8 || type == QUANTIZE_S16);
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if (safe_access)
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{
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BitSet32 regsToSave = QUANTIZED_REGS_TO_SAVE_LOAD;
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int flags = isInline ? 0 :
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SAFE_LOADSTORE_NO_FASTMEM | SAFE_LOADSTORE_NO_PROLOG |
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@ -603,23 +600,6 @@ void QuantizedMemoryRoutines::GenQuantizedLoad(bool single, EQuantizeType type,
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// TODO: Support not swapping in safeLoadToReg to avoid bswapping twice
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ROR(16, R(RSCRATCH_EXTRA), Imm8(8));
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}
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}
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else
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{
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switch (type)
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{
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case QUANTIZE_U8:
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case QUANTIZE_S8:
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UnsafeLoadRegToRegNoSwap(RSCRATCH_EXTRA, RSCRATCH_EXTRA, size, 0, extend);
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break;
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case QUANTIZE_U16:
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case QUANTIZE_S16:
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UnsafeLoadRegToReg(RSCRATCH_EXTRA, RSCRATCH_EXTRA, size, 0, extend);
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break;
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default:
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break;
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}
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}
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if (single)
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{
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@ -717,59 +697,21 @@ void QuantizedMemoryRoutines::GenQuantizedLoadFloat(bool single, bool isInline)
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{
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int size = single ? 32 : 64;
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bool extend = false;
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bool safe_access = m_jit.jo.memcheck || !m_jit.jo.fastmem;
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if (safe_access)
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{
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BitSet32 regsToSave = QUANTIZED_REGS_TO_SAVE;
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int flags = isInline ? 0 :
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SAFE_LOADSTORE_NO_FASTMEM | SAFE_LOADSTORE_NO_PROLOG |
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SAFE_LOADSTORE_DR_ON | SAFE_LOADSTORE_NO_UPDATE_PC;
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SafeLoadToReg(RSCRATCH_EXTRA, R(RSCRATCH_EXTRA), size, 0, regsToSave, extend, flags);
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}
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if (single)
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{
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if (safe_access)
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{
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MOVD_xmm(XMM0, R(RSCRATCH_EXTRA));
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}
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else if (cpu_info.bSSSE3)
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{
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MOVD_xmm(XMM0, MRegSum(RMEM, RSCRATCH_EXTRA));
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PSHUFB(XMM0, MConst(pbswapShuffle1x4));
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}
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else
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{
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LoadAndSwap(32, RSCRATCH_EXTRA, MRegSum(RMEM, RSCRATCH_EXTRA));
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MOVD_xmm(XMM0, R(RSCRATCH_EXTRA));
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}
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UNPCKLPS(XMM0, MConst(m_one));
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}
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else
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{
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// FIXME? This code (in non-MMU mode) assumes all accesses are directly to RAM, i.e.
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// don't need hardware access handling. This will definitely crash if paired loads occur
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// from non-RAM areas, but as far as I know, this never happens. I don't know if this is
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// for a good reason, or merely because no game does this.
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// If we find something that actually does do this, maybe this should be changed. How
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// much of a performance hit would it be?
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if (safe_access)
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{
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ROL(64, R(RSCRATCH_EXTRA), Imm8(32));
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MOVQ_xmm(XMM0, R(RSCRATCH_EXTRA));
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}
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else if (cpu_info.bSSSE3)
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{
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MOVQ_xmm(XMM0, MRegSum(RMEM, RSCRATCH_EXTRA));
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PSHUFB(XMM0, MConst(pbswapShuffle2x4));
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}
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else
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{
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LoadAndSwap(64, RSCRATCH_EXTRA, MRegSum(RMEM, RSCRATCH_EXTRA));
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ROL(64, R(RSCRATCH_EXTRA), Imm8(32));
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MOVQ_xmm(XMM0, R(RSCRATCH_EXTRA));
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}
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}
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}
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