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Added the corresponding change from r352ab2ba4394 into JITIL. 

Tidied some code.
This commit is contained in:
skidau 2012-03-13 22:35:11 +11:00
parent 352ab2ba43
commit dc79d68e72
8 changed files with 28 additions and 39 deletions
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1
Source/Core/Core/Src/HW/GPFifo.cpp
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@ -98,7 +98,6 @@ void STACKALIGN CheckGatherPipe()
memmove(m_gatherPipe, m_gatherPipe + cnt, m_gatherPipeCount); memmove(m_gatherPipe, m_gatherPipe + cnt, m_gatherPipeCount);
// Profile where the FIFO writes are occurring. // Profile where the FIFO writes are occurring.
if (jit && (jit->js.fifoWriteAddresses.find(PC)) == (jit->js.fifoWriteAddresses.end())) if (jit && (jit->js.fifoWriteAddresses.find(PC)) == (jit->js.fifoWriteAddresses.end()))
{ {
jit->js.fifoWriteAddresses.insert(PC); jit->js.fifoWriteAddresses.insert(PC);

16
Source/Core/Core/Src/PowerPC/Jit64/Jit.cpp
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@ -42,6 +42,9 @@
#include "JitRegCache.h" #include "JitRegCache.h"
#include "Jit64_Tables.h" #include "Jit64_Tables.h"
#include "HW/ProcessorInterface.h" #include "HW/ProcessorInterface.h"
#if defined(_DEBUG) || defined(DEBUGFAST)
#include "PowerPCDisasm.h"
#endif
using namespace Gen; using namespace Gen;
using namespace PowerPC; using namespace PowerPC;
@ -576,23 +579,22 @@ const u8* Jit64::DoJit(u32 em_address, PPCAnalyst::CodeBuffer *code_buf, JitBloc
gpr.Flush(FLUSH_ALL); gpr.Flush(FLUSH_ALL);
fpr.Flush(FLUSH_ALL); fpr.Flush(FLUSH_ALL);
TEST(32, M((void *)&PowerPC::ppcState.Exceptions), Imm32(EXCEPTION_ISI | EXCEPTION_PROGRAM | EXCEPTION_SYSCALL | EXCEPTION_FPU_UNAVAILABLE | EXCEPTION_DSI | EXCEPTION_ALIGNMENT | EXCEPTION_DECREMENTER)); TEST(32, M((void *)&PowerPC::ppcState.Exceptions), Imm32(EXCEPTION_ISI | EXCEPTION_PROGRAM | EXCEPTION_SYSCALL | EXCEPTION_FPU_UNAVAILABLE | EXCEPTION_DSI | EXCEPTION_ALIGNMENT | EXCEPTION_DECREMENTER));
FixupBranch clearInt = J_CC(CC_NZ); FixupBranch clearInt = J_CC(CC_NZ);
TEST(32, M((void *)&PowerPC::ppcState.Exceptions), Imm32(EXCEPTION_EXTERNAL_INT)); TEST(32, M((void *)&PowerPC::ppcState.Exceptions), Imm32(EXCEPTION_EXTERNAL_INT));
FixupBranch noExtException = J_CC(CC_Z); FixupBranch noExtException = J_CC(CC_Z);
TEST(32, M((void *)&PowerPC::ppcState.msr), Imm32(0x0008000)); TEST(32, M((void *)&PowerPC::ppcState.msr), Imm32(0x0008000));
FixupBranch noCPInt = J_CC(CC_Z); FixupBranch noExtIntEnable = J_CC(CC_Z);
TEST(32, M((void *)&ProcessorInterface::m_InterruptCause), Imm32(ProcessorInterface::INT_CAUSE_CP)); TEST(32, M((void *)&ProcessorInterface::m_InterruptCause), Imm32(ProcessorInterface::INT_CAUSE_CP));
FixupBranch noCPInt2 = J_CC(CC_Z); FixupBranch noCPInt = J_CC(CC_Z);
MOV(32, M(&PC), Imm32(ops[i].address)); MOV(32, M(&PC), Imm32(ops[i].address));
WriteExceptionExit(); WriteExceptionExit();
SetJumpTarget(clearInt);
SetJumpTarget(noCPInt2);
SetJumpTarget(noCPInt); SetJumpTarget(noCPInt);
SetJumpTarget(noExtIntEnable);
SetJumpTarget(noExtException); SetJumpTarget(noExtException);
SetJumpTarget(clearInt);
} }
Jit64Tables::CompileInstruction(ops[i]); Jit64Tables::CompileInstruction(ops[i]);
@ -619,7 +621,7 @@ const u8* Jit64::DoJit(u32 em_address, PPCAnalyst::CodeBuffer *code_buf, JitBloc
{ {
char ppcInst[256]; char ppcInst[256];
DisassembleGekko(ops[i].inst.hex, em_address, ppcInst, 256); DisassembleGekko(ops[i].inst.hex, em_address, ppcInst, 256);
NOTICE_LOG(DYNA_REC, "Unflushed reg: %s", ppcInst); DEBUG_LOG(DYNA_REC, "Unflushed reg: %s", ppcInst);
} }
#endif #endif

7
Source/Core/Core/Src/PowerPC/Jit64IL/IR_X86.cpp
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@ -1925,17 +1925,22 @@ static void DoWriteCode(IRBuilder* ibuild, JitIL* Jit, bool UseProfile, bool Mak
case ExtExceptionCheck: { case ExtExceptionCheck: {
unsigned InstLoc = ibuild->GetImmValue(getOp1(I)); unsigned InstLoc = ibuild->GetImmValue(getOp1(I));
Jit->TEST(32, M((void *)&PowerPC::ppcState.Exceptions), Imm32(EXCEPTION_ISI | EXCEPTION_PROGRAM | EXCEPTION_SYSCALL | EXCEPTION_FPU_UNAVAILABLE | EXCEPTION_DSI | EXCEPTION_ALIGNMENT | EXCEPTION_DECREMENTER));
FixupBranch clearInt = Jit->J_CC(CC_NZ);
Jit->TEST(32, M((void *)&PowerPC::ppcState.Exceptions), Imm32(EXCEPTION_EXTERNAL_INT)); Jit->TEST(32, M((void *)&PowerPC::ppcState.Exceptions), Imm32(EXCEPTION_EXTERNAL_INT));
FixupBranch noExtException = Jit->J_CC(CC_Z); FixupBranch noExtException = Jit->J_CC(CC_Z);
Jit->TEST(32, M((void *)&PowerPC::ppcState.msr), Imm32(0x0008000));
FixupBranch noExtIntEnable = Jit->J_CC(CC_Z);
Jit->TEST(32, M((void *)&ProcessorInterface::m_InterruptCause), Imm32(ProcessorInterface::INT_CAUSE_CP)); Jit->TEST(32, M((void *)&ProcessorInterface::m_InterruptCause), Imm32(ProcessorInterface::INT_CAUSE_CP));
FixupBranch noCPInt = Jit->J_CC(CC_Z); FixupBranch noCPInt = Jit->J_CC(CC_Z);
Jit->MOV(32, M(&PC), Imm32(InstLoc)); Jit->MOV(32, M(&PC), Imm32(InstLoc));
Jit->WriteExceptionExit(); Jit->WriteExceptionExit();
Jit->SetJumpTarget(noCPInt); Jit->SetJumpTarget(noCPInt);
Jit->SetJumpTarget(noExtIntEnable);
Jit->SetJumpTarget(noExtException); Jit->SetJumpTarget(noExtException);
Jit->SetJumpTarget(clearInt);
break; break;
} }
case Int3: { case Int3: {

2
Source/Core/Core/Src/PowerPC/JitCommon/JitBase.cpp
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@ -13,6 +13,8 @@
// If not, see http://www.gnu.org/licenses/ // If not, see http://www.gnu.org/licenses/
#include "JitBase.h" #include "JitBase.h"
#include "PowerPCDisasm.h"
#include "disasm.h"
JitBase *jit; JitBase *jit;

3
Source/Core/Core/Src/PowerPC/JitCommon/JitBase.h
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@ -28,9 +28,6 @@
#include "JitBackpatch.h" // for EmuCodeBlock #include "JitBackpatch.h" // for EmuCodeBlock
#include "JitAsmCommon.h" #include "JitAsmCommon.h"
#include "PowerPCDisasm.h"
#include "disasm.h"
#include <set> #include <set>
#define JIT_OPCODE 0 #define JIT_OPCODE 0

34
Source/Core/VideoCommon/Src/CommandProcessor.cpp
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@ -141,7 +141,6 @@ void Init()
void Read16(u16& _rReturnValue, const u32 _Address) void Read16(u16& _rReturnValue, const u32 _Address)
{ {
INFO_LOG(COMMANDPROCESSOR, "(r): 0x%08x", _Address); INFO_LOG(COMMANDPROCESSOR, "(r): 0x%08x", _Address);
switch (_Address & 0xFFF) switch (_Address & 0xFFF)
{ {
@ -177,7 +176,7 @@ void Read16(u16& _rReturnValue, const u32 _Address)
else else
_rReturnValue = ReadLow (fifo.CPEnd - fifo.CPWritePointer + fifo.SafeCPReadPointer); _rReturnValue = ReadLow (fifo.CPEnd - fifo.CPWritePointer + fifo.SafeCPReadPointer);
else else
_rReturnValue = ReadLow (fifo.CPReadWriteDistance); _rReturnValue = ReadLow (fifo.CPReadWriteDistance);
DEBUG_LOG(COMMANDPROCESSOR, "read FIFO_RW_DISTANCE_LO : %04x", _rReturnValue); DEBUG_LOG(COMMANDPROCESSOR, "read FIFO_RW_DISTANCE_LO : %04x", _rReturnValue);
return; return;
case FIFO_RW_DISTANCE_HI: case FIFO_RW_DISTANCE_HI:
@ -187,7 +186,7 @@ void Read16(u16& _rReturnValue, const u32 _Address)
else else
_rReturnValue = ReadHigh (fifo.CPEnd - fifo.CPWritePointer + fifo.SafeCPReadPointer); _rReturnValue = ReadHigh (fifo.CPEnd - fifo.CPWritePointer + fifo.SafeCPReadPointer);
else else
_rReturnValue = ReadHigh(fifo.CPReadWriteDistance); _rReturnValue = ReadHigh(fifo.CPReadWriteDistance);
DEBUG_LOG(COMMANDPROCESSOR, "read FIFO_RW_DISTANCE_HI : %04x", _rReturnValue); DEBUG_LOG(COMMANDPROCESSOR, "read FIFO_RW_DISTANCE_HI : %04x", _rReturnValue);
return; return;
case FIFO_WRITE_POINTER_LO: case FIFO_WRITE_POINTER_LO:
@ -499,18 +498,15 @@ void AbortFrame()
void SetOverflowStatusFromGatherPipe() void SetOverflowStatusFromGatherPipe()
{ {
fifo.bFF_HiWatermark = (fifo.CPReadWriteDistance > fifo.CPHiWatermark); fifo.bFF_HiWatermark = (fifo.CPReadWriteDistance > fifo.CPHiWatermark);
isHiWatermarkActive = fifo.bFF_HiWatermark && fifo.bFF_HiWatermarkInt && m_CPCtrlReg.GPReadEnable; isHiWatermarkActive = fifo.bFF_HiWatermark && fifo.bFF_HiWatermarkInt && m_CPCtrlReg.GPReadEnable;
if (isHiWatermarkActive) if (isHiWatermarkActive)
{ {
interruptSet = true; interruptSet = true;
INFO_LOG(COMMANDPROCESSOR,"Interrupt set"); INFO_LOG(COMMANDPROCESSOR,"Interrupt set");
ProcessorInterface::SetInterrupt(INT_CAUSE_CP, true); ProcessorInterface::SetInterrupt(INT_CAUSE_CP, true);
} }
} }
void SetCpStatus() void SetCpStatus()
@ -520,12 +516,10 @@ void SetCpStatus()
fifo.bFF_LoWatermark = (fifo.CPReadWriteDistance < fifo.CPLoWatermark); fifo.bFF_LoWatermark = (fifo.CPReadWriteDistance < fifo.CPLoWatermark);
// breakpoint // breakpoint
if (fifo.bFF_BPEnable) if (fifo.bFF_BPEnable)
{ {
if (fifo.CPBreakpoint == fifo.CPReadPointer) if (fifo.CPBreakpoint == fifo.CPReadPointer)
{ {
if (!fifo.bFF_Breakpoint) if (!fifo.bFF_Breakpoint)
{ {
INFO_LOG(COMMANDPROCESSOR, "Hit breakpoint at %i", fifo.CPReadPointer); INFO_LOG(COMMANDPROCESSOR, "Hit breakpoint at %i", fifo.CPReadPointer);
@ -607,15 +601,16 @@ void Shutdown()
void SetCpStatusRegister() void SetCpStatusRegister()
{ {
// Here always there is one fifo attached to the GPU // Here always there is one fifo attached to the GPU
m_CPStatusReg.Breakpoint = fifo.bFF_Breakpoint; m_CPStatusReg.Breakpoint = fifo.bFF_Breakpoint;
m_CPStatusReg.ReadIdle = !fifo.CPReadWriteDistance || (fifo.CPReadPointer == fifo.CPWritePointer) || (fifo.CPReadPointer == fifo.CPBreakpoint) ; m_CPStatusReg.ReadIdle = !fifo.CPReadWriteDistance || (fifo.CPReadPointer == fifo.CPWritePointer) || (fifo.CPReadPointer == fifo.CPBreakpoint) ;
m_CPStatusReg.CommandIdle = !fifo.CPReadWriteDistance; m_CPStatusReg.CommandIdle = !fifo.CPReadWriteDistance;
m_CPStatusReg.UnderflowLoWatermark = fifo.bFF_LoWatermark; m_CPStatusReg.UnderflowLoWatermark = fifo.bFF_LoWatermark;
m_CPStatusReg.OverflowHiWatermark = fifo.bFF_HiWatermark; m_CPStatusReg.OverflowHiWatermark = fifo.bFF_HiWatermark;
PixelEngine::ResumeWaitingForPEInterrupt(); // HACK to compensate for slow response to PE interrupts in Time Splitters: Future Perfect
if (IsOnThread())
PixelEngine::ResumeWaitingForPEInterrupt();
INFO_LOG(COMMANDPROCESSOR,"\t Read from STATUS_REGISTER : %04x", m_CPStatusReg.Hex); INFO_LOG(COMMANDPROCESSOR,"\t Read from STATUS_REGISTER : %04x", m_CPStatusReg.Hex);
DEBUG_LOG(COMMANDPROCESSOR, "(r) status: iBP %s | fReadIdle %s | fCmdIdle %s | iOvF %s | iUndF %s" DEBUG_LOG(COMMANDPROCESSOR, "(r) status: iBP %s | fReadIdle %s | fCmdIdle %s | iOvF %s | iUndF %s"
, m_CPStatusReg.Breakpoint ? "ON" : "OFF" , m_CPStatusReg.Breakpoint ? "ON" : "OFF"
@ -624,13 +619,10 @@ void SetCpStatusRegister()
, m_CPStatusReg.OverflowHiWatermark ? "ON" : "OFF" , m_CPStatusReg.OverflowHiWatermark ? "ON" : "OFF"
, m_CPStatusReg.UnderflowLoWatermark ? "ON" : "OFF" , m_CPStatusReg.UnderflowLoWatermark ? "ON" : "OFF"
); );
} }
void SetCpControlRegister() void SetCpControlRegister()
{ {
// If the new fifo is being attached We make sure there wont be SetFinish event pending. // If the new fifo is being attached We make sure there wont be SetFinish event pending.
// This protection fix eternal darkness booting, because the second SetFinish event when it is booting // This protection fix eternal darkness booting, because the second SetFinish event when it is booting
// seems invalid or has a bug and hang the game. // seems invalid or has a bug and hang the game.
@ -638,7 +630,7 @@ void SetCpControlRegister()
if (!fifo.bFF_GPReadEnable && m_CPCtrlReg.GPReadEnable && !m_CPCtrlReg.BPEnable) if (!fifo.bFF_GPReadEnable && m_CPCtrlReg.GPReadEnable && !m_CPCtrlReg.BPEnable)
{ {
ProcessFifoEvents(); ProcessFifoEvents();
PixelEngine::ResetSetFinish(); PixelEngine::ResetSetFinish();
} }
fifo.bFF_BPInt = m_CPCtrlReg.BPInt; fifo.bFF_BPInt = m_CPCtrlReg.BPInt;
@ -653,9 +645,6 @@ void SetCpControlRegister()
ProcessorInterface::Fifo_CPUBase = fifo.CPBase; ProcessorInterface::Fifo_CPUBase = fifo.CPBase;
ProcessorInterface::Fifo_CPUEnd = fifo.CPEnd; ProcessorInterface::Fifo_CPUEnd = fifo.CPEnd;
} }
// If overflown happens process the fifo to LoWatemark
//if (bProcessFifoToLoWatermark)
// ProcessFifoToLoWatermark();
if(fifo.bFF_GPReadEnable && !m_CPCtrlReg.GPReadEnable) if(fifo.bFF_GPReadEnable && !m_CPCtrlReg.GPReadEnable)
{ {
@ -667,7 +656,6 @@ void SetCpControlRegister()
fifo.bFF_GPReadEnable = m_CPCtrlReg.GPReadEnable; fifo.bFF_GPReadEnable = m_CPCtrlReg.GPReadEnable;
} }
DEBUG_LOG(COMMANDPROCESSOR, "\t GPREAD %s | BP %s | Int %s | OvF %s | UndF %s | LINK %s" DEBUG_LOG(COMMANDPROCESSOR, "\t GPREAD %s | BP %s | Int %s | OvF %s | UndF %s | LINK %s"
, fifo.bFF_GPReadEnable ? "ON" : "OFF" , fifo.bFF_GPReadEnable ? "ON" : "OFF"
, fifo.bFF_BPEnable ? "ON" : "OFF" , fifo.bFF_BPEnable ? "ON" : "OFF"

1
Source/Core/VideoCommon/Src/CommandProcessor.h
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@ -25,7 +25,6 @@ class PointerWrap;
extern bool MT; extern bool MT;
namespace CommandProcessor namespace CommandProcessor
{ {

3
Source/Core/VideoCommon/Src/PixelEngine.cpp
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@ -322,7 +322,6 @@ void Write16(const u16 _iValue, const u32 _iAddress)
break; break;
case PE_TOKEN_REG: case PE_TOKEN_REG:
//LOG(PIXELENGINE,"WEIRD: program wrote token: %i",_iValue);
PanicAlert("(w16) WTF? PowerPC program wrote token: %i", _iValue); PanicAlert("(w16) WTF? PowerPC program wrote token: %i", _iValue);
//only the gx pipeline is supposed to be able to write here //only the gx pipeline is supposed to be able to write here
//g_token = _iValue; //g_token = _iValue;
@ -384,8 +383,6 @@ void SetToken_OnMainThread(u64 userdata, int cyclesLate)
CommandProcessor::interruptTokenWaiting = false; CommandProcessor::interruptTokenWaiting = false;
IncrementCheckContextId(); IncrementCheckContextId();
//} //}
//else
// LOGV(PIXELENGINE, 1, "VIDEO Backend wrote token: %i", CommandProcessor::fifo.PEToken);
} }
void SetFinish_OnMainThread(u64 userdata, int cyclesLate) void SetFinish_OnMainThread(u64 userdata, int cyclesLate)