From db93b516b0295d040780840f6f2a6d6cf1985dbb Mon Sep 17 00:00:00 2001 From: Ryan Houdek Date: Mon, 5 Aug 2013 02:15:25 +0000 Subject: [PATCH] [ARM] Missed flushing our register caches in mtmsr. This would cause a buttload of problems, including the suspected ori being wrong issue. So flush caches and reenable ori. --- Source/Core/Core/Src/PowerPC/JitArm32/JitArm_Integer.cpp | 5 ++--- .../Core/Src/PowerPC/JitArm32/JitArm_SystemRegisters.cpp | 4 ++++ 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_Integer.cpp b/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_Integer.cpp index 3f76d6e526..b05cbffbdd 100644 --- a/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_Integer.cpp +++ b/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_Integer.cpp @@ -123,12 +123,11 @@ void JitArm::mulli(UGeckoInstruction inst) MUL(RD, RA, rA); gpr.Unlock(rA); } -// Wrong 04-08-2013. Breaks Wind Waker booting + void JitArm::ori(UGeckoInstruction inst) { INSTRUCTION_START JITDISABLE(Integer) - Default(inst); return; ARMReg RA = gpr.R(inst.RA); ARMReg RS = gpr.R(inst.RS); @@ -283,7 +282,7 @@ void JitArm::cmpli(UGeckoInstruction inst) gpr.Unlock(rA); } -// Wrong - 27/10/2012 + void JitArm::negx(UGeckoInstruction inst) { INSTRUCTION_START diff --git a/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_SystemRegisters.cpp b/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_SystemRegisters.cpp index cf7535136f..6013d7d66b 100644 --- a/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_SystemRegisters.cpp +++ b/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_SystemRegisters.cpp @@ -105,6 +105,10 @@ void JitArm::mtmsr(UGeckoInstruction inst) //JITDISABLE(SystemRegisters) STR(gpr.R(inst.RS), R9, PPCSTATE_OFF(msr)); + + gpr.Flush(); + fpr.Flush(); + WriteExit(js.compilerPC + 4, 0); } void JitArm::mfmsr(UGeckoInstruction inst)