Merge pull request #11534 from Pokechu22/warning-fixes-feb-2023
Resolve various compiler warnings
This commit is contained in:
commit
dad7a32a35
|
@ -48,6 +48,21 @@ u32 GetMemoryTargetSize(std::string_view instr)
|
|||
|
||||
return 4;
|
||||
}
|
||||
|
||||
bool CompareMemoryTargetToTracked(const std::string& instr, const u32 mem_target,
|
||||
const std::set<u32>& mem_tracked)
|
||||
{
|
||||
// This function is hit often and should be optimized.
|
||||
auto it_lower = std::lower_bound(mem_tracked.begin(), mem_tracked.end(), mem_target);
|
||||
|
||||
if (it_lower == mem_tracked.end())
|
||||
return false;
|
||||
else if (*it_lower == mem_target)
|
||||
return true;
|
||||
|
||||
// If the base value doesn't hit, still need to check if longer values overlap.
|
||||
return *it_lower < mem_target + GetMemoryTargetSize(instr);
|
||||
}
|
||||
} // namespace
|
||||
|
||||
void CodeTrace::SetRegTracked(const std::string& reg)
|
||||
|
@ -124,21 +139,6 @@ TraceOutput CodeTrace::SaveCurrentInstruction() const
|
|||
return output;
|
||||
}
|
||||
|
||||
bool CompareMemoryTargetToTracked(const std::string& instr, const u32 mem_target,
|
||||
const std::set<u32>& mem_tracked)
|
||||
{
|
||||
// This function is hit often and should be optimized.
|
||||
auto it_lower = std::lower_bound(mem_tracked.begin(), mem_tracked.end(), mem_target);
|
||||
|
||||
if (it_lower == mem_tracked.end())
|
||||
return false;
|
||||
else if (*it_lower == mem_target)
|
||||
return true;
|
||||
|
||||
// If the base value doesn't hit, still need to check if longer values overlap.
|
||||
return *it_lower < mem_target + GetMemoryTargetSize(instr);
|
||||
}
|
||||
|
||||
AutoStepResults CodeTrace::AutoStepping(bool continue_previous, AutoStop stop_on)
|
||||
{
|
||||
AutoStepResults results;
|
||||
|
|
|
@ -195,6 +195,7 @@ extern "C" DWORD get_fattime(void)
|
|||
return static_cast<DWORD>(s_callbacks->GetCurrentTimeFAT());
|
||||
}
|
||||
|
||||
#if FF_USE_LFN == 3 // match ff.h; currently unused by Dolphin
|
||||
extern "C" void* ff_memalloc(UINT msize)
|
||||
{
|
||||
return std::malloc(msize);
|
||||
|
@ -204,7 +205,9 @@ extern "C" void ff_memfree(void* mblock)
|
|||
{
|
||||
return std::free(mblock);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if FF_FS_REENTRANT
|
||||
extern "C" int ff_cre_syncobj(BYTE vol, FF_SYNC_t* sobj)
|
||||
{
|
||||
*sobj = new std::recursive_mutex();
|
||||
|
@ -229,6 +232,7 @@ extern "C" int ff_del_syncobj(FF_SYNC_t sobj)
|
|||
delete reinterpret_cast<std::recursive_mutex*>(sobj);
|
||||
return 1;
|
||||
}
|
||||
#endif
|
||||
|
||||
static const char* FatFsErrorToString(FRESULT error_code)
|
||||
{
|
||||
|
|
|
@ -502,8 +502,8 @@ bool CBoot::BootUp(Core::System& system, std::unique_ptr<BootParameters> boot)
|
|||
|
||||
struct BootTitle
|
||||
{
|
||||
BootTitle(Core::System& system, const std::vector<DiscIO::Riivolution::Patch>& patches)
|
||||
: system(system), config(SConfig::GetInstance()), riivolution_patches(patches)
|
||||
BootTitle(Core::System& system_, const std::vector<DiscIO::Riivolution::Patch>& patches)
|
||||
: system(system_), config(SConfig::GetInstance()), riivolution_patches(patches)
|
||||
{
|
||||
}
|
||||
bool operator()(BootParameters::Disc& disc) const
|
||||
|
|
|
@ -101,7 +101,14 @@ void FifoPlaybackAnalyzer::AnalyzeFrames(FifoDataFile* file,
|
|||
part_start = offset;
|
||||
// Copy cpmem now, because end_of_primitives isn't triggered until the first opcode after
|
||||
// primitive data, and the first opcode might update cpmem
|
||||
#ifdef __GNUC__
|
||||
#pragma GCC diagnostic push
|
||||
#pragma GCC diagnostic ignored "-Wclass-memaccess"
|
||||
#endif
|
||||
std::memcpy(&cpmem, &analyzer.m_cpmem, sizeof(CPState));
|
||||
#ifdef __GNUC__
|
||||
#pragma GCC diagnostic pop
|
||||
#endif
|
||||
}
|
||||
if (analyzer.m_end_of_primitives)
|
||||
{
|
||||
|
|
|
@ -292,21 +292,21 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
|
|||
const AICR tmp_ai_ctrl(val);
|
||||
|
||||
auto& core_timing = system.GetCoreTiming();
|
||||
auto& state = system.GetAudioInterfaceState().GetData();
|
||||
if (state.control.AIINTMSK != tmp_ai_ctrl.AIINTMSK)
|
||||
auto& state_ = system.GetAudioInterfaceState().GetData();
|
||||
if (state_.control.AIINTMSK != tmp_ai_ctrl.AIINTMSK)
|
||||
{
|
||||
DEBUG_LOG_FMT(AUDIO_INTERFACE, "Change AIINTMSK to {}", tmp_ai_ctrl.AIINTMSK);
|
||||
state.control.AIINTMSK = tmp_ai_ctrl.AIINTMSK;
|
||||
state_.control.AIINTMSK = tmp_ai_ctrl.AIINTMSK;
|
||||
}
|
||||
|
||||
if (state.control.AIINTVLD != tmp_ai_ctrl.AIINTVLD)
|
||||
if (state_.control.AIINTVLD != tmp_ai_ctrl.AIINTVLD)
|
||||
{
|
||||
DEBUG_LOG_FMT(AUDIO_INTERFACE, "Change AIINTVLD to {}", tmp_ai_ctrl.AIINTVLD);
|
||||
state.control.AIINTVLD = tmp_ai_ctrl.AIINTVLD;
|
||||
state_.control.AIINTVLD = tmp_ai_ctrl.AIINTVLD;
|
||||
}
|
||||
|
||||
// Set frequency of streaming audio
|
||||
if (tmp_ai_ctrl.AISFR != state.control.AISFR)
|
||||
if (tmp_ai_ctrl.AISFR != state_.control.AISFR)
|
||||
{
|
||||
// AISFR rates below are intentionally inverted wrt yagcd
|
||||
DEBUG_LOG_FMT(AUDIO_INTERFACE, "Change AISFR to {}",
|
||||
|
@ -315,7 +315,7 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
|
|||
}
|
||||
|
||||
// Set frequency of DMA
|
||||
if (tmp_ai_ctrl.AIDFR != state.control.AIDFR)
|
||||
if (tmp_ai_ctrl.AIDFR != state_.control.AIDFR)
|
||||
{
|
||||
DEBUG_LOG_FMT(AUDIO_INTERFACE, "Change AIDFR to {}",
|
||||
tmp_ai_ctrl.AIDFR ? "32khz" : "48khz");
|
||||
|
@ -323,31 +323,31 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
|
|||
}
|
||||
|
||||
// Streaming counter
|
||||
if (tmp_ai_ctrl.PSTAT != state.control.PSTAT)
|
||||
if (tmp_ai_ctrl.PSTAT != state_.control.PSTAT)
|
||||
{
|
||||
DEBUG_LOG_FMT(AUDIO_INTERFACE, "{} streaming audio",
|
||||
tmp_ai_ctrl.PSTAT ? "start" : "stop");
|
||||
state.control.PSTAT = tmp_ai_ctrl.PSTAT;
|
||||
state.last_cpu_time = core_timing.GetTicks();
|
||||
state_.control.PSTAT = tmp_ai_ctrl.PSTAT;
|
||||
state_.last_cpu_time = core_timing.GetTicks();
|
||||
|
||||
core_timing.RemoveEvent(state.event_type_ai);
|
||||
core_timing.ScheduleEvent(GetAIPeriod(), state.event_type_ai);
|
||||
core_timing.RemoveEvent(state_.event_type_ai);
|
||||
core_timing.ScheduleEvent(GetAIPeriod(), state_.event_type_ai);
|
||||
}
|
||||
|
||||
// AI Interrupt
|
||||
if (tmp_ai_ctrl.AIINT)
|
||||
{
|
||||
DEBUG_LOG_FMT(AUDIO_INTERFACE, "Clear AIS Interrupt");
|
||||
state.control.AIINT = 0;
|
||||
state_.control.AIINT = 0;
|
||||
}
|
||||
|
||||
// Sample Count Reset
|
||||
if (tmp_ai_ctrl.SCRESET)
|
||||
{
|
||||
DEBUG_LOG_FMT(AUDIO_INTERFACE, "Reset AIS sample counter");
|
||||
state.sample_counter = 0;
|
||||
state_.sample_counter = 0;
|
||||
|
||||
state.last_cpu_time = core_timing.GetTicks();
|
||||
state_.last_cpu_time = core_timing.GetTicks();
|
||||
}
|
||||
|
||||
UpdateInterrupts();
|
||||
|
@ -355,39 +355,39 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
|
|||
|
||||
mmio->Register(base | AI_VOLUME_REGISTER, MMIO::DirectRead<u32>(&state.volume.hex),
|
||||
MMIO::ComplexWrite<u32>([](Core::System& system, u32, u32 val) {
|
||||
auto& state = system.GetAudioInterfaceState().GetData();
|
||||
state.volume.hex = val;
|
||||
auto& state_ = system.GetAudioInterfaceState().GetData();
|
||||
state_.volume.hex = val;
|
||||
SoundStream* sound_stream = system.GetSoundStream();
|
||||
sound_stream->GetMixer()->SetStreamingVolume(state.volume.left,
|
||||
state.volume.right);
|
||||
sound_stream->GetMixer()->SetStreamingVolume(state_.volume.left,
|
||||
state_.volume.right);
|
||||
}));
|
||||
|
||||
mmio->Register(base | AI_SAMPLE_COUNTER, MMIO::ComplexRead<u32>([](Core::System& system, u32) {
|
||||
auto& state = system.GetAudioInterfaceState().GetData();
|
||||
auto& state_ = system.GetAudioInterfaceState().GetData();
|
||||
const u64 cycles_streamed =
|
||||
IsPlaying() ? (system.GetCoreTiming().GetTicks() - state.last_cpu_time) :
|
||||
state.last_cpu_time;
|
||||
return state.sample_counter +
|
||||
static_cast<u32>(cycles_streamed / state.cpu_cycles_per_sample);
|
||||
IsPlaying() ? (system.GetCoreTiming().GetTicks() - state_.last_cpu_time) :
|
||||
state_.last_cpu_time;
|
||||
return state_.sample_counter +
|
||||
static_cast<u32>(cycles_streamed / state_.cpu_cycles_per_sample);
|
||||
}),
|
||||
MMIO::ComplexWrite<u32>([](Core::System& system, u32, u32 val) {
|
||||
auto& core_timing = system.GetCoreTiming();
|
||||
auto& state = system.GetAudioInterfaceState().GetData();
|
||||
state.sample_counter = val;
|
||||
state.last_cpu_time = core_timing.GetTicks();
|
||||
core_timing.RemoveEvent(state.event_type_ai);
|
||||
core_timing.ScheduleEvent(GetAIPeriod(), state.event_type_ai);
|
||||
auto& state_ = system.GetAudioInterfaceState().GetData();
|
||||
state_.sample_counter = val;
|
||||
state_.last_cpu_time = core_timing.GetTicks();
|
||||
core_timing.RemoveEvent(state_.event_type_ai);
|
||||
core_timing.ScheduleEvent(GetAIPeriod(), state_.event_type_ai);
|
||||
}));
|
||||
|
||||
mmio->Register(base | AI_INTERRUPT_TIMING, MMIO::DirectRead<u32>(&state.interrupt_timing),
|
||||
MMIO::ComplexWrite<u32>([](Core::System& system, u32, u32 val) {
|
||||
auto& core_timing = system.GetCoreTiming();
|
||||
auto& state = system.GetAudioInterfaceState().GetData();
|
||||
auto& state_ = system.GetAudioInterfaceState().GetData();
|
||||
DEBUG_LOG_FMT(AUDIO_INTERFACE, "AI_INTERRUPT_TIMING={:08x} at PC: {:08x}", val,
|
||||
system.GetPPCState().pc);
|
||||
state.interrupt_timing = val;
|
||||
core_timing.RemoveEvent(state.event_type_ai);
|
||||
core_timing.ScheduleEvent(GetAIPeriod(), state.event_type_ai);
|
||||
state_.interrupt_timing = val;
|
||||
core_timing.RemoveEvent(state_.event_type_ai);
|
||||
core_timing.ScheduleEvent(GetAIPeriod(), state_.event_type_ai);
|
||||
}));
|
||||
}
|
||||
|
||||
|
|
|
@ -306,86 +306,86 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
|
|||
|
||||
// DSP mail MMIOs call DSP emulator functions to get results or write data.
|
||||
mmio->Register(base | DSP_MAIL_TO_DSP_HI, MMIO::ComplexRead<u16>([](Core::System& system, u32) {
|
||||
auto& state = system.GetDSPState().GetData();
|
||||
if (state.dsp_slice > DSP_MAIL_SLICE && state.is_lle)
|
||||
auto& state_ = system.GetDSPState().GetData();
|
||||
if (state_.dsp_slice > DSP_MAIL_SLICE && state_.is_lle)
|
||||
{
|
||||
state.dsp_emulator->DSP_Update(DSP_MAIL_SLICE);
|
||||
state.dsp_slice -= DSP_MAIL_SLICE;
|
||||
state_.dsp_emulator->DSP_Update(DSP_MAIL_SLICE);
|
||||
state_.dsp_slice -= DSP_MAIL_SLICE;
|
||||
}
|
||||
return state.dsp_emulator->DSP_ReadMailBoxHigh(true);
|
||||
return state_.dsp_emulator->DSP_ReadMailBoxHigh(true);
|
||||
}),
|
||||
MMIO::ComplexWrite<u16>([](Core::System& system, u32, u16 val) {
|
||||
auto& state = system.GetDSPState().GetData();
|
||||
state.dsp_emulator->DSP_WriteMailBoxHigh(true, val);
|
||||
auto& state_ = system.GetDSPState().GetData();
|
||||
state_.dsp_emulator->DSP_WriteMailBoxHigh(true, val);
|
||||
}));
|
||||
mmio->Register(base | DSP_MAIL_TO_DSP_LO, MMIO::ComplexRead<u16>([](Core::System& system, u32) {
|
||||
auto& state = system.GetDSPState().GetData();
|
||||
return state.dsp_emulator->DSP_ReadMailBoxLow(true);
|
||||
auto& state_ = system.GetDSPState().GetData();
|
||||
return state_.dsp_emulator->DSP_ReadMailBoxLow(true);
|
||||
}),
|
||||
MMIO::ComplexWrite<u16>([](Core::System& system, u32, u16 val) {
|
||||
auto& state = system.GetDSPState().GetData();
|
||||
state.dsp_emulator->DSP_WriteMailBoxLow(true, val);
|
||||
auto& state_ = system.GetDSPState().GetData();
|
||||
state_.dsp_emulator->DSP_WriteMailBoxLow(true, val);
|
||||
}));
|
||||
mmio->Register(base | DSP_MAIL_FROM_DSP_HI, MMIO::ComplexRead<u16>([](Core::System& system, u32) {
|
||||
auto& state = system.GetDSPState().GetData();
|
||||
if (state.dsp_slice > DSP_MAIL_SLICE && state.is_lle)
|
||||
auto& state_ = system.GetDSPState().GetData();
|
||||
if (state_.dsp_slice > DSP_MAIL_SLICE && state_.is_lle)
|
||||
{
|
||||
state.dsp_emulator->DSP_Update(DSP_MAIL_SLICE);
|
||||
state.dsp_slice -= DSP_MAIL_SLICE;
|
||||
state_.dsp_emulator->DSP_Update(DSP_MAIL_SLICE);
|
||||
state_.dsp_slice -= DSP_MAIL_SLICE;
|
||||
}
|
||||
return state.dsp_emulator->DSP_ReadMailBoxHigh(false);
|
||||
return state_.dsp_emulator->DSP_ReadMailBoxHigh(false);
|
||||
}),
|
||||
MMIO::InvalidWrite<u16>());
|
||||
mmio->Register(base | DSP_MAIL_FROM_DSP_LO, MMIO::ComplexRead<u16>([](Core::System& system, u32) {
|
||||
auto& state = system.GetDSPState().GetData();
|
||||
return state.dsp_emulator->DSP_ReadMailBoxLow(false);
|
||||
auto& state_ = system.GetDSPState().GetData();
|
||||
return state_.dsp_emulator->DSP_ReadMailBoxLow(false);
|
||||
}),
|
||||
MMIO::InvalidWrite<u16>());
|
||||
|
||||
mmio->Register(
|
||||
base | DSP_CONTROL, MMIO::ComplexRead<u16>([](Core::System& system, u32) {
|
||||
auto& state = system.GetDSPState().GetData();
|
||||
return (state.dsp_control.Hex & ~DSP_CONTROL_MASK) |
|
||||
(state.dsp_emulator->DSP_ReadControlRegister() & DSP_CONTROL_MASK);
|
||||
auto& state_ = system.GetDSPState().GetData();
|
||||
return (state_.dsp_control.Hex & ~DSP_CONTROL_MASK) |
|
||||
(state_.dsp_emulator->DSP_ReadControlRegister() & DSP_CONTROL_MASK);
|
||||
}),
|
||||
MMIO::ComplexWrite<u16>([](Core::System& system, u32, u16 val) {
|
||||
auto& state = system.GetDSPState().GetData();
|
||||
auto& state_ = system.GetDSPState().GetData();
|
||||
|
||||
UDSPControl tmpControl;
|
||||
tmpControl.Hex = (val & ~DSP_CONTROL_MASK) |
|
||||
(state.dsp_emulator->DSP_WriteControlRegister(val) & DSP_CONTROL_MASK);
|
||||
(state_.dsp_emulator->DSP_WriteControlRegister(val) & DSP_CONTROL_MASK);
|
||||
|
||||
// Not really sure if this is correct, but it works...
|
||||
// Kind of a hack because DSP_CONTROL_MASK should make this bit
|
||||
// only viewable to DSP emulator
|
||||
if (val & 1 /*DSPReset*/)
|
||||
{
|
||||
state.audio_dma.AudioDMAControl.Hex = 0;
|
||||
state_.audio_dma.AudioDMAControl.Hex = 0;
|
||||
}
|
||||
|
||||
// Update DSP related flags
|
||||
state.dsp_control.DSPReset = tmpControl.DSPReset;
|
||||
state.dsp_control.DSPAssertInt = tmpControl.DSPAssertInt;
|
||||
state.dsp_control.DSPHalt = tmpControl.DSPHalt;
|
||||
state.dsp_control.DSPInitCode = tmpControl.DSPInitCode;
|
||||
state.dsp_control.DSPInit = tmpControl.DSPInit;
|
||||
state_.dsp_control.DSPReset = tmpControl.DSPReset;
|
||||
state_.dsp_control.DSPAssertInt = tmpControl.DSPAssertInt;
|
||||
state_.dsp_control.DSPHalt = tmpControl.DSPHalt;
|
||||
state_.dsp_control.DSPInitCode = tmpControl.DSPInitCode;
|
||||
state_.dsp_control.DSPInit = tmpControl.DSPInit;
|
||||
|
||||
// Interrupt (mask)
|
||||
state.dsp_control.AID_mask = tmpControl.AID_mask;
|
||||
state.dsp_control.ARAM_mask = tmpControl.ARAM_mask;
|
||||
state.dsp_control.DSP_mask = tmpControl.DSP_mask;
|
||||
state_.dsp_control.AID_mask = tmpControl.AID_mask;
|
||||
state_.dsp_control.ARAM_mask = tmpControl.ARAM_mask;
|
||||
state_.dsp_control.DSP_mask = tmpControl.DSP_mask;
|
||||
|
||||
// Interrupt
|
||||
if (tmpControl.AID)
|
||||
state.dsp_control.AID = 0;
|
||||
state_.dsp_control.AID = 0;
|
||||
if (tmpControl.ARAM)
|
||||
state.dsp_control.ARAM = 0;
|
||||
state_.dsp_control.ARAM = 0;
|
||||
if (tmpControl.DSP)
|
||||
state.dsp_control.DSP = 0;
|
||||
state_.dsp_control.DSP = 0;
|
||||
|
||||
// unknown
|
||||
state.dsp_control.pad = tmpControl.pad;
|
||||
if (state.dsp_control.pad != 0)
|
||||
state_.dsp_control.pad = tmpControl.pad;
|
||||
if (state_.dsp_control.pad != 0)
|
||||
{
|
||||
PanicAlertFmt(
|
||||
"DSPInterface (w) DSP state (CC00500A) gets a value with junk in the padding {:08x}",
|
||||
|
@ -399,17 +399,17 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
|
|||
mmio->Register(base | AR_DMA_CNT_L,
|
||||
MMIO::DirectRead<u16>(MMIO::Utils::LowPart(&state.aram_dma.Cnt.Hex)),
|
||||
MMIO::ComplexWrite<u16>([](Core::System& system, u32, u16 val) {
|
||||
auto& state = system.GetDSPState().GetData();
|
||||
state.aram_dma.Cnt.Hex =
|
||||
(state.aram_dma.Cnt.Hex & 0xFFFF0000) | (val & WMASK_LO_ALIGN_32BIT);
|
||||
auto& state_ = system.GetDSPState().GetData();
|
||||
state_.aram_dma.Cnt.Hex =
|
||||
(state_.aram_dma.Cnt.Hex & 0xFFFF0000) | (val & WMASK_LO_ALIGN_32BIT);
|
||||
Do_ARAM_DMA();
|
||||
}));
|
||||
|
||||
mmio->Register(base | AUDIO_DMA_START_HI,
|
||||
MMIO::DirectRead<u16>(MMIO::Utils::HighPart(&state.audio_dma.SourceAddress)),
|
||||
MMIO::ComplexWrite<u16>([](Core::System& system, u32, u16 val) {
|
||||
auto& state = system.GetDSPState().GetData();
|
||||
*MMIO::Utils::HighPart(&state.audio_dma.SourceAddress) =
|
||||
auto& state_ = system.GetDSPState().GetData();
|
||||
*MMIO::Utils::HighPart(&state_.audio_dma.SourceAddress) =
|
||||
val & (SConfig::GetInstance().bWii ? WMASK_AUDIO_HI_RESTRICT_WII :
|
||||
WMASK_AUDIO_HI_RESTRICT_GCN);
|
||||
}));
|
||||
|
@ -418,25 +418,25 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
|
|||
mmio->Register(
|
||||
base | AUDIO_DMA_CONTROL_LEN, MMIO::DirectRead<u16>(&state.audio_dma.AudioDMAControl.Hex),
|
||||
MMIO::ComplexWrite<u16>([](Core::System& system, u32, u16 val) {
|
||||
auto& state = system.GetDSPState().GetData();
|
||||
bool already_enabled = state.audio_dma.AudioDMAControl.Enable;
|
||||
state.audio_dma.AudioDMAControl.Hex = val;
|
||||
auto& state_ = system.GetDSPState().GetData();
|
||||
bool already_enabled = state_.audio_dma.AudioDMAControl.Enable;
|
||||
state_.audio_dma.AudioDMAControl.Hex = val;
|
||||
|
||||
// Only load new values if we're not already doing a DMA transfer,
|
||||
// otherwise just let the new values be autoloaded in when the
|
||||
// current transfer ends.
|
||||
if (!already_enabled && state.audio_dma.AudioDMAControl.Enable)
|
||||
if (!already_enabled && state_.audio_dma.AudioDMAControl.Enable)
|
||||
{
|
||||
state.audio_dma.current_source_address = state.audio_dma.SourceAddress;
|
||||
state.audio_dma.remaining_blocks_count = state.audio_dma.AudioDMAControl.NumBlocks;
|
||||
state_.audio_dma.current_source_address = state_.audio_dma.SourceAddress;
|
||||
state_.audio_dma.remaining_blocks_count = state_.audio_dma.AudioDMAControl.NumBlocks;
|
||||
|
||||
INFO_LOG_FMT(AUDIO_INTERFACE, "Audio DMA configured: {} blocks from {:#010x}",
|
||||
state.audio_dma.AudioDMAControl.NumBlocks, state.audio_dma.SourceAddress);
|
||||
state_.audio_dma.AudioDMAControl.NumBlocks, state_.audio_dma.SourceAddress);
|
||||
|
||||
// TODO: need hardware tests for the timing of this interrupt.
|
||||
// Sky Crawlers crashes at boot if this is scheduled less than 87 cycles in the future.
|
||||
// Other Namco games crash too, see issue 9509. For now we will just push it to 200 cycles
|
||||
system.GetCoreTiming().ScheduleEvent(200, state.event_type_generate_dsp_interrupt,
|
||||
system.GetCoreTiming().ScheduleEvent(200, state_.event_type_generate_dsp_interrupt,
|
||||
INT_AID);
|
||||
}
|
||||
}));
|
||||
|
@ -447,9 +447,9 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
|
|||
MMIO::ComplexRead<u16>([](Core::System& system, u32) {
|
||||
// remaining_blocks_count is zero-based. DreamMix World Fighters will hang if it
|
||||
// never reaches zero.
|
||||
auto& state = system.GetDSPState().GetData();
|
||||
return (state.audio_dma.remaining_blocks_count > 0 ?
|
||||
state.audio_dma.remaining_blocks_count - 1 :
|
||||
auto& state_ = system.GetDSPState().GetData();
|
||||
return (state_.audio_dma.remaining_blocks_count > 0 ?
|
||||
state_.audio_dma.remaining_blocks_count - 1 :
|
||||
0);
|
||||
}),
|
||||
MMIO::InvalidWrite<u16>());
|
||||
|
|
|
@ -647,24 +647,24 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base, bool is_wii)
|
|||
auto& state = Core::System::GetInstance().GetDVDInterfaceState().GetData();
|
||||
mmio->Register(base | DI_STATUS_REGISTER, MMIO::DirectRead<u32>(&state.DISR.Hex),
|
||||
MMIO::ComplexWrite<u32>([](Core::System& system, u32, u32 val) {
|
||||
auto& state = system.GetDVDInterfaceState().GetData();
|
||||
auto& state_ = system.GetDVDInterfaceState().GetData();
|
||||
const UDISR tmp_status_reg(val);
|
||||
|
||||
state.DISR.DEINTMASK = tmp_status_reg.DEINTMASK.Value();
|
||||
state.DISR.TCINTMASK = tmp_status_reg.TCINTMASK.Value();
|
||||
state.DISR.BRKINTMASK = tmp_status_reg.BRKINTMASK.Value();
|
||||
state.DISR.BREAK = tmp_status_reg.BREAK.Value();
|
||||
state_.DISR.DEINTMASK = tmp_status_reg.DEINTMASK.Value();
|
||||
state_.DISR.TCINTMASK = tmp_status_reg.TCINTMASK.Value();
|
||||
state_.DISR.BRKINTMASK = tmp_status_reg.BRKINTMASK.Value();
|
||||
state_.DISR.BREAK = tmp_status_reg.BREAK.Value();
|
||||
|
||||
if (tmp_status_reg.DEINT)
|
||||
state.DISR.DEINT = 0;
|
||||
state_.DISR.DEINT = 0;
|
||||
|
||||
if (tmp_status_reg.TCINT)
|
||||
state.DISR.TCINT = 0;
|
||||
state_.DISR.TCINT = 0;
|
||||
|
||||
if (tmp_status_reg.BRKINT)
|
||||
state.DISR.BRKINT = 0;
|
||||
state_.DISR.BRKINT = 0;
|
||||
|
||||
if (state.DISR.BREAK)
|
||||
if (state_.DISR.BREAK)
|
||||
{
|
||||
DEBUG_ASSERT(0);
|
||||
}
|
||||
|
@ -674,13 +674,13 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base, bool is_wii)
|
|||
|
||||
mmio->Register(base | DI_COVER_REGISTER, MMIO::DirectRead<u32>(&state.DICVR.Hex),
|
||||
MMIO::ComplexWrite<u32>([](Core::System& system, u32, u32 val) {
|
||||
auto& state = system.GetDVDInterfaceState().GetData();
|
||||
auto& state_ = system.GetDVDInterfaceState().GetData();
|
||||
const UDICVR tmp_cover_reg(val);
|
||||
|
||||
state.DICVR.CVRINTMASK = tmp_cover_reg.CVRINTMASK.Value();
|
||||
state_.DICVR.CVRINTMASK = tmp_cover_reg.CVRINTMASK.Value();
|
||||
|
||||
if (tmp_cover_reg.CVRINT)
|
||||
state.DICVR.CVRINT = 0;
|
||||
state_.DICVR.CVRINT = 0;
|
||||
|
||||
UpdateInterrupts();
|
||||
}));
|
||||
|
@ -712,9 +712,9 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base, bool is_wii)
|
|||
MMIO::DirectWrite<u32>(&state.DILENGTH, ~0x1F));
|
||||
mmio->Register(base | DI_DMA_CONTROL_REGISTER, MMIO::DirectRead<u32>(&state.DICR.Hex),
|
||||
MMIO::ComplexWrite<u32>([](Core::System& system, u32, u32 val) {
|
||||
auto& state = system.GetDVDInterfaceState().GetData();
|
||||
state.DICR.Hex = val & 7;
|
||||
if (state.DICR.TSTART)
|
||||
auto& state_ = system.GetDVDInterfaceState().GetData();
|
||||
state_.DICR.Hex = val & 7;
|
||||
if (state_.DICR.TSTART)
|
||||
{
|
||||
ExecuteCommand(ReplyType::Interrupt);
|
||||
}
|
||||
|
|
|
@ -578,7 +578,7 @@ bool CEXIETHERNET::RecvHandlePacket()
|
|||
off = 0;
|
||||
// avoid increasing the BBA register while copying
|
||||
// sometime the OS can try to process when it's not completed
|
||||
current_rwp = current_rwp == page_ptr(BBA_RHBP) ? page_ptr(BBA_BP) : ++current_rwp;
|
||||
current_rwp = current_rwp == page_ptr(BBA_RHBP) ? page_ptr(BBA_BP) : current_rwp + 1;
|
||||
|
||||
write_ptr = &mBbaMem[current_rwp << 8];
|
||||
|
||||
|
@ -604,7 +604,7 @@ bool CEXIETHERNET::RecvHandlePacket()
|
|||
|
||||
// Align up to next page
|
||||
if ((mRecvBufferLength + 4) % 256)
|
||||
current_rwp = current_rwp == page_ptr(BBA_RHBP) ? page_ptr(BBA_BP) : ++current_rwp;
|
||||
current_rwp = current_rwp == page_ptr(BBA_RHBP) ? page_ptr(BBA_BP) : current_rwp + 1;
|
||||
|
||||
#ifdef BBA_TRACK_PAGE_PTRS
|
||||
INFO_LOG_FMT(SP1, "{:x} {:x} {:x} {:x}", page_ptr(BBA_BP), page_ptr(BBA_RRP), page_ptr(BBA_RWP),
|
||||
|
|
|
@ -728,7 +728,7 @@ void GCMemcardDirectory::DoState(PointerWrap& p)
|
|||
p.Do(m_dir2);
|
||||
p.Do(m_bat1);
|
||||
p.Do(m_bat2);
|
||||
p.DoEachElement(m_saves, [](PointerWrap& p, Memcard::GCIFile& save) { save.DoState(p); });
|
||||
p.DoEachElement(m_saves, [](PointerWrap& p_, Memcard::GCIFile& save) { save.DoState(p_); });
|
||||
}
|
||||
|
||||
void MigrateFromMemcardFile(const std::string& directory_name, ExpansionInterface::Slot card_slot,
|
||||
|
|
|
@ -150,7 +150,14 @@ void Init()
|
|||
{
|
||||
auto& state = Core::System::GetInstance().GetMemoryInterfaceState().GetData();
|
||||
static_assert(std::is_trivially_copyable_v<MIMemStruct>);
|
||||
#ifdef __GNUC__
|
||||
#pragma GCC diagnostic push
|
||||
#pragma GCC diagnostic ignored "-Wclass-memaccess"
|
||||
#endif
|
||||
std::memset(&state.mi_mem, 0, sizeof(MIMemStruct));
|
||||
#ifdef __GNUC__
|
||||
#pragma GCC diagnostic pop
|
||||
#endif
|
||||
}
|
||||
|
||||
void Shutdown()
|
||||
|
|
|
@ -498,15 +498,15 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
|
|||
const u32 address = base | static_cast<u32>(io_buffer_base + i);
|
||||
|
||||
mmio->Register(address, MMIO::ComplexRead<u32>([i](Core::System& system, u32) {
|
||||
auto& state = system.GetSerialInterfaceState().GetData();
|
||||
auto& state_ = system.GetSerialInterfaceState().GetData();
|
||||
u32 val;
|
||||
std::memcpy(&val, &state.si_buffer[i], sizeof(val));
|
||||
std::memcpy(&val, &state_.si_buffer[i], sizeof(val));
|
||||
return Common::swap32(val);
|
||||
}),
|
||||
MMIO::ComplexWrite<u32>([i](Core::System& system, u32, u32 val) {
|
||||
auto& state = system.GetSerialInterfaceState().GetData();
|
||||
auto& state_ = system.GetSerialInterfaceState().GetData();
|
||||
val = Common::swap32(val);
|
||||
std::memcpy(&state.si_buffer[i], &val, sizeof(val));
|
||||
std::memcpy(&state_.si_buffer[i], &val, sizeof(val));
|
||||
}));
|
||||
}
|
||||
for (size_t i = 0; i < state.si_buffer.size(); i += sizeof(u16))
|
||||
|
@ -514,15 +514,15 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
|
|||
const u32 address = base | static_cast<u32>(io_buffer_base + i);
|
||||
|
||||
mmio->Register(address, MMIO::ComplexRead<u16>([i](Core::System& system, u32) {
|
||||
auto& state = system.GetSerialInterfaceState().GetData();
|
||||
auto& state_ = system.GetSerialInterfaceState().GetData();
|
||||
u16 val;
|
||||
std::memcpy(&val, &state.si_buffer[i], sizeof(val));
|
||||
std::memcpy(&val, &state_.si_buffer[i], sizeof(val));
|
||||
return Common::swap16(val);
|
||||
}),
|
||||
MMIO::ComplexWrite<u16>([i](Core::System& system, u32, u16 val) {
|
||||
auto& state = system.GetSerialInterfaceState().GetData();
|
||||
auto& state_ = system.GetSerialInterfaceState().GetData();
|
||||
val = Common::swap16(val);
|
||||
std::memcpy(&state.si_buffer[i], &val, sizeof(val));
|
||||
std::memcpy(&state_.si_buffer[i], &val, sizeof(val));
|
||||
}));
|
||||
}
|
||||
|
||||
|
@ -541,18 +541,18 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
|
|||
MMIO::DirectWrite<u32>(&state.channel[i].out.hex));
|
||||
mmio->Register(base | (SI_CHANNEL_0_IN_HI + 0xC * i),
|
||||
MMIO::ComplexRead<u32>([i, rdst_bit](Core::System& system, u32) {
|
||||
auto& state = system.GetSerialInterfaceState().GetData();
|
||||
state.status_reg.hex &= ~(1U << rdst_bit);
|
||||
auto& state_ = system.GetSerialInterfaceState().GetData();
|
||||
state_.status_reg.hex &= ~(1U << rdst_bit);
|
||||
UpdateInterrupts();
|
||||
return state.channel[i].in_hi.hex;
|
||||
return state_.channel[i].in_hi.hex;
|
||||
}),
|
||||
MMIO::DirectWrite<u32>(&state.channel[i].in_hi.hex));
|
||||
mmio->Register(base | (SI_CHANNEL_0_IN_LO + 0xC * i),
|
||||
MMIO::ComplexRead<u32>([i, rdst_bit](Core::System& system, u32) {
|
||||
auto& state = system.GetSerialInterfaceState().GetData();
|
||||
state.status_reg.hex &= ~(1U << rdst_bit);
|
||||
auto& state_ = system.GetSerialInterfaceState().GetData();
|
||||
state_.status_reg.hex &= ~(1U << rdst_bit);
|
||||
UpdateInterrupts();
|
||||
return state.channel[i].in_lo.hex;
|
||||
return state_.channel[i].in_lo.hex;
|
||||
}),
|
||||
MMIO::DirectWrite<u32>(&state.channel[i].in_lo.hex));
|
||||
}
|
||||
|
@ -562,90 +562,91 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
|
|||
|
||||
mmio->Register(base | SI_COM_CSR, MMIO::DirectRead<u32>(&state.com_csr.hex),
|
||||
MMIO::ComplexWrite<u32>([](Core::System& system, u32, u32 val) {
|
||||
auto& state = system.GetSerialInterfaceState().GetData();
|
||||
auto& state_ = system.GetSerialInterfaceState().GetData();
|
||||
const USIComCSR tmp_com_csr(val);
|
||||
|
||||
state.com_csr.CHANNEL = tmp_com_csr.CHANNEL.Value();
|
||||
state.com_csr.INLNGTH = tmp_com_csr.INLNGTH.Value();
|
||||
state.com_csr.OUTLNGTH = tmp_com_csr.OUTLNGTH.Value();
|
||||
state.com_csr.RDSTINTMSK = tmp_com_csr.RDSTINTMSK.Value();
|
||||
state.com_csr.TCINTMSK = tmp_com_csr.TCINTMSK.Value();
|
||||
state_.com_csr.CHANNEL = tmp_com_csr.CHANNEL.Value();
|
||||
state_.com_csr.INLNGTH = tmp_com_csr.INLNGTH.Value();
|
||||
state_.com_csr.OUTLNGTH = tmp_com_csr.OUTLNGTH.Value();
|
||||
state_.com_csr.RDSTINTMSK = tmp_com_csr.RDSTINTMSK.Value();
|
||||
state_.com_csr.TCINTMSK = tmp_com_csr.TCINTMSK.Value();
|
||||
|
||||
if (tmp_com_csr.RDSTINT)
|
||||
state.com_csr.RDSTINT = 0;
|
||||
state_.com_csr.RDSTINT = 0;
|
||||
if (tmp_com_csr.TCINT)
|
||||
state.com_csr.TCINT = 0;
|
||||
state_.com_csr.TCINT = 0;
|
||||
|
||||
// be careful: run si-buffer after updating the INT flags
|
||||
if (tmp_com_csr.TSTART)
|
||||
{
|
||||
if (state.com_csr.TSTART)
|
||||
system.GetCoreTiming().RemoveEvent(state.event_type_tranfer_pending);
|
||||
state.com_csr.TSTART = 1;
|
||||
if (state_.com_csr.TSTART)
|
||||
system.GetCoreTiming().RemoveEvent(state_.event_type_tranfer_pending);
|
||||
state_.com_csr.TSTART = 1;
|
||||
RunSIBuffer(system, 0, 0);
|
||||
}
|
||||
|
||||
if (!state.com_csr.TSTART)
|
||||
if (!state_.com_csr.TSTART)
|
||||
UpdateInterrupts();
|
||||
}));
|
||||
|
||||
mmio->Register(base | SI_STATUS_REG, MMIO::DirectRead<u32>(&state.status_reg.hex),
|
||||
MMIO::ComplexWrite<u32>([](Core::System& system, u32, u32 val) {
|
||||
auto& state = system.GetSerialInterfaceState().GetData();
|
||||
const USIStatusReg tmp_status(val);
|
||||
mmio->Register(
|
||||
base | SI_STATUS_REG, MMIO::DirectRead<u32>(&state.status_reg.hex),
|
||||
MMIO::ComplexWrite<u32>([](Core::System& system, u32, u32 val) {
|
||||
auto& state_ = system.GetSerialInterfaceState().GetData();
|
||||
const USIStatusReg tmp_status(val);
|
||||
|
||||
// clear bits ( if (tmp.bit) SISR.bit=0 )
|
||||
if (tmp_status.NOREP0)
|
||||
state.status_reg.NOREP0 = 0;
|
||||
if (tmp_status.COLL0)
|
||||
state.status_reg.COLL0 = 0;
|
||||
if (tmp_status.OVRUN0)
|
||||
state.status_reg.OVRUN0 = 0;
|
||||
if (tmp_status.UNRUN0)
|
||||
state.status_reg.UNRUN0 = 0;
|
||||
// clear bits ( if (tmp.bit) SISR.bit=0 )
|
||||
if (tmp_status.NOREP0)
|
||||
state_.status_reg.NOREP0 = 0;
|
||||
if (tmp_status.COLL0)
|
||||
state_.status_reg.COLL0 = 0;
|
||||
if (tmp_status.OVRUN0)
|
||||
state_.status_reg.OVRUN0 = 0;
|
||||
if (tmp_status.UNRUN0)
|
||||
state_.status_reg.UNRUN0 = 0;
|
||||
|
||||
if (tmp_status.NOREP1)
|
||||
state.status_reg.NOREP1 = 0;
|
||||
if (tmp_status.COLL1)
|
||||
state.status_reg.COLL1 = 0;
|
||||
if (tmp_status.OVRUN1)
|
||||
state.status_reg.OVRUN1 = 0;
|
||||
if (tmp_status.UNRUN1)
|
||||
state.status_reg.UNRUN1 = 0;
|
||||
if (tmp_status.NOREP1)
|
||||
state_.status_reg.NOREP1 = 0;
|
||||
if (tmp_status.COLL1)
|
||||
state_.status_reg.COLL1 = 0;
|
||||
if (tmp_status.OVRUN1)
|
||||
state_.status_reg.OVRUN1 = 0;
|
||||
if (tmp_status.UNRUN1)
|
||||
state_.status_reg.UNRUN1 = 0;
|
||||
|
||||
if (tmp_status.NOREP2)
|
||||
state.status_reg.NOREP2 = 0;
|
||||
if (tmp_status.COLL2)
|
||||
state.status_reg.COLL2 = 0;
|
||||
if (tmp_status.OVRUN2)
|
||||
state.status_reg.OVRUN2 = 0;
|
||||
if (tmp_status.UNRUN2)
|
||||
state.status_reg.UNRUN2 = 0;
|
||||
if (tmp_status.NOREP2)
|
||||
state_.status_reg.NOREP2 = 0;
|
||||
if (tmp_status.COLL2)
|
||||
state_.status_reg.COLL2 = 0;
|
||||
if (tmp_status.OVRUN2)
|
||||
state_.status_reg.OVRUN2 = 0;
|
||||
if (tmp_status.UNRUN2)
|
||||
state_.status_reg.UNRUN2 = 0;
|
||||
|
||||
if (tmp_status.NOREP3)
|
||||
state.status_reg.NOREP3 = 0;
|
||||
if (tmp_status.COLL3)
|
||||
state.status_reg.COLL3 = 0;
|
||||
if (tmp_status.OVRUN3)
|
||||
state.status_reg.OVRUN3 = 0;
|
||||
if (tmp_status.UNRUN3)
|
||||
state.status_reg.UNRUN3 = 0;
|
||||
if (tmp_status.NOREP3)
|
||||
state_.status_reg.NOREP3 = 0;
|
||||
if (tmp_status.COLL3)
|
||||
state_.status_reg.COLL3 = 0;
|
||||
if (tmp_status.OVRUN3)
|
||||
state_.status_reg.OVRUN3 = 0;
|
||||
if (tmp_status.UNRUN3)
|
||||
state_.status_reg.UNRUN3 = 0;
|
||||
|
||||
// send command to devices
|
||||
if (tmp_status.WR)
|
||||
{
|
||||
state.channel[0].device->SendCommand(state.channel[0].out.hex, state.poll.EN0);
|
||||
state.channel[1].device->SendCommand(state.channel[1].out.hex, state.poll.EN1);
|
||||
state.channel[2].device->SendCommand(state.channel[2].out.hex, state.poll.EN2);
|
||||
state.channel[3].device->SendCommand(state.channel[3].out.hex, state.poll.EN3);
|
||||
// send command to devices
|
||||
if (tmp_status.WR)
|
||||
{
|
||||
state_.channel[0].device->SendCommand(state_.channel[0].out.hex, state_.poll.EN0);
|
||||
state_.channel[1].device->SendCommand(state_.channel[1].out.hex, state_.poll.EN1);
|
||||
state_.channel[2].device->SendCommand(state_.channel[2].out.hex, state_.poll.EN2);
|
||||
state_.channel[3].device->SendCommand(state_.channel[3].out.hex, state_.poll.EN3);
|
||||
|
||||
state.status_reg.WR = 0;
|
||||
state.status_reg.WRST0 = 0;
|
||||
state.status_reg.WRST1 = 0;
|
||||
state.status_reg.WRST2 = 0;
|
||||
state.status_reg.WRST3 = 0;
|
||||
}
|
||||
}));
|
||||
state_.status_reg.WR = 0;
|
||||
state_.status_reg.WRST0 = 0;
|
||||
state_.status_reg.WRST1 = 0;
|
||||
state_.status_reg.WRST2 = 0;
|
||||
state_.status_reg.WRST3 = 0;
|
||||
}
|
||||
}));
|
||||
|
||||
mmio->Register(base | SI_EXI_CLOCK_COUNT, MMIO::DirectRead<u32>(&state.exi_clock_count.hex),
|
||||
MMIO::DirectWrite<u32>(&state.exi_clock_count.hex));
|
||||
|
|
|
@ -277,38 +277,38 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
|
|||
// XFB related MMIOs that require special handling on writes.
|
||||
mmio->Register(base | VI_FB_LEFT_TOP_HI, MMIO::DirectRead<u16>(&state.xfb_info_top.Hi),
|
||||
MMIO::ComplexWrite<u16>([](Core::System& system, u32, u16 val) {
|
||||
auto& state = system.GetVideoInterfaceState().GetData();
|
||||
state.xfb_info_top.Hi = val;
|
||||
if (state.xfb_info_top.CLRPOFF)
|
||||
state.xfb_info_top.POFF = 0;
|
||||
auto& state_ = system.GetVideoInterfaceState().GetData();
|
||||
state_.xfb_info_top.Hi = val;
|
||||
if (state_.xfb_info_top.CLRPOFF)
|
||||
state_.xfb_info_top.POFF = 0;
|
||||
}));
|
||||
mmio->Register(base | VI_FB_LEFT_BOTTOM_HI, MMIO::DirectRead<u16>(&state.xfb_info_bottom.Hi),
|
||||
MMIO::ComplexWrite<u16>([](Core::System& system, u32, u16 val) {
|
||||
auto& state = system.GetVideoInterfaceState().GetData();
|
||||
state.xfb_info_bottom.Hi = val;
|
||||
if (state.xfb_info_bottom.CLRPOFF)
|
||||
state.xfb_info_bottom.POFF = 0;
|
||||
auto& state_ = system.GetVideoInterfaceState().GetData();
|
||||
state_.xfb_info_bottom.Hi = val;
|
||||
if (state_.xfb_info_bottom.CLRPOFF)
|
||||
state_.xfb_info_bottom.POFF = 0;
|
||||
}));
|
||||
mmio->Register(base | VI_FB_RIGHT_TOP_HI, MMIO::DirectRead<u16>(&state.xfb_3d_info_top.Hi),
|
||||
MMIO::ComplexWrite<u16>([](Core::System& system, u32, u16 val) {
|
||||
auto& state = system.GetVideoInterfaceState().GetData();
|
||||
state.xfb_3d_info_top.Hi = val;
|
||||
if (state.xfb_3d_info_top.CLRPOFF)
|
||||
state.xfb_3d_info_top.POFF = 0;
|
||||
auto& state_ = system.GetVideoInterfaceState().GetData();
|
||||
state_.xfb_3d_info_top.Hi = val;
|
||||
if (state_.xfb_3d_info_top.CLRPOFF)
|
||||
state_.xfb_3d_info_top.POFF = 0;
|
||||
}));
|
||||
mmio->Register(base | VI_FB_RIGHT_BOTTOM_HI, MMIO::DirectRead<u16>(&state.xfb_3d_info_bottom.Hi),
|
||||
MMIO::ComplexWrite<u16>([](Core::System& system, u32, u16 val) {
|
||||
auto& state = system.GetVideoInterfaceState().GetData();
|
||||
state.xfb_3d_info_bottom.Hi = val;
|
||||
if (state.xfb_3d_info_bottom.CLRPOFF)
|
||||
state.xfb_3d_info_bottom.POFF = 0;
|
||||
auto& state_ = system.GetVideoInterfaceState().GetData();
|
||||
state_.xfb_3d_info_bottom.Hi = val;
|
||||
if (state_.xfb_3d_info_bottom.CLRPOFF)
|
||||
state_.xfb_3d_info_bottom.POFF = 0;
|
||||
}));
|
||||
|
||||
// MMIOs with unimplemented writes that trigger warnings.
|
||||
mmio->Register(
|
||||
base | VI_VERTICAL_BEAM_POSITION, MMIO::ComplexRead<u16>([](Core::System& system, u32) {
|
||||
auto& state = system.GetVideoInterfaceState().GetData();
|
||||
return 1 + (state.half_line_count) / 2;
|
||||
auto& state_ = system.GetVideoInterfaceState().GetData();
|
||||
return 1 + (state_.half_line_count) / 2;
|
||||
}),
|
||||
MMIO::ComplexWrite<u16>([](Core::System& system, u32, u16 val) {
|
||||
WARN_LOG_FMT(
|
||||
|
@ -317,12 +317,12 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
|
|||
}));
|
||||
mmio->Register(
|
||||
base | VI_HORIZONTAL_BEAM_POSITION, MMIO::ComplexRead<u16>([](Core::System& system, u32) {
|
||||
auto& state = system.GetVideoInterfaceState().GetData();
|
||||
auto& state_ = system.GetVideoInterfaceState().GetData();
|
||||
u16 value = static_cast<u16>(
|
||||
1 + state.h_timing_0.HLW *
|
||||
(system.GetCoreTiming().GetTicks() - state.ticks_last_line_start) /
|
||||
1 + state_.h_timing_0.HLW *
|
||||
(system.GetCoreTiming().GetTicks() - state_.ticks_last_line_start) /
|
||||
(GetTicksPerHalfLine()));
|
||||
return std::clamp<u16>(value, 1, state.h_timing_0.HLW * 2);
|
||||
return std::clamp<u16>(value, 1, state_.h_timing_0.HLW * 2);
|
||||
}),
|
||||
MMIO::ComplexWrite<u16>([](Core::System& system, u32, u16 val) {
|
||||
WARN_LOG_FMT(
|
||||
|
@ -335,50 +335,50 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
|
|||
// on writes.
|
||||
mmio->Register(base | VI_PRERETRACE_HI, MMIO::DirectRead<u16>(&state.interrupt_register[0].Hi),
|
||||
MMIO::ComplexWrite<u16>([](Core::System& system, u32, u16 val) {
|
||||
auto& state = system.GetVideoInterfaceState().GetData();
|
||||
state.interrupt_register[0].Hi = val;
|
||||
auto& state_ = system.GetVideoInterfaceState().GetData();
|
||||
state_.interrupt_register[0].Hi = val;
|
||||
UpdateInterrupts();
|
||||
}));
|
||||
mmio->Register(base | VI_POSTRETRACE_HI, MMIO::DirectRead<u16>(&state.interrupt_register[1].Hi),
|
||||
MMIO::ComplexWrite<u16>([](Core::System& system, u32, u16 val) {
|
||||
auto& state = system.GetVideoInterfaceState().GetData();
|
||||
state.interrupt_register[1].Hi = val;
|
||||
auto& state_ = system.GetVideoInterfaceState().GetData();
|
||||
state_.interrupt_register[1].Hi = val;
|
||||
UpdateInterrupts();
|
||||
}));
|
||||
mmio->Register(base | VI_DISPLAY_INTERRUPT_2_HI,
|
||||
MMIO::DirectRead<u16>(&state.interrupt_register[2].Hi),
|
||||
MMIO::ComplexWrite<u16>([](Core::System& system, u32, u16 val) {
|
||||
auto& state = system.GetVideoInterfaceState().GetData();
|
||||
state.interrupt_register[2].Hi = val;
|
||||
auto& state_ = system.GetVideoInterfaceState().GetData();
|
||||
state_.interrupt_register[2].Hi = val;
|
||||
UpdateInterrupts();
|
||||
}));
|
||||
mmio->Register(base | VI_DISPLAY_INTERRUPT_3_HI,
|
||||
MMIO::DirectRead<u16>(&state.interrupt_register[3].Hi),
|
||||
MMIO::ComplexWrite<u16>([](Core::System& system, u32, u16 val) {
|
||||
auto& state = system.GetVideoInterfaceState().GetData();
|
||||
state.interrupt_register[3].Hi = val;
|
||||
auto& state_ = system.GetVideoInterfaceState().GetData();
|
||||
state_.interrupt_register[3].Hi = val;
|
||||
UpdateInterrupts();
|
||||
}));
|
||||
|
||||
// Unknown anti-aliasing related MMIO register: puts a warning on log and
|
||||
// needs to shift/mask when reading/writing.
|
||||
mmio->Register(base | VI_UNK_AA_REG_HI, MMIO::ComplexRead<u16>([](Core::System& system, u32) {
|
||||
auto& state = system.GetVideoInterfaceState().GetData();
|
||||
return state.unknown_aa_register >> 16;
|
||||
auto& state_ = system.GetVideoInterfaceState().GetData();
|
||||
return state_.unknown_aa_register >> 16;
|
||||
}),
|
||||
MMIO::ComplexWrite<u16>([](Core::System& system, u32, u16 val) {
|
||||
auto& state = system.GetVideoInterfaceState().GetData();
|
||||
state.unknown_aa_register =
|
||||
(state.unknown_aa_register & 0x0000FFFF) | ((u32)val << 16);
|
||||
auto& state_ = system.GetVideoInterfaceState().GetData();
|
||||
state_.unknown_aa_register =
|
||||
(state_.unknown_aa_register & 0x0000FFFF) | ((u32)val << 16);
|
||||
WARN_LOG_FMT(VIDEOINTERFACE, "Writing to the unknown AA register (hi)");
|
||||
}));
|
||||
mmio->Register(base | VI_UNK_AA_REG_LO, MMIO::ComplexRead<u16>([](Core::System& system, u32) {
|
||||
auto& state = system.GetVideoInterfaceState().GetData();
|
||||
return state.unknown_aa_register & 0xFFFF;
|
||||
auto& state_ = system.GetVideoInterfaceState().GetData();
|
||||
return state_.unknown_aa_register & 0xFFFF;
|
||||
}),
|
||||
MMIO::ComplexWrite<u16>([](Core::System& system, u32, u16 val) {
|
||||
auto& state = system.GetVideoInterfaceState().GetData();
|
||||
state.unknown_aa_register = (state.unknown_aa_register & 0xFFFF0000) | val;
|
||||
auto& state_ = system.GetVideoInterfaceState().GetData();
|
||||
state_.unknown_aa_register = (state_.unknown_aa_register & 0xFFFF0000) | val;
|
||||
WARN_LOG_FMT(VIDEOINTERFACE, "Writing to the unknown AA register (lo)");
|
||||
}));
|
||||
|
||||
|
@ -387,21 +387,21 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
|
|||
mmio->Register(base | VI_CONTROL_REGISTER,
|
||||
MMIO::DirectRead<u16>(&state.display_control_register.Hex),
|
||||
MMIO::ComplexWrite<u16>([](Core::System& system, u32, u16 val) {
|
||||
auto& state = system.GetVideoInterfaceState().GetData();
|
||||
auto& state_ = system.GetVideoInterfaceState().GetData();
|
||||
|
||||
UVIDisplayControlRegister tmpConfig(val);
|
||||
state.display_control_register.ENB = tmpConfig.ENB;
|
||||
state.display_control_register.NIN = tmpConfig.NIN;
|
||||
state.display_control_register.DLR = tmpConfig.DLR;
|
||||
state.display_control_register.LE0 = tmpConfig.LE0;
|
||||
state.display_control_register.LE1 = tmpConfig.LE1;
|
||||
state.display_control_register.FMT = tmpConfig.FMT;
|
||||
state_.display_control_register.ENB = tmpConfig.ENB;
|
||||
state_.display_control_register.NIN = tmpConfig.NIN;
|
||||
state_.display_control_register.DLR = tmpConfig.DLR;
|
||||
state_.display_control_register.LE0 = tmpConfig.LE0;
|
||||
state_.display_control_register.LE1 = tmpConfig.LE1;
|
||||
state_.display_control_register.FMT = tmpConfig.FMT;
|
||||
|
||||
if (tmpConfig.RST)
|
||||
{
|
||||
// shuffle2 clear all data, reset to default vals, and enter idle mode
|
||||
state.display_control_register.RST = 0;
|
||||
state.interrupt_register = {};
|
||||
state_.display_control_register.RST = 0;
|
||||
state_.interrupt_register = {};
|
||||
UpdateInterrupts();
|
||||
}
|
||||
|
||||
|
|
|
@ -136,7 +136,14 @@ static bool DeserializeExtensionState(DesiredWiimoteState* state,
|
|||
return false;
|
||||
auto& e = state->extension.data.emplace<T>();
|
||||
static_assert(std::is_trivially_copyable_v<T>);
|
||||
#ifdef __GNUC__
|
||||
#pragma GCC diagnostic push
|
||||
#pragma GCC diagnostic ignored "-Wclass-memaccess"
|
||||
#endif
|
||||
std::memcpy(&e, &serialized.data[offset], sizeof(T));
|
||||
#ifdef __GNUC__
|
||||
#pragma GCC diagnostic pop
|
||||
#endif
|
||||
return true;
|
||||
}
|
||||
|
||||
|
|
|
@ -120,13 +120,13 @@ void ESDevice::InitializeEmulationState()
|
|||
auto& system = Core::System::GetInstance();
|
||||
auto& core_timing = system.GetCoreTiming();
|
||||
s_finish_init_event = core_timing.RegisterEvent(
|
||||
"IOS-ESFinishInit", [](Core::System& system, u64, s64) { GetIOS()->GetES()->FinishInit(); });
|
||||
"IOS-ESFinishInit", [](Core::System& system_, u64, s64) { GetIOS()->GetES()->FinishInit(); });
|
||||
s_reload_ios_for_ppc_launch_event = core_timing.RegisterEvent(
|
||||
"IOS-ESReloadIOSForPPCLaunch", [](Core::System& system, u64 ios_id, s64) {
|
||||
"IOS-ESReloadIOSForPPCLaunch", [](Core::System& system_, u64 ios_id, s64) {
|
||||
GetIOS()->GetES()->LaunchTitle(ios_id, HangPPC::Yes);
|
||||
});
|
||||
s_bootstrap_ppc_for_launch_event =
|
||||
core_timing.RegisterEvent("IOS-ESBootstrapPPCForLaunch", [](Core::System& system, u64, s64) {
|
||||
core_timing.RegisterEvent("IOS-ESBootstrapPPCForLaunch", [](Core::System& system_, u64, s64) {
|
||||
GetIOS()->GetES()->BootstrapPPC();
|
||||
});
|
||||
}
|
||||
|
|
|
@ -922,7 +922,7 @@ void Init()
|
|||
auto& core_timing = system.GetCoreTiming();
|
||||
|
||||
s_event_enqueue =
|
||||
core_timing.RegisterEvent("IPCEvent", [](Core::System& system, u64 userdata, s64) {
|
||||
core_timing.RegisterEvent("IPCEvent", [](Core::System& system_, u64 userdata, s64) {
|
||||
if (s_ios)
|
||||
s_ios->HandleIPCEvent(userdata);
|
||||
});
|
||||
|
@ -933,7 +933,7 @@ void Init()
|
|||
core_timing.RegisterEvent("IOSFinishPPCBootstrap", FinishPPCBootstrap);
|
||||
|
||||
s_event_finish_ios_boot =
|
||||
core_timing.RegisterEvent("IOSFinishIOSBoot", [](Core::System& system, u64 ios_title_id,
|
||||
core_timing.RegisterEvent("IOSFinishIOSBoot", [](Core::System& system_, u64 ios_title_id,
|
||||
s64) { FinishIOSBoot(ios_title_id); });
|
||||
|
||||
DIDevice::s_finish_executing_di_command =
|
||||
|
|
|
@ -1144,9 +1144,9 @@ void SkylanderPortal::WriteBlock(u8 sky_num, u8 block, const u8* to_write_buf, u
|
|||
}
|
||||
}
|
||||
|
||||
u16 SkylanderCRC16(u16 init_value, const u8* buffer, u32 size)
|
||||
static u16 SkylanderCRC16(u16 init_value, const u8* buffer, u32 size)
|
||||
{
|
||||
const unsigned short CRC_CCITT_TABLE[256] = {
|
||||
static constexpr std::array<u16, 256> CRC_CCITT_TABLE{
|
||||
0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50A5, 0x60C6, 0x70E7, 0x8108, 0x9129, 0xA14A,
|
||||
0xB16B, 0xC18C, 0xD1AD, 0xE1CE, 0xF1EF, 0x1231, 0x0210, 0x3273, 0x2252, 0x52B5, 0x4294,
|
||||
0x72F7, 0x62D6, 0x9339, 0x8318, 0xB37B, 0xA35A, 0xD3BD, 0xC39C, 0xF3FF, 0xE3DE, 0x2462,
|
||||
|
|
|
@ -39,7 +39,7 @@ bool BreakPoints::IsTempBreakPoint(u32 address) const
|
|||
const TBreakPoint* BreakPoints::GetBreakpoint(u32 address) const
|
||||
{
|
||||
auto bp = std::find_if(m_breakpoints.begin(), m_breakpoints.end(),
|
||||
[address](const auto& bp) { return bp.address == address; });
|
||||
[address](const auto& bp_) { return bp_.address == address; });
|
||||
|
||||
if (bp == m_breakpoints.end())
|
||||
return nullptr;
|
||||
|
|
|
@ -223,8 +223,15 @@ struct PowerPCState
|
|||
};
|
||||
|
||||
#if _M_X86_64
|
||||
#ifdef __GNUC__
|
||||
#pragma GCC diagnostic push
|
||||
#pragma GCC diagnostic ignored "-Winvalid-offsetof"
|
||||
#endif
|
||||
static_assert(offsetof(PowerPC::PowerPCState, above_fits_in_first_0x100) <= 0x100,
|
||||
"top of PowerPCState too big");
|
||||
#ifdef __GNUC__
|
||||
#pragma GCC diagnostic pop
|
||||
#endif
|
||||
#endif
|
||||
|
||||
extern PowerPCState ppcState;
|
||||
|
|
|
@ -473,7 +473,7 @@ void SaveAs(const std::string& filename, bool wait)
|
|||
Core::RunOnCPUThread(
|
||||
[&] {
|
||||
{
|
||||
std::lock_guard lk(s_state_writes_in_queue_mutex);
|
||||
std::lock_guard lk_(s_state_writes_in_queue_mutex);
|
||||
++s_state_writes_in_queue;
|
||||
}
|
||||
|
||||
|
@ -515,7 +515,7 @@ void SaveAs(const std::string& filename, bool wait)
|
|||
// someone aborted the save by changing the mode?
|
||||
{
|
||||
// Note: The worker thread takes care of this in the other branch.
|
||||
std::lock_guard lk(s_state_writes_in_queue_mutex);
|
||||
std::lock_guard lk_(s_state_writes_in_queue_mutex);
|
||||
if (--s_state_writes_in_queue == 0)
|
||||
s_state_write_queue_is_empty.notify_all();
|
||||
}
|
||||
|
|
|
@ -110,14 +110,14 @@ void CodeWidget::CreateWidgets()
|
|||
|
||||
auto add_search_line_edit = [this](const QString& name, QListWidget* list_widget) {
|
||||
auto* widget = new QWidget;
|
||||
auto* layout = new QGridLayout;
|
||||
auto* line_layout = new QGridLayout;
|
||||
auto* label = new QLabel(name);
|
||||
auto* search_line_edit = new QLineEdit;
|
||||
|
||||
widget->setLayout(layout);
|
||||
layout->addWidget(label, 0, 0);
|
||||
layout->addWidget(search_line_edit, 0, 1);
|
||||
layout->addWidget(list_widget, 1, 0, -1, -1);
|
||||
widget->setLayout(line_layout);
|
||||
line_layout->addWidget(label, 0, 0);
|
||||
line_layout->addWidget(search_line_edit, 0, 1);
|
||||
line_layout->addWidget(list_widget, 1, 0, -1, -1);
|
||||
m_box_splitter->addWidget(widget);
|
||||
return search_line_edit;
|
||||
};
|
||||
|
|
|
@ -728,6 +728,9 @@ std::vector<u8> MemoryViewWidget::ConvertTextToBytes(Type type, QString input_te
|
|||
}
|
||||
break;
|
||||
}
|
||||
default:
|
||||
// Do nothing
|
||||
break;
|
||||
}
|
||||
|
||||
return {};
|
||||
|
|
|
@ -64,7 +64,7 @@ void SkylanderPortalWindow::CreateMainWindow()
|
|||
checkbox_layout->setAlignment(Qt::AlignHCenter);
|
||||
m_checkbox = new QCheckBox(tr("Emulate Skylander Portal"), this);
|
||||
m_checkbox->setChecked(Config::Get(Config::MAIN_EMULATE_SKYLANDER_PORTAL));
|
||||
connect(m_checkbox, &QCheckBox::toggled, [=](bool checked) { EmulatePortal(checked); });
|
||||
connect(m_checkbox, &QCheckBox::toggled, [&](bool checked) { EmulatePortal(checked); });
|
||||
checkbox_layout->addWidget(m_checkbox);
|
||||
checkbox_group->setLayout(checkbox_layout);
|
||||
main_layout->addWidget(checkbox_group);
|
||||
|
|
|
@ -151,9 +151,9 @@ void KeyboardMouse::SelectEventsForDevice(XIEventMask* mask, int deviceid)
|
|||
}
|
||||
|
||||
KeyboardMouse::KeyboardMouse(Window window, int opcode, int pointer, int keyboard,
|
||||
double scroll_increment)
|
||||
double scroll_increment_)
|
||||
: m_window(window), xi_opcode(opcode), pointer_deviceid(pointer), keyboard_deviceid(keyboard),
|
||||
scroll_increment(scroll_increment)
|
||||
scroll_increment(scroll_increment_)
|
||||
{
|
||||
// The cool thing about each KeyboardMouse object having its own Display
|
||||
// is that each one gets its own separate copy of the X11 event stream,
|
||||
|
|
|
@ -752,7 +752,7 @@ GCPadStatus Input(int chan)
|
|||
}
|
||||
|
||||
// Get ControllerType from first byte in input payload.
|
||||
ControllerType IdentifyControllerType(u8 data)
|
||||
static ControllerType IdentifyControllerType(u8 data)
|
||||
{
|
||||
if (Common::ExtractBit<4>(data))
|
||||
return ControllerType::Wired;
|
||||
|
|
|
@ -24,6 +24,8 @@
|
|||
|
||||
namespace Discord
|
||||
{
|
||||
static bool s_using_custom_client = false;
|
||||
|
||||
#ifdef USE_DISCORD_PRESENCE
|
||||
namespace
|
||||
{
|
||||
|
|
|
@ -27,8 +27,6 @@ enum class SecretType
|
|||
RoomID,
|
||||
};
|
||||
|
||||
static bool s_using_custom_client = false;
|
||||
|
||||
void Init();
|
||||
void InitNetPlayFunctionality(Handler& handler);
|
||||
void CallPendingCallbacks();
|
||||
|
|
|
@ -13,7 +13,7 @@ class Tev
|
|||
struct TevColor
|
||||
{
|
||||
constexpr TevColor() = default;
|
||||
constexpr explicit TevColor(s16 a, s16 b, s16 g, s16 r) : a(a), b(b), g(g), r(r) {}
|
||||
constexpr explicit TevColor(s16 a_, s16 b_, s16 g_, s16 r_) : a(a_), b(b_), g(g_), r(r_) {}
|
||||
|
||||
s16 a = 0;
|
||||
s16 b = 0;
|
||||
|
@ -43,7 +43,10 @@ class Tev
|
|||
|
||||
struct TevColorRef
|
||||
{
|
||||
constexpr explicit TevColorRef(const s16& r, const s16& g, const s16& b) : r(r), g(g), b(b) {}
|
||||
constexpr explicit TevColorRef(const s16& r_, const s16& g_, const s16& b_)
|
||||
: r(r_), g(g_), b(b_)
|
||||
{
|
||||
}
|
||||
|
||||
const s16& r;
|
||||
const s16& g;
|
||||
|
@ -60,15 +63,15 @@ class Tev
|
|||
struct TevAlphaRef
|
||||
{
|
||||
constexpr explicit TevAlphaRef(const TevColor& color) : a(color.a) {}
|
||||
constexpr explicit TevAlphaRef(const s16& a) : a(a) {}
|
||||
constexpr explicit TevAlphaRef(const s16& a_) : a(a_) {}
|
||||
|
||||
const s16& a;
|
||||
};
|
||||
|
||||
struct TevKonstRef
|
||||
{
|
||||
constexpr explicit TevKonstRef(const s16& a, const s16& r, const s16& g, const s16& b)
|
||||
: a(a), r(r), g(g), b(b)
|
||||
constexpr explicit TevKonstRef(const s16& a_, const s16& r_, const s16& g_, const s16& b_)
|
||||
: a(a_), r(r_), g(g_), b(b_)
|
||||
{
|
||||
}
|
||||
|
||||
|
|
|
@ -17,7 +17,14 @@ CPState g_preprocess_cp_state;
|
|||
|
||||
void CopyPreprocessCPStateFromMain()
|
||||
{
|
||||
#ifdef __GNUC__
|
||||
#pragma GCC diagnostic push
|
||||
#pragma GCC diagnostic ignored "-Wclass-memaccess"
|
||||
#endif
|
||||
std::memcpy(&g_preprocess_cp_state, &g_main_cp_state, sizeof(CPState));
|
||||
#ifdef __GNUC__
|
||||
#pragma GCC diagnostic pop
|
||||
#endif
|
||||
}
|
||||
|
||||
std::pair<std::string, std::string> GetCPRegInfo(u8 cmd, u32 value)
|
||||
|
|
|
@ -221,30 +221,30 @@ void CommandProcessorManager::RegisterMMIO(Core::System& system, MMIO::Mapping*
|
|||
MMIO::InvalidWrite<u16>());
|
||||
}
|
||||
|
||||
mmio->Register(base | STATUS_REGISTER, MMIO::ComplexRead<u16>([](Core::System& system, u32) {
|
||||
auto& cp = system.GetCommandProcessor();
|
||||
system.GetFifo().SyncGPUForRegisterAccess(system);
|
||||
cp.SetCpStatusRegister(system);
|
||||
mmio->Register(base | STATUS_REGISTER, MMIO::ComplexRead<u16>([](Core::System& system_, u32) {
|
||||
auto& cp = system_.GetCommandProcessor();
|
||||
system_.GetFifo().SyncGPUForRegisterAccess(system_);
|
||||
cp.SetCpStatusRegister(system_);
|
||||
return cp.m_cp_status_reg.Hex;
|
||||
}),
|
||||
MMIO::InvalidWrite<u16>());
|
||||
|
||||
mmio->Register(base | CTRL_REGISTER, MMIO::DirectRead<u16>(&m_cp_ctrl_reg.Hex),
|
||||
MMIO::ComplexWrite<u16>([](Core::System& system, u32, u16 val) {
|
||||
auto& cp = system.GetCommandProcessor();
|
||||
MMIO::ComplexWrite<u16>([](Core::System& system_, u32, u16 val) {
|
||||
auto& cp = system_.GetCommandProcessor();
|
||||
UCPCtrlReg tmp(val);
|
||||
cp.m_cp_ctrl_reg.Hex = tmp.Hex;
|
||||
cp.SetCpControlRegister(system);
|
||||
system.GetFifo().RunGpu(system);
|
||||
cp.SetCpControlRegister(system_);
|
||||
system_.GetFifo().RunGpu(system_);
|
||||
}));
|
||||
|
||||
mmio->Register(base | CLEAR_REGISTER, MMIO::DirectRead<u16>(&m_cp_clear_reg.Hex),
|
||||
MMIO::ComplexWrite<u16>([](Core::System& system, u32, u16 val) {
|
||||
auto& cp = system.GetCommandProcessor();
|
||||
MMIO::ComplexWrite<u16>([](Core::System& system_, u32, u16 val) {
|
||||
auto& cp = system_.GetCommandProcessor();
|
||||
UCPClearReg tmp(val);
|
||||
cp.m_cp_clear_reg.Hex = tmp.Hex;
|
||||
cp.SetCpClearRegister();
|
||||
system.GetFifo().RunGpu(system);
|
||||
system_.GetFifo().RunGpu(system_);
|
||||
}));
|
||||
|
||||
mmio->Register(base | PERF_SELECT, MMIO::InvalidRead<u16>(), MMIO::Nop<u16>());
|
||||
|
@ -254,20 +254,20 @@ void CommandProcessorManager::RegisterMMIO(Core::System& system, MMIO::Mapping*
|
|||
MMIO::ReadHandlingMethod<u16>* fifo_rw_distance_lo_r;
|
||||
if (is_on_thread)
|
||||
{
|
||||
fifo_rw_distance_lo_r = MMIO::ComplexRead<u16>([](Core::System& system, u32) {
|
||||
const auto& fifo = system.GetCommandProcessor().GetFifo();
|
||||
if (fifo.CPWritePointer.load(std::memory_order_relaxed) >=
|
||||
fifo.SafeCPReadPointer.load(std::memory_order_relaxed))
|
||||
fifo_rw_distance_lo_r = MMIO::ComplexRead<u16>([](Core::System& system_, u32) {
|
||||
const auto& fifo_ = system_.GetCommandProcessor().GetFifo();
|
||||
if (fifo_.CPWritePointer.load(std::memory_order_relaxed) >=
|
||||
fifo_.SafeCPReadPointer.load(std::memory_order_relaxed))
|
||||
{
|
||||
return static_cast<u16>(fifo.CPWritePointer.load(std::memory_order_relaxed) -
|
||||
fifo.SafeCPReadPointer.load(std::memory_order_relaxed));
|
||||
return static_cast<u16>(fifo_.CPWritePointer.load(std::memory_order_relaxed) -
|
||||
fifo_.SafeCPReadPointer.load(std::memory_order_relaxed));
|
||||
}
|
||||
else
|
||||
{
|
||||
return static_cast<u16>(fifo.CPEnd.load(std::memory_order_relaxed) -
|
||||
fifo.SafeCPReadPointer.load(std::memory_order_relaxed) +
|
||||
fifo.CPWritePointer.load(std::memory_order_relaxed) -
|
||||
fifo.CPBase.load(std::memory_order_relaxed) + 32);
|
||||
return static_cast<u16>(fifo_.CPEnd.load(std::memory_order_relaxed) -
|
||||
fifo_.SafeCPReadPointer.load(std::memory_order_relaxed) +
|
||||
fifo_.CPWritePointer.load(std::memory_order_relaxed) -
|
||||
fifo_.CPBase.load(std::memory_order_relaxed) + 32);
|
||||
}
|
||||
});
|
||||
}
|
||||
|
@ -282,40 +282,40 @@ void CommandProcessorManager::RegisterMMIO(Core::System& system, MMIO::Mapping*
|
|||
MMIO::ReadHandlingMethod<u16>* fifo_rw_distance_hi_r;
|
||||
if (is_on_thread)
|
||||
{
|
||||
fifo_rw_distance_hi_r = MMIO::ComplexRead<u16>([](Core::System& system, u32) {
|
||||
const auto& fifo = system.GetCommandProcessor().GetFifo();
|
||||
system.GetFifo().SyncGPUForRegisterAccess(system);
|
||||
if (fifo.CPWritePointer.load(std::memory_order_relaxed) >=
|
||||
fifo.SafeCPReadPointer.load(std::memory_order_relaxed))
|
||||
fifo_rw_distance_hi_r = MMIO::ComplexRead<u16>([](Core::System& system_, u32) {
|
||||
const auto& fifo_ = system_.GetCommandProcessor().GetFifo();
|
||||
system_.GetFifo().SyncGPUForRegisterAccess(system_);
|
||||
if (fifo_.CPWritePointer.load(std::memory_order_relaxed) >=
|
||||
fifo_.SafeCPReadPointer.load(std::memory_order_relaxed))
|
||||
{
|
||||
return (fifo.CPWritePointer.load(std::memory_order_relaxed) -
|
||||
fifo.SafeCPReadPointer.load(std::memory_order_relaxed)) >>
|
||||
return (fifo_.CPWritePointer.load(std::memory_order_relaxed) -
|
||||
fifo_.SafeCPReadPointer.load(std::memory_order_relaxed)) >>
|
||||
16;
|
||||
}
|
||||
else
|
||||
{
|
||||
return (fifo.CPEnd.load(std::memory_order_relaxed) -
|
||||
fifo.SafeCPReadPointer.load(std::memory_order_relaxed) +
|
||||
fifo.CPWritePointer.load(std::memory_order_relaxed) -
|
||||
fifo.CPBase.load(std::memory_order_relaxed) + 32) >>
|
||||
return (fifo_.CPEnd.load(std::memory_order_relaxed) -
|
||||
fifo_.SafeCPReadPointer.load(std::memory_order_relaxed) +
|
||||
fifo_.CPWritePointer.load(std::memory_order_relaxed) -
|
||||
fifo_.CPBase.load(std::memory_order_relaxed) + 32) >>
|
||||
16;
|
||||
}
|
||||
});
|
||||
}
|
||||
else
|
||||
{
|
||||
fifo_rw_distance_hi_r = MMIO::ComplexRead<u16>([](Core::System& system, u32) {
|
||||
const auto& fifo = system.GetCommandProcessor().GetFifo();
|
||||
system.GetFifo().SyncGPUForRegisterAccess(system);
|
||||
return fifo.CPReadWriteDistance.load(std::memory_order_relaxed) >> 16;
|
||||
fifo_rw_distance_hi_r = MMIO::ComplexRead<u16>([](Core::System& system_, u32) {
|
||||
const auto& fifo_ = system_.GetCommandProcessor().GetFifo();
|
||||
system_.GetFifo().SyncGPUForRegisterAccess(system_);
|
||||
return fifo_.CPReadWriteDistance.load(std::memory_order_relaxed) >> 16;
|
||||
});
|
||||
}
|
||||
mmio->Register(base | FIFO_RW_DISTANCE_HI, fifo_rw_distance_hi_r,
|
||||
MMIO::ComplexWrite<u16>([WMASK_HI_RESTRICT](Core::System& system, u32, u16 val) {
|
||||
auto& fifo = system.GetCommandProcessor().GetFifo();
|
||||
system.GetFifo().SyncGPUForRegisterAccess(system);
|
||||
WriteHigh(fifo.CPReadWriteDistance, val & WMASK_HI_RESTRICT);
|
||||
system.GetFifo().RunGpu(system);
|
||||
MMIO::ComplexWrite<u16>([WMASK_HI_RESTRICT](Core::System& system_, u32, u16 val) {
|
||||
auto& fifo_ = system_.GetCommandProcessor().GetFifo();
|
||||
system_.GetFifo().SyncGPUForRegisterAccess(system_);
|
||||
WriteHigh(fifo_.CPReadWriteDistance, val & WMASK_HI_RESTRICT);
|
||||
system_.GetFifo().RunGpu(system_);
|
||||
}));
|
||||
|
||||
mmio->Register(
|
||||
|
@ -328,31 +328,33 @@ void CommandProcessorManager::RegisterMMIO(Core::System& system, MMIO::Mapping*
|
|||
MMIO::WriteHandlingMethod<u16>* fifo_read_hi_w;
|
||||
if (is_on_thread)
|
||||
{
|
||||
fifo_read_hi_r = MMIO::ComplexRead<u16>([](Core::System& system, u32) {
|
||||
auto& fifo = system.GetCommandProcessor().GetFifo();
|
||||
system.GetFifo().SyncGPUForRegisterAccess(system);
|
||||
return fifo.SafeCPReadPointer.load(std::memory_order_relaxed) >> 16;
|
||||
});
|
||||
fifo_read_hi_w = MMIO::ComplexWrite<u16>([WMASK_HI_RESTRICT](Core::System& sys, u32, u16 val) {
|
||||
auto& fifo = sys.GetCommandProcessor().GetFifo();
|
||||
sys.GetFifo().SyncGPUForRegisterAccess(sys);
|
||||
WriteHigh(fifo.CPReadPointer, val & WMASK_HI_RESTRICT);
|
||||
fifo.SafeCPReadPointer.store(fifo.CPReadPointer.load(std::memory_order_relaxed),
|
||||
std::memory_order_relaxed);
|
||||
fifo_read_hi_r = MMIO::ComplexRead<u16>([](Core::System& system_, u32) {
|
||||
auto& fifo_ = system_.GetCommandProcessor().GetFifo();
|
||||
system_.GetFifo().SyncGPUForRegisterAccess(system_);
|
||||
return fifo_.SafeCPReadPointer.load(std::memory_order_relaxed) >> 16;
|
||||
});
|
||||
fifo_read_hi_w =
|
||||
MMIO::ComplexWrite<u16>([WMASK_HI_RESTRICT](Core::System& system_, u32, u16 val) {
|
||||
auto& fifo_ = system_.GetCommandProcessor().GetFifo();
|
||||
system_.GetFifo().SyncGPUForRegisterAccess(system_);
|
||||
WriteHigh(fifo_.CPReadPointer, val & WMASK_HI_RESTRICT);
|
||||
fifo_.SafeCPReadPointer.store(fifo_.CPReadPointer.load(std::memory_order_relaxed),
|
||||
std::memory_order_relaxed);
|
||||
});
|
||||
}
|
||||
else
|
||||
{
|
||||
fifo_read_hi_r = MMIO::ComplexRead<u16>([](Core::System& system, u32) {
|
||||
const auto& fifo = system.GetCommandProcessor().GetFifo();
|
||||
system.GetFifo().SyncGPUForRegisterAccess(system);
|
||||
return fifo.CPReadPointer.load(std::memory_order_relaxed) >> 16;
|
||||
});
|
||||
fifo_read_hi_w = MMIO::ComplexWrite<u16>([WMASK_HI_RESTRICT](Core::System& sys, u32, u16 val) {
|
||||
auto& fifo = sys.GetCommandProcessor().GetFifo();
|
||||
sys.GetFifo().SyncGPUForRegisterAccess(sys);
|
||||
WriteHigh(fifo.CPReadPointer, val & WMASK_HI_RESTRICT);
|
||||
fifo_read_hi_r = MMIO::ComplexRead<u16>([](Core::System& system_, u32) {
|
||||
const auto& fifo_ = system_.GetCommandProcessor().GetFifo();
|
||||
system_.GetFifo().SyncGPUForRegisterAccess(system_);
|
||||
return fifo_.CPReadPointer.load(std::memory_order_relaxed) >> 16;
|
||||
});
|
||||
fifo_read_hi_w =
|
||||
MMIO::ComplexWrite<u16>([WMASK_HI_RESTRICT](Core::System& system_, u32, u16 val) {
|
||||
auto& fifo_ = system_.GetCommandProcessor().GetFifo();
|
||||
system_.GetFifo().SyncGPUForRegisterAccess(system_);
|
||||
WriteHigh(fifo_.CPReadPointer, val & WMASK_HI_RESTRICT);
|
||||
});
|
||||
}
|
||||
mmio->Register(base | FIFO_READ_POINTER_HI, fifo_read_hi_r, fifo_read_hi_w);
|
||||
}
|
||||
|
|
|
@ -195,21 +195,22 @@ void GraphicsModManager::Load(const GraphicsModGroupConfig& config)
|
|||
{
|
||||
for (const GraphicsModFeatureConfig& feature : mod.m_features)
|
||||
{
|
||||
const auto create_action = [](const std::string_view& action_name,
|
||||
const picojson::value& json_data,
|
||||
GraphicsModConfig mod) -> std::unique_ptr<GraphicsModAction> {
|
||||
const auto create_action =
|
||||
[](const std::string_view& action_name, const picojson::value& json_data,
|
||||
GraphicsModConfig mod_config) -> std::unique_ptr<GraphicsModAction> {
|
||||
auto action = GraphicsModActionFactory::Create(action_name, json_data);
|
||||
if (action == nullptr)
|
||||
{
|
||||
return nullptr;
|
||||
}
|
||||
return std::make_unique<DecoratedAction>(std::move(action), std::move(mod));
|
||||
return std::make_unique<DecoratedAction>(std::move(action), std::move(mod_config));
|
||||
};
|
||||
|
||||
const auto internal_group = fmt::format("{}.{}", mod.m_title, feature.m_group);
|
||||
|
||||
const auto add_target = [&](const GraphicsTargetConfig& target, GraphicsModConfig mod) {
|
||||
auto action = create_action(feature.m_action, feature.m_action_data, std::move(mod));
|
||||
const auto add_target = [&](const GraphicsTargetConfig& target,
|
||||
GraphicsModConfig mod_config) {
|
||||
auto action = create_action(feature.m_action, feature.m_action_data, std::move(mod_config));
|
||||
if (action == nullptr)
|
||||
{
|
||||
WARN_LOG_FMT(VIDEO, "Failed to create action '{}' for group '{}'.", feature.m_action,
|
||||
|
|
|
@ -608,7 +608,14 @@ AbstractPipelineConfig ShaderCache::GetGXPipelineConfig(
|
|||
static GXPipelineUid ApplyDriverBugs(const GXPipelineUid& in)
|
||||
{
|
||||
GXPipelineUid out;
|
||||
#ifdef __GNUC__
|
||||
#pragma GCC diagnostic push
|
||||
#pragma GCC diagnostic ignored "-Wclass-memaccess"
|
||||
#endif
|
||||
memcpy(&out, &in, sizeof(out)); // copy padding
|
||||
#ifdef __GNUC__
|
||||
#pragma GCC diagnostic pop
|
||||
#endif
|
||||
pixel_shader_uid_data* ps = out.ps_uid.GetUidData();
|
||||
BlendingState& blend = out.blending_state;
|
||||
|
||||
|
@ -778,7 +785,14 @@ ShaderCache::GetGXPipelineConfig(const GXPipelineUid& config_in)
|
|||
static GXUberPipelineUid ApplyDriverBugs(const GXUberPipelineUid& in)
|
||||
{
|
||||
GXUberPipelineUid out;
|
||||
#ifdef __GNUC__
|
||||
#pragma GCC diagnostic push
|
||||
#pragma GCC diagnostic ignored "-Wclass-memaccess"
|
||||
#endif
|
||||
memcpy(&out, &in, sizeof(out)); // Copy padding
|
||||
#ifdef __GNUC__
|
||||
#pragma GCC diagnostic pop
|
||||
#endif
|
||||
if (g_ActiveConfig.backend_info.bSupportsDynamicVertexLoader)
|
||||
out.vertex_format = nullptr;
|
||||
|
||||
|
|
|
@ -271,7 +271,7 @@ static void TexDecoder_DrawOverlay(u8* dst, int width, int height, TextureFormat
|
|||
for (char ch : fmt_str)
|
||||
{
|
||||
int xcnt = 0;
|
||||
int nchar = sfont_map[ch];
|
||||
int nchar = sfont_map[static_cast<u8>(ch)];
|
||||
|
||||
const unsigned char* ptr = sfont_raw[nchar]; // each char is up to 9x10
|
||||
|
||||
|
|
|
@ -112,8 +112,8 @@ public:
|
|||
|
||||
// Some games (e.g. Donkey Kong Country Returns) have a few draws that contain NaN.
|
||||
// Since NaN != NaN, we need to compare the bits instead.
|
||||
const auto bit_equal = [](float a, float b) {
|
||||
return Common::BitCast<u32>(a) == Common::BitCast<u32>(b);
|
||||
const auto bit_equal = [](float val_a, float val_b) {
|
||||
return Common::BitCast<u32>(val_a) == Common::BitCast<u32>(val_b);
|
||||
};
|
||||
|
||||
// The last element is allowed to be garbage for SIMD overwrites.
|
||||
|
|
|
@ -153,7 +153,14 @@ NativeVertexFormat* GetUberVertexFormat(const PortableVertexDeclaration& decl)
|
|||
// The padding in the structs can cause the memcmp() in the map to create duplicates.
|
||||
// Avoid this by initializing the padding to zero.
|
||||
PortableVertexDeclaration new_decl;
|
||||
#ifdef __GNUC__
|
||||
#pragma GCC diagnostic push
|
||||
#pragma GCC diagnostic ignored "-Wclass-memaccess"
|
||||
#endif
|
||||
std::memset(&new_decl, 0, sizeof(new_decl));
|
||||
#ifdef __GNUC__
|
||||
#pragma GCC diagnostic pop
|
||||
#endif
|
||||
new_decl.stride = decl.stride;
|
||||
|
||||
auto MakeDummyAttribute = [](AttributeFormat& attr, ComponentFormat type, int components,
|
||||
|
|
Loading…
Reference in New Issue