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x64Emitter: Add some single-precision instructions

This commit is contained in:
MerryMage 2018-12-26 00:23:42 +00:00
parent a0673fbb47
commit da7608ff9f
2 changed files with 63 additions and 0 deletions
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51
Source/Core/Common/x64Emitter.cpp
View File

@ -2823,6 +2823,38 @@ void XEmitter::PSHUFHW(X64Reg regOp, const OpArg& arg, u8 shuffle)
} }
// VEX // VEX
void XEmitter::VADDSS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg)
{
WriteAVXOp(0xF3, sseADD, regOp1, regOp2, arg);
}
void XEmitter::VSUBSS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg)
{
WriteAVXOp(0xF3, sseSUB, regOp1, regOp2, arg);
}
void XEmitter::VMULSS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg)
{
WriteAVXOp(0xF3, sseMUL, regOp1, regOp2, arg);
}
void XEmitter::VDIVSS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg)
{
WriteAVXOp(0xF3, sseDIV, regOp1, regOp2, arg);
}
void XEmitter::VADDPS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg)
{
WriteAVXOp(0x00, sseADD, regOp1, regOp2, arg);
}
void XEmitter::VSUBPS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg)
{
WriteAVXOp(0x00, sseSUB, regOp1, regOp2, arg);
}
void XEmitter::VMULPS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg)
{
WriteAVXOp(0x00, sseMUL, regOp1, regOp2, arg);
}
void XEmitter::VDIVPS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg)
{
WriteAVXOp(0x00, sseDIV, regOp1, regOp2, arg);
}
void XEmitter::VADDSD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) void XEmitter::VADDSD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg)
{ {
WriteAVXOp(0xF2, sseADD, regOp1, regOp2, arg); WriteAVXOp(0xF2, sseADD, regOp1, regOp2, arg);
@ -2864,11 +2896,20 @@ void XEmitter::VCMPPD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg, u8 compare
WriteAVXOp(0x66, sseCMP, regOp1, regOp2, arg, 0, 1); WriteAVXOp(0x66, sseCMP, regOp1, regOp2, arg, 0, 1);
Write8(compare); Write8(compare);
} }
void XEmitter::VSHUFPS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg, u8 shuffle)
{
WriteAVXOp(0x00, sseSHUF, regOp1, regOp2, arg, 0, 1);
Write8(shuffle);
}
void XEmitter::VSHUFPD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg, u8 shuffle) void XEmitter::VSHUFPD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg, u8 shuffle)
{ {
WriteAVXOp(0x66, sseSHUF, regOp1, regOp2, arg, 0, 1); WriteAVXOp(0x66, sseSHUF, regOp1, regOp2, arg, 0, 1);
Write8(shuffle); Write8(shuffle);
} }
void XEmitter::VUNPCKLPS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg)
{
WriteAVXOp(0x00, 0x14, regOp1, regOp2, arg);
}
void XEmitter::VUNPCKLPD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) void XEmitter::VUNPCKLPD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg)
{ {
WriteAVXOp(0x66, 0x14, regOp1, regOp2, arg); WriteAVXOp(0x66, 0x14, regOp1, regOp2, arg);
@ -2881,6 +2922,16 @@ void XEmitter::VBLENDVPD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg, X64Reg
{ {
WriteAVXOp4(0x66, 0x3A4B, regOp1, regOp2, arg, regOp3); WriteAVXOp4(0x66, 0x3A4B, regOp1, regOp2, arg, regOp3);
} }
void XEmitter::VBLENDPS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg, u8 blend)
{
WriteAVXOp(0x66, 0x3A0C, regOp1, regOp2, arg, 0, 1);
Write8(blend);
}
void XEmitter::VBLENDPD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg, u8 blend)
{
WriteAVXOp(0x66, 0x3A0D, regOp1, regOp2, arg, 0, 1);
Write8(blend);
}
void XEmitter::VANDPS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) void XEmitter::VANDPS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg)
{ {

12
Source/Core/Common/x64Emitter.h
View File

@ -847,6 +847,14 @@ public:
void BLENDPD(X64Reg dest, const OpArg& arg, u8 blend); void BLENDPD(X64Reg dest, const OpArg& arg, u8 blend);
// AVX // AVX
void VADDSS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
void VSUBSS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
void VMULSS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
void VDIVSS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
void VADDPS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
void VSUBPS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
void VMULPS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
void VDIVPS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
void VADDSD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg); void VADDSD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
void VSUBSD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg); void VSUBSD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
void VMULSD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg); void VMULSD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
@ -857,10 +865,14 @@ public:
void VDIVPD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg); void VDIVPD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
void VSQRTSD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg); void VSQRTSD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
void VCMPPD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg, u8 compare); void VCMPPD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg, u8 compare);
void VSHUFPS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg, u8 shuffle);
void VSHUFPD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg, u8 shuffle); void VSHUFPD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg, u8 shuffle);
void VUNPCKLPS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
void VUNPCKLPD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg); void VUNPCKLPD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
void VUNPCKHPD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg); void VUNPCKHPD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
void VBLENDVPD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg, X64Reg mask); void VBLENDVPD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg, X64Reg mask);
void VBLENDPS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg, u8 blend);
void VBLENDPD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg, u8 blend);
void VANDPS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg); void VANDPS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
void VANDPD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg); void VANDPD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);