Merge pull request #1075 from phire/jitil-fastmem
Fix Fastmem in JitIL for massive speed gains.
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da717bfce4
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@ -577,7 +577,7 @@ static void regEmitMemLoad(RegInfo& RI, InstLoc I, unsigned Size)
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X64Reg reg;
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auto info = regBuildMemAddress(RI, I, getOp1(I), 1, Size, ®);
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RI.Jit->SafeLoadToReg(reg, info.first, Size, info.second, regsInUse(RI), false, EmuCodeBlock::SAFE_LOADSTORE_NO_FASTMEM);
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RI.Jit->SafeLoadToReg(reg, info.first, Size, info.second, regsInUse(RI), false);
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if (regReadUse(RI, I))
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RI.regs[reg] = I;
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}
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@ -619,7 +619,7 @@ static void regEmitMemStore(RegInfo& RI, InstLoc I, unsigned Size)
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RI.Jit->MOV(32, R(RSCRATCH), regLocForInst(RI, getOp1(I)));
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}
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RI.Jit->SafeWriteRegToReg(RSCRATCH, RSCRATCH2, Size, 0, regsInUse(RI), EmuCodeBlock::SAFE_LOADSTORE_NO_FASTMEM);
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RI.Jit->SafeWriteRegToReg(RSCRATCH, RSCRATCH2, Size, 0, regsInUse(RI));
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if (RI.IInfo[I - RI.FirstI] & 4)
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regClearInst(RI, getOp1(I));
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}
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@ -1557,7 +1557,7 @@ static void DoWriteCode(IRBuilder* ibuild, JitIL* Jit, u32 exitAddress)
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X64Reg reg = fregFindFreeReg(RI);
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Jit->MOV(32, R(RSCRATCH2), regLocForInst(RI, getOp1(I)));
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RI.Jit->SafeLoadToReg(RSCRATCH2, R(RSCRATCH2), 32, 0, regsInUse(RI), false, EmuCodeBlock::SAFE_LOADSTORE_NO_FASTMEM);
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RI.Jit->SafeLoadToReg(RSCRATCH2, R(RSCRATCH2), 32, 0, regsInUse(RI), false);
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Jit->MOVD_xmm(reg, R(RSCRATCH2));
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RI.fregs[reg] = I;
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regNormalRegClear(RI, I);
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@ -1571,7 +1571,7 @@ static void DoWriteCode(IRBuilder* ibuild, JitIL* Jit, u32 exitAddress)
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X64Reg reg = fregFindFreeReg(RI);
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const OpArg loc = regLocForInst(RI, getOp1(I));
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Jit->MOV(32, R(RSCRATCH2), loc);
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RI.Jit->SafeLoadToReg(RSCRATCH2, R(RSCRATCH2), 64, 0, regsInUse(RI), false, EmuCodeBlock::SAFE_LOADSTORE_NO_FASTMEM);
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RI.Jit->SafeLoadToReg(RSCRATCH2, R(RSCRATCH2), 64, 0, regsInUse(RI), false);
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Jit->MOVQ_xmm(reg, R(RSCRATCH2));
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RI.fregs[reg] = I;
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regNormalRegClear(RI, I);
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@ -1612,7 +1612,7 @@ static void DoWriteCode(IRBuilder* ibuild, JitIL* Jit, u32 exitAddress)
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Jit->MOV(32, R(RSCRATCH), loc1);
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Jit->MOV(32, R(RSCRATCH2), regLocForInst(RI, getOp2(I)));
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RI.Jit->SafeWriteRegToReg(RSCRATCH, RSCRATCH2, 32, 0, regsInUse(RI), EmuCodeBlock::SAFE_LOADSTORE_NO_FASTMEM);
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RI.Jit->SafeWriteRegToReg(RSCRATCH, RSCRATCH2, 32, 0, regsInUse(RI));
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if (RI.IInfo[I - RI.FirstI] & 4)
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fregClearInst(RI, getOp1(I));
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if (RI.IInfo[I - RI.FirstI] & 8)
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@ -1628,7 +1628,7 @@ static void DoWriteCode(IRBuilder* ibuild, JitIL* Jit, u32 exitAddress)
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Jit->MOVAPD(XMM0, value);
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Jit->MOVQ_xmm(R(RSCRATCH), XMM0);
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Jit->MOV(32, R(RSCRATCH2), address);
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RI.Jit->SafeWriteRegToReg(RSCRATCH, RSCRATCH2, 64, 0, regsInUse(RI), EmuCodeBlock::SAFE_LOADSTORE_NO_FASTMEM);
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RI.Jit->SafeWriteRegToReg(RSCRATCH, RSCRATCH2, 64, 0, regsInUse(RI));
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if (RI.IInfo[I - RI.FirstI] & 4)
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fregClearInst(RI, getOp1(I));
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@ -36,12 +36,8 @@
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#include "Core/PowerPC/JitILCommon/IR.h"
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#include "Core/PowerPC/JitILCommon/JitILBase.h"
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class JitIL : public JitILBase, public EmuCodeBlock
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class JitIL : public JitILBase
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{
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private:
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JitBlockCache blocks;
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TrampolineCache trampolines;
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public:
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Jit64AsmRoutineManager asm_routines;
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@ -60,12 +56,6 @@ public:
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void Trace();
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JitBlockCache *GetBlockCache() override { return &blocks; }
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const u8 *BackPatch(u8 *codePtr, u32 em_address, void *ctx) override { return nullptr; };
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bool IsInCodeSpace(u8 *ptr) override { return IsInSpace(ptr); }
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void ClearCache() override;
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const u8 *GetDispatcher()
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{
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@ -15,7 +15,7 @@
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#include "Core/PowerPC/JitCommon/JitBase.h"
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#include "Core/PowerPC/JitILCommon/IR.h"
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class JitILBase : public JitBase
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class JitILBase : public Jitx86Base
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{
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protected:
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// The default code buffer. We keep it around to not have to alloc/dealloc a
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@ -27,16 +27,10 @@ public:
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IREmitter::IRBuilder ibuild;
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virtual JitBaseBlockCache *GetBlockCache() = 0;
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virtual void Jit(u32 em_address) = 0;
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virtual const u8 *BackPatch(u8 *codePtr, u32 em_address, void *ctx) = 0;
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virtual const CommonAsmRoutinesBase *GetAsmRoutines() = 0;
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virtual bool IsInCodeSpace(u8 *ptr) = 0;
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// OPCODES
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virtual void unknown_instruction(UGeckoInstruction inst) = 0;
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virtual void FallBackToInterpreter(UGeckoInstruction inst) = 0;
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