From 4cc2d972947f59c75cb71737be747aa48f7333a9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?L=C3=A9o=20Lam?= Date: Sun, 5 Jan 2020 01:25:20 +0100 Subject: [PATCH] Require clang-format 9 and reformat source code This updates the lint script to require clang-format 9 and reformats existing source code. Since VS2019 ships with clang-format 9 this should make auto reformats less painful. This also updates the clang-format configuration to set BraceWrapping.AfterCaseLabel to true to ensure consistent brace style; otherwise clang-format 9+ defaults to putting braces on the same line as switch case labels. --- Readme.md | 5 - Source/.clang-format | 1 + Source/Core/Core/IOS/USB/USBV4.cpp | 5 +- .../DolphinQt/Debugger/RegisterWidget.cpp | 143 ++++++++++-------- Tools/lint.sh | 2 +- 5 files changed, 88 insertions(+), 68 deletions(-) diff --git a/Readme.md b/Readme.md index 97bec9e4e4..f448b02d59 100644 --- a/Readme.md +++ b/Readme.md @@ -56,11 +56,6 @@ Installer directory. This will require the Nullsoft Scriptable Install System (NSIS) to be installed. Creating an installer is not necessary to run Dolphin since the Binary directory contains a working Dolphin distribution. -To ease contributing code to Dolphin which has been modified in Visual Studio, -install clang-format-7 by installing a 7.x version of the LLVM tools from http://releases.llvm.org. -In Visual Studio, under Options > Text Editor > C/C++ > Formatting > General, -enable "Use custom clang-format.exe file" and point it to the just-installed clang-format.exe - ## Building for Linux and macOS Dolphin requires [CMake](https://cmake.org/) for systems other than Windows. Many libraries are diff --git a/Source/.clang-format b/Source/.clang-format index c4f102adc1..06a5f10067 100644 --- a/Source/.clang-format +++ b/Source/.clang-format @@ -20,6 +20,7 @@ AlwaysBreakTemplateDeclarations: true BinPackArguments: true BinPackParameters: true BraceWrapping: + AfterCaseLabel: true AfterClass: true AfterControlStatement: true AfterEnum: true diff --git a/Source/Core/Core/IOS/USB/USBV4.cpp b/Source/Core/Core/IOS/USB/USBV4.cpp index 1aae6c6a7b..782dc463b4 100644 --- a/Source/Core/Core/IOS/USB/USBV4.cpp +++ b/Source/Core/Core/IOS/USB/USBV4.cpp @@ -77,8 +77,9 @@ void V4GetUSStringMessage::OnTransferComplete(s32 return_value) const { const std::locale& c_locale = std::locale::classic(); std::string message = Memory::GetString(data_address); - std::replace_if(message.begin(), message.end(), - [&c_locale](char c) { return !std::isprint(c, c_locale); }, '?'); + std::replace_if( + message.begin(), message.end(), [&c_locale](char c) { return !std::isprint(c, c_locale); }, + '?'); Memory::CopyToEmu(data_address, message.c_str(), message.size()); TransferCommand::OnTransferComplete(return_value); } diff --git a/Source/Core/DolphinQt/Debugger/RegisterWidget.cpp b/Source/Core/DolphinQt/Debugger/RegisterWidget.cpp index 1b3511310b..182244969a 100644 --- a/Source/Core/DolphinQt/Debugger/RegisterWidget.cpp +++ b/Source/Core/DolphinQt/Debugger/RegisterWidget.cpp @@ -226,54 +226,64 @@ void RegisterWidget::PopulateTable() for (int i = 0; i < 32; i++) { // General purpose registers (int) - AddRegister(i, 0, RegisterType::gpr, "r" + std::to_string(i), [i] { return GPR(i); }, - [i](u64 value) { GPR(i) = value; }); + AddRegister( + i, 0, RegisterType::gpr, "r" + std::to_string(i), [i] { return GPR(i); }, + [i](u64 value) { GPR(i) = value; }); // Floating point registers (double) - AddRegister(i, 2, RegisterType::fpr, "f" + std::to_string(i), [i] { return rPS(i).PS0AsU64(); }, - [i](u64 value) { rPS(i).SetPS0(value); }); + AddRegister( + i, 2, RegisterType::fpr, "f" + std::to_string(i), [i] { return rPS(i).PS0AsU64(); }, + [i](u64 value) { rPS(i).SetPS0(value); }); - AddRegister(i, 4, RegisterType::fpr, "", [i] { return rPS(i).PS1AsU64(); }, - [i](u64 value) { rPS(i).SetPS1(value); }); + AddRegister( + i, 4, RegisterType::fpr, "", [i] { return rPS(i).PS1AsU64(); }, + [i](u64 value) { rPS(i).SetPS1(value); }); } for (int i = 0; i < 8; i++) { // IBAT registers - AddRegister(i, 5, RegisterType::ibat, "IBAT" + std::to_string(i), - [i] { - return (static_cast(PowerPC::ppcState.spr[SPR_IBAT0U + i * 2]) << 32) + - PowerPC::ppcState.spr[SPR_IBAT0L + i * 2]; - }, - nullptr); + AddRegister( + i, 5, RegisterType::ibat, "IBAT" + std::to_string(i), + [i] { + return (static_cast(PowerPC::ppcState.spr[SPR_IBAT0U + i * 2]) << 32) + + PowerPC::ppcState.spr[SPR_IBAT0L + i * 2]; + }, + nullptr); // DBAT registers - AddRegister(i + 8, 5, RegisterType::dbat, "DBAT" + std::to_string(i), - [i] { - return (static_cast(PowerPC::ppcState.spr[SPR_DBAT0U + i * 2]) << 32) + - PowerPC::ppcState.spr[SPR_DBAT0L + i * 2]; - }, - nullptr); + AddRegister( + i + 8, 5, RegisterType::dbat, "DBAT" + std::to_string(i), + [i] { + return (static_cast(PowerPC::ppcState.spr[SPR_DBAT0U + i * 2]) << 32) + + PowerPC::ppcState.spr[SPR_DBAT0L + i * 2]; + }, + nullptr); // Graphics quantization registers - AddRegister(i + 16, 7, RegisterType::gqr, "GQR" + std::to_string(i), - [i] { return PowerPC::ppcState.spr[SPR_GQR0 + i]; }, nullptr); + AddRegister( + i + 16, 7, RegisterType::gqr, "GQR" + std::to_string(i), + [i] { return PowerPC::ppcState.spr[SPR_GQR0 + i]; }, nullptr); } // HID registers - AddRegister(24, 7, RegisterType::hid, "HID0", [] { return PowerPC::ppcState.spr[SPR_HID0]; }, - [](u64 value) { PowerPC::ppcState.spr[SPR_HID0] = static_cast(value); }); - AddRegister(25, 7, RegisterType::hid, "HID1", [] { return PowerPC::ppcState.spr[SPR_HID1]; }, - [](u64 value) { PowerPC::ppcState.spr[SPR_HID1] = static_cast(value); }); - AddRegister(26, 7, RegisterType::hid, "HID2", [] { return PowerPC::ppcState.spr[SPR_HID2]; }, - [](u64 value) { PowerPC::ppcState.spr[SPR_HID2] = static_cast(value); }); - AddRegister(27, 7, RegisterType::hid, "HID4", [] { return PowerPC::ppcState.spr[SPR_HID4]; }, - [](u64 value) { PowerPC::ppcState.spr[SPR_HID4] = static_cast(value); }); + AddRegister( + 24, 7, RegisterType::hid, "HID0", [] { return PowerPC::ppcState.spr[SPR_HID0]; }, + [](u64 value) { PowerPC::ppcState.spr[SPR_HID0] = static_cast(value); }); + AddRegister( + 25, 7, RegisterType::hid, "HID1", [] { return PowerPC::ppcState.spr[SPR_HID1]; }, + [](u64 value) { PowerPC::ppcState.spr[SPR_HID1] = static_cast(value); }); + AddRegister( + 26, 7, RegisterType::hid, "HID2", [] { return PowerPC::ppcState.spr[SPR_HID2]; }, + [](u64 value) { PowerPC::ppcState.spr[SPR_HID2] = static_cast(value); }); + AddRegister( + 27, 7, RegisterType::hid, "HID4", [] { return PowerPC::ppcState.spr[SPR_HID4]; }, + [](u64 value) { PowerPC::ppcState.spr[SPR_HID4] = static_cast(value); }); for (int i = 0; i < 16; i++) { // SR registers - AddRegister(i, 7, RegisterType::sr, "SR" + std::to_string(i), - [i] { return PowerPC::ppcState.sr[i]; }, - [i](u64 value) { PowerPC::ppcState.sr[i] = value; }); + AddRegister( + i, 7, RegisterType::sr, "SR" + std::to_string(i), [i] { return PowerPC::ppcState.sr[i]; }, + [i](u64 value) { PowerPC::ppcState.sr[i] = value; }); } // Special registers @@ -281,58 +291,71 @@ void RegisterWidget::PopulateTable() AddRegister(16, 5, RegisterType::tb, "TB", PowerPC::ReadFullTimeBaseValue, nullptr); // PC - AddRegister(17, 5, RegisterType::pc, "PC", [] { return PowerPC::ppcState.pc; }, - [](u64 value) { PowerPC::ppcState.pc = value; }); + AddRegister( + 17, 5, RegisterType::pc, "PC", [] { return PowerPC::ppcState.pc; }, + [](u64 value) { PowerPC::ppcState.pc = value; }); // LR - AddRegister(18, 5, RegisterType::lr, "LR", [] { return PowerPC::ppcState.spr[SPR_LR]; }, - [](u64 value) { PowerPC::ppcState.spr[SPR_LR] = value; }); + AddRegister( + 18, 5, RegisterType::lr, "LR", [] { return PowerPC::ppcState.spr[SPR_LR]; }, + [](u64 value) { PowerPC::ppcState.spr[SPR_LR] = value; }); // CTR - AddRegister(19, 5, RegisterType::ctr, "CTR", [] { return PowerPC::ppcState.spr[SPR_CTR]; }, - [](u64 value) { PowerPC::ppcState.spr[SPR_CTR] = value; }); + AddRegister( + 19, 5, RegisterType::ctr, "CTR", [] { return PowerPC::ppcState.spr[SPR_CTR]; }, + [](u64 value) { PowerPC::ppcState.spr[SPR_CTR] = value; }); // CR - AddRegister(20, 5, RegisterType::cr, "CR", [] { return PowerPC::ppcState.cr.Get(); }, - [](u64 value) { PowerPC::ppcState.cr.Set(value); }); + AddRegister( + 20, 5, RegisterType::cr, "CR", [] { return PowerPC::ppcState.cr.Get(); }, + [](u64 value) { PowerPC::ppcState.cr.Set(value); }); // XER - AddRegister(21, 5, RegisterType::xer, "XER", [] { return PowerPC::GetXER().Hex; }, - [](u64 value) { PowerPC::SetXER(UReg_XER(value)); }); + AddRegister( + 21, 5, RegisterType::xer, "XER", [] { return PowerPC::GetXER().Hex; }, + [](u64 value) { PowerPC::SetXER(UReg_XER(value)); }); // FPSCR - AddRegister(22, 5, RegisterType::fpscr, "FPSCR", [] { return PowerPC::ppcState.fpscr.Hex; }, - [](u64 value) { PowerPC::ppcState.fpscr = static_cast(value); }); + AddRegister( + 22, 5, RegisterType::fpscr, "FPSCR", [] { return PowerPC::ppcState.fpscr.Hex; }, + [](u64 value) { PowerPC::ppcState.fpscr = static_cast(value); }); // MSR - AddRegister(23, 5, RegisterType::msr, "MSR", [] { return PowerPC::ppcState.msr.Hex; }, - [](u64 value) { PowerPC::ppcState.msr.Hex = value; }); + AddRegister( + 23, 5, RegisterType::msr, "MSR", [] { return PowerPC::ppcState.msr.Hex; }, + [](u64 value) { PowerPC::ppcState.msr.Hex = value; }); // SRR 0-1 - AddRegister(24, 5, RegisterType::srr, "SRR0", [] { return PowerPC::ppcState.spr[SPR_SRR0]; }, - [](u64 value) { PowerPC::ppcState.spr[SPR_SRR0] = value; }); - AddRegister(25, 5, RegisterType::srr, "SRR1", [] { return PowerPC::ppcState.spr[SPR_SRR1]; }, - [](u64 value) { PowerPC::ppcState.spr[SPR_SRR1] = value; }); + AddRegister( + 24, 5, RegisterType::srr, "SRR0", [] { return PowerPC::ppcState.spr[SPR_SRR0]; }, + [](u64 value) { PowerPC::ppcState.spr[SPR_SRR0] = value; }); + AddRegister( + 25, 5, RegisterType::srr, "SRR1", [] { return PowerPC::ppcState.spr[SPR_SRR1]; }, + [](u64 value) { PowerPC::ppcState.spr[SPR_SRR1] = value; }); // Exceptions - AddRegister(26, 5, RegisterType::exceptions, "Exceptions", - [] { return PowerPC::ppcState.Exceptions; }, - [](u64 value) { PowerPC::ppcState.Exceptions = value; }); + AddRegister( + 26, 5, RegisterType::exceptions, "Exceptions", [] { return PowerPC::ppcState.Exceptions; }, + [](u64 value) { PowerPC::ppcState.Exceptions = value; }); // Int Mask - AddRegister(27, 5, RegisterType::int_mask, "Int Mask", - [] { return ProcessorInterface::GetMask(); }, nullptr); + AddRegister( + 27, 5, RegisterType::int_mask, "Int Mask", [] { return ProcessorInterface::GetMask(); }, + nullptr); // Int Cause - AddRegister(28, 5, RegisterType::int_cause, "Int Cause", - [] { return ProcessorInterface::GetCause(); }, nullptr); + AddRegister( + 28, 5, RegisterType::int_cause, "Int Cause", [] { return ProcessorInterface::GetCause(); }, + nullptr); // DSISR - AddRegister(29, 5, RegisterType::dsisr, "DSISR", [] { return PowerPC::ppcState.spr[SPR_DSISR]; }, - [](u64 value) { PowerPC::ppcState.spr[SPR_DSISR] = value; }); + AddRegister( + 29, 5, RegisterType::dsisr, "DSISR", [] { return PowerPC::ppcState.spr[SPR_DSISR]; }, + [](u64 value) { PowerPC::ppcState.spr[SPR_DSISR] = value; }); // DAR - AddRegister(30, 5, RegisterType::dar, "DAR", [] { return PowerPC::ppcState.spr[SPR_DAR]; }, - [](u64 value) { PowerPC::ppcState.spr[SPR_DAR] = value; }); + AddRegister( + 30, 5, RegisterType::dar, "DAR", [] { return PowerPC::ppcState.spr[SPR_DAR]; }, + [](u64 value) { PowerPC::ppcState.spr[SPR_DAR] = value; }); // Hash Mask AddRegister( diff --git a/Tools/lint.sh b/Tools/lint.sh index ad41c8e666..31adf33452 100755 --- a/Tools/lint.sh +++ b/Tools/lint.sh @@ -9,7 +9,7 @@ if ! [ -x "$(command -v git)" ]; then exit 1 fi -REQUIRED_CLANG_FORMAT_MAJOR=7 +REQUIRED_CLANG_FORMAT_MAJOR=9 REQUIRED_CLANG_FORMAT_MINOR=0 CLANG_FORMAT=clang-format CLANG_FORMAT_MAJOR=clang-format-${REQUIRED_CLANG_FORMAT_MAJOR}