Adds new PPCAnalyser class.
Supports conditional branch continuation. More features to come.
This commit is contained in:
Ryan Houdek
parent
664496a2a8
commit
da2ed2e17d
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@ -699,4 +699,317 @@ void FindFunctions(u32 startAddr, u32 endAddr, PPCSymbolDB *func_db)
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leafSize, niceSize, unniceSize);
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leafSize, niceSize, unniceSize);
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}
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}
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void PPCAnalyser::ReorderInstructions(u32 instructions, CodeOp *code)
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{
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// Instruction Reordering Pass
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// Bubble down compares towards branches, so that they can be merged.
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// -2: -1 for the pair, -1 for not swapping with the final instruction which is probably the branch.
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for (u32 i = 0; i < (instructions - 2); ++i)
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{
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CodeOp &a = code[i];
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CodeOp &b = code[i + 1];
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// All integer compares can be reordered.
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if ((a.inst.OPCD == 10 || a.inst.OPCD == 11) ||
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(a.inst.OPCD == 31 && (a.inst.SUBOP10 == 0 || a.inst.SUBOP10 == 32)))
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{
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// Got a compare instruction.
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if (CanSwapAdjacentOps(a, b)) {
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// Alright, let's bubble it down!
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CodeOp c = a;
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a = b;
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b = c;
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}
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}
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}
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}
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void PPCAnalyser::SetInstructionStats(CodeBlock *block, CodeOp *code, GekkoOPInfo *opinfo, u32 index)
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{
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code->wantsCR0 = false;
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code->wantsCR1 = false;
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code->wantsPS1 = false;
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if (opinfo->flags & FL_USE_FPU)
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block->m_fpa->any = true;
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if (opinfo->flags & FL_TIMER)
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block->m_gpa->anyTimer = true;
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// Does the instruction output CR0?
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if (opinfo->flags & FL_RC_BIT)
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code->outputCR0 = code->inst.hex & 1; //todo fix
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else if ((opinfo->flags & FL_SET_CRn) && code->inst.CRFD == 0)
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code->outputCR0 = true;
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else
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code->outputCR0 = (opinfo->flags & FL_SET_CR0) ? true : false;
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// Does the instruction output CR1?
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if (opinfo->flags & FL_RC_BIT_F)
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code->outputCR1 = code->inst.hex & 1; //todo fix
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else if ((opinfo->flags & FL_SET_CRn) && code->inst.CRFD == 1)
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code->outputCR1 = true;
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else
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code->outputCR1 = (opinfo->flags & FL_SET_CR1) ? true : false;
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int numOut = 0;
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int numIn = 0;
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if (opinfo->flags & FL_OUT_A)
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{
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code->regsOut[numOut++] = code->inst.RA;
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block->m_gpa->SetOutputRegister(code->inst.RA, index);
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}
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if (opinfo->flags & FL_OUT_D)
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{
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code->regsOut[numOut++] = code->inst.RD;
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block->m_gpa->SetOutputRegister(code->inst.RD, index);
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}
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if (opinfo->flags & FL_OUT_S)
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{
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code->regsOut[numOut++] = code->inst.RS;
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block->m_gpa->SetOutputRegister(code->inst.RS, index);
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}
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if ((opinfo->flags & FL_IN_A) || ((opinfo->flags & FL_IN_A0) && code->inst.RA != 0))
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{
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code->regsIn[numIn++] = code->inst.RA;
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block->m_gpa->SetInputRegister(code->inst.RA, index);
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}
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if (opinfo->flags & FL_IN_B)
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{
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code->regsIn[numIn++] = code->inst.RB;
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block->m_gpa->SetInputRegister(code->inst.RB, index);
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}
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if (opinfo->flags & FL_IN_C)
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{
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code->regsIn[numIn++] = code->inst.RC;
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block->m_gpa->SetInputRegister(code->inst.RC, index);
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}
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if (opinfo->flags & FL_IN_S)
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{
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code->regsIn[numIn++] = code->inst.RS;
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block->m_gpa->SetInputRegister(code->inst.RS, index);
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}
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// Set remaining register slots as unused (-1)
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for (int j = numIn; j < 3; j++)
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code->regsIn[j] = -1;
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for (int j = numOut; j < 2; j++)
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code->regsOut[j] = -1;
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for (int j = 0; j < 3; j++)
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code->fregsIn[j] = -1;
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code->fregOut = -1;
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switch (opinfo->type)
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{
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case OPTYPE_INTEGER:
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case OPTYPE_LOAD:
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case OPTYPE_STORE:
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case OPTYPE_LOADFP:
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case OPTYPE_STOREFP:
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break;
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case OPTYPE_FPU:
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break;
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case OPTYPE_BRANCH:
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if (code->inst.hex == 0x4e800020)
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{
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// For analysis purposes, we can assume that blr eats opinfo->flags.
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code->outputCR0 = true;
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code->outputCR1 = true;
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}
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break;
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case OPTYPE_SYSTEM:
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case OPTYPE_SYSTEMFP:
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break;
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}
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}
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u32 PPCAnalyser::Analyse(u32 address, CodeBlock *block, CodeBuffer *buffer, u32 blockSize)
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{
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// Clear block stats
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memset(block->m_stats, 0, sizeof(BlockStats));
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// Clear register stats
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block->m_gpa->any = true;
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block->m_fpa->any = false;
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block->m_gpa->Clear();
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block->m_fpa->Clear();
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// Set the blocks start address
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block->m_address = address;
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// Reset our block state
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block->m_broken = false;
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block->m_instructions = 0;
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CodeOp *code = buffer->codebuffer;
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bool found_exit = false;
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u32 returnAddress = 0;
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u32 numFollows = 0;
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u32 num_inst = 0;
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for (u32 i = 0; i < blockSize; ++i)
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{
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UGeckoInstruction inst = JitInterface::Read_Opcode_JIT(address);
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if (inst.hex != 0)
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{
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num_inst++;
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memset(&code[i], 0, sizeof(CodeOp));
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GekkoOPInfo *opinfo = GetOpInfo(inst);
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code[i].opinfo = opinfo;
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code[i].address = address;
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code[i].inst = inst;
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code[i].branchTo = -1;
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code[i].branchToIndex = -1;
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code[i].skip = false;
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block->m_stats->numCycles += opinfo->numCycles;
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SetInstructionStats(block, &code[i], opinfo, i);
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bool follow = false;
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u32 destination = 0;
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bool conditional_continue = false;
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// Do we inline leaf functions?
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if (HasOption(OPTION_LEAF_INLINE))
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{
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if (inst.OPCD == 18 && blockSize > 1)
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{
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//Is bx - should we inline? yes!
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if (inst.AA)
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destination = SignExt26(inst.LI << 2);
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else
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destination = address + SignExt26(inst.LI << 2);
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if (destination != block->m_address)
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follow = true;
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}
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else if (inst.OPCD == 19 && inst.SUBOP10 == 16 &&
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(inst.BO & (1 << 4)) && (inst.BO & (1 << 2)) &&
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returnAddress != 0)
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{
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// bclrx with unconditional branch = return
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follow = true;
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destination = returnAddress;
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returnAddress = 0;
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if (inst.LK)
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returnAddress = address + 4;
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}
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else if (inst.OPCD == 31 && inst.SUBOP10 == 467)
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{
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// mtspr
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const u32 index = (inst.SPRU << 5) | (inst.SPRL & 0x1F);
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if (index == SPR_LR) {
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// We give up to follow the return address
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// because we have to check the register usage.
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returnAddress = 0;
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}
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}
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// TODO: Find the optimal value for FUNCTION_FOLLOWING_THRESHOLD.
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// If it is small, the performance will be down.
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// If it is big, the size of generated code will be big and
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// cache clearning will happen many times.
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// TODO: Investivate the reason why
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// "0" is fastest in some games, MP2 for example.
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if (numFollows > FUNCTION_FOLLOWING_THRESHOLD)
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follow = false;
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}
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if (HasOption(OPTION_CONDITIONAL_CONTINUE))
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{
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if (inst.OPCD == 16 &&
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((inst.BO & BO_DONT_DECREMENT_FLAG) == 0 || (inst.BO & BO_DONT_CHECK_CONDITION) == 0))
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{
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// bcx with conditional branch
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conditional_continue = true;
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}
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else if (inst.OPCD == 19 && inst.SUBOP10 == 16 &&
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((inst.BO & BO_DONT_DECREMENT_FLAG) == 0 || (inst.BO & BO_DONT_CHECK_CONDITION) == 0))
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{
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// bclrx with conditional branch
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conditional_continue = true;
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}
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else if (inst.OPCD == 3 ||
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(inst.OPCD == 31 && inst.SUBOP10 == 4))
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{
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// tw/twi tests and raises an exception
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conditional_continue = true;
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}
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else if (inst.OPCD == 19 && inst.SUBOP10 == 528 &&
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(inst.BO_2 & BO_DONT_CHECK_CONDITION) == 0)
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{
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// Rare bcctrx with conditional branch
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// Seen in NES games
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conditional_continue = true;
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}
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}
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if (!follow)
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{
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if (!conditional_continue && opinfo->flags & FL_ENDBLOCK) //right now we stop early
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{
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found_exit = true;
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break;
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}
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address += 4;
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}
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// XXX: We don't support inlining yet.
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#if 0
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else
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{
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numFollows++;
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// We don't "code[i].skip = true" here
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// because bx may store a certain value to the link register.
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// Instead, we skip a part of bx in Jit**::bx().
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address = destination;
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merged_addresses[size_of_merged_addresses++] = address;
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}
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#endif
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}
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else
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{
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// ISI exception or other critical memory exception occured (game over)
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ERROR_LOG(DYNA_REC, "Instruction hex was 0!");
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break;
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}
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}
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if (block->m_instructions > 1)
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ReorderInstructions(block->m_instructions, code);
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if ((!found_exit && num_inst > 0) || blockSize == 1)
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{
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// We couldn't find an exit
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block->m_broken = true;
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}
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// Scan for CR0 dependency
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// assume next block wants CR0 to be safe
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bool wantsCR0 = true;
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bool wantsCR1 = true;
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bool wantsPS1 = true;
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for (int i = block->m_instructions - 1; i >= 0; i--)
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{
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if (code[i].outputCR0)
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wantsCR0 = false;
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if (code[i].outputCR1)
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wantsCR1 = false;
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if (code[i].outputPS1)
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wantsPS1 = false;
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wantsCR0 |= code[i].wantsCR0;
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wantsCR1 |= code[i].wantsCR1;
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wantsPS1 |= code[i].wantsPS1;
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code[i].wantsCR0 = wantsCR0;
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code[i].wantsCR1 = wantsCR1;
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code[i].wantsPS1 = wantsPS1;
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}
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block->m_instructions = num_inst;
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return address;
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}
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} // namespace
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} // namespace
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@ -64,19 +64,32 @@ struct BlockRegStats
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return std::max(lastRead[reg], lastWrite[reg]) -
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return std::max(lastRead[reg], lastWrite[reg]) -
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std::min(firstRead[reg], firstWrite[reg]);}
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std::min(firstRead[reg], firstWrite[reg]);}
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inline void SetInputRegister(int reg, short opindex) {
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inline void SetInputRegister(int reg, short opindex)
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{
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if (firstRead[reg] == -1)
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if (firstRead[reg] == -1)
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firstRead[reg] = (short)(opindex);
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firstRead[reg] = (short)(opindex);
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lastRead[reg] = (short)(opindex);
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lastRead[reg] = (short)(opindex);
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numReads[reg]++;
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numReads[reg]++;
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}
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}
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inline void SetOutputRegister(int reg, short opindex) {
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inline void SetOutputRegister(int reg, short opindex)
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{
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if (firstWrite[reg] == -1)
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if (firstWrite[reg] == -1)
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firstWrite[reg] = (short)(opindex);
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firstWrite[reg] = (short)(opindex);
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lastWrite[reg] = (short)(opindex);
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lastWrite[reg] = (short)(opindex);
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numWrites[reg]++;
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numWrites[reg]++;
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}
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}
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inline void Clear()
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{
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for (int i = 0; i < 32; ++i)
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{
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firstRead[i] = -1;
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firstWrite[i] = -1;
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numReads[i] = 0;
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numWrites[i] = 0;
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}
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}
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};
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};
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@ -94,6 +107,75 @@ public:
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};
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};
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struct CodeBlock
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{
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// Beginning PPC address.
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u32 m_address;
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// Number of instructions
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// Gives us the size of the block.
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u32 m_instructions;
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// Some basic statistics about the block.
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BlockStats *m_stats;
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// Register statistics about the block.
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BlockRegStats *m_gpa, *m_fpa;
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// Are we a broken block?
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bool m_broken;
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};
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class PPCAnalyser
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{
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private:
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void ReorderInstructions(u32 instructions, CodeOp *code);
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void SetInstructionStats(CodeBlock *block, CodeOp *code, GekkoOPInfo *opinfo, u32 index);
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// Options
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u32 m_options;
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public:
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enum AnalystOption
|
||||||
|
{
|
||||||
|
// Conditional branch continuing
|
||||||
|
// If the JIT core supports conditional branches within the blocks
|
||||||
|
// Block will end on unconditional branch or other ENDBLOCK flagged instruction.
|
||||||
|
// Requires JIT support to be enabled.
|
||||||
|
OPTION_CONDITIONAL_CONTINUE = (1 << 0),
|
||||||
|
|
||||||
|
// If there is a unconditional branch that jumps to a leaf function then inline it.
|
||||||
|
// Might require JIT intervention to support it correctly.
|
||||||
|
// Requires JITBLock support for inlined code
|
||||||
|
// XXX: NOT COMPLETE
|
||||||
|
OPTION_LEAF_INLINE = (1 << 1),
|
||||||
|
|
||||||
|
// Complex blocks support jumping backwards on to themselves.
|
||||||
|
// Happens commonly in loops, pretty complex to support.
|
||||||
|
// May require register caches to use register usage metrics.
|
||||||
|
// XXX: NOT COMPLETE
|
||||||
|
OPTION_COMPLEX_BLOCK = (1 << 2),
|
||||||
|
|
||||||
|
// Similar to complex blocks.
|
||||||
|
// Instead of jumping backwards, this jumps forwards within the block.
|
||||||
|
// Requires JIT support to work.
|
||||||
|
// XXX: NOT COMPLETE
|
||||||
|
OPTION_FORWARD_JUMP = (1 << 3),
|
||||||
|
};
|
||||||
|
|
||||||
|
|
||||||
|
PPCAnalyser() : m_options(0) {}
|
||||||
|
|
||||||
|
// Option setting/getting
|
||||||
|
void SetOption(AnalystOption option) { m_options |= option; }
|
||||||
|
void ClearOption(AnalystOption option) { m_options &= ~(option); }
|
||||||
|
bool HasOption(AnalystOption option) { return !!(m_options & option); }
|
||||||
|
|
||||||
|
u32 Analyse(u32 address, CodeBlock *block, CodeBuffer *buffer, u32 blockSize);
|
||||||
|
};
|
||||||
|
|
||||||
u32 Flatten(u32 address, int *realsize, BlockStats *st, BlockRegStats *gpa,
|
u32 Flatten(u32 address, int *realsize, BlockStats *st, BlockRegStats *gpa,
|
||||||
BlockRegStats *fpa, bool &broken_block, CodeBuffer *buffer,
|
BlockRegStats *fpa, bool &broken_block, CodeBuffer *buffer,
|
||||||
int blockSize, u32* merged_addresses,
|
int blockSize, u32* merged_addresses,
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue