JitArm64: Fix dcbz backpatch
The dcbz instruction needs to lock W30 so that the slowmem code will push and pop it when calling into C++. Also, the slowmem code expects that the address is present in W0, so replace the use of W0 as a scratch register in the fastmem code with the now locked W30.
This commit is contained in:
parent
d1beb9ef70
commit
d91d6fcdc5
|
@ -104,9 +104,10 @@ void JitArm64::EmitBackpatchRoutine(u32 flags, bool fastmem, bool do_farcode, AR
|
|||
else if (flags & BackPatchInfo::FLAG_ZERO_256)
|
||||
{
|
||||
// This literally only stores 32bytes of zeros to the target address
|
||||
ADD(addr, addr, MEM_REG);
|
||||
STP(IndexType::Signed, ARM64Reg::ZR, ARM64Reg::ZR, addr, 0);
|
||||
STP(IndexType::Signed, ARM64Reg::ZR, ARM64Reg::ZR, addr, 16);
|
||||
ARM64Reg temp = ARM64Reg::X30;
|
||||
ADD(temp, addr, MEM_REG);
|
||||
STP(IndexType::Signed, ARM64Reg::ZR, ARM64Reg::ZR, temp, 0);
|
||||
STP(IndexType::Signed, ARM64Reg::ZR, ARM64Reg::ZR, temp, 16);
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
|
@ -597,7 +597,7 @@ void JitArm64::dcbz(UGeckoInstruction inst)
|
|||
|
||||
int a = inst.RA, b = inst.RB;
|
||||
|
||||
gpr.Lock(ARM64Reg::W0);
|
||||
gpr.Lock(ARM64Reg::W0, ARM64Reg::W30);
|
||||
|
||||
ARM64Reg addr_reg = ARM64Reg::W0;
|
||||
|
||||
|
@ -651,7 +651,7 @@ void JitArm64::dcbz(UGeckoInstruction inst)
|
|||
EmitBackpatchRoutine(BackPatchInfo::FLAG_ZERO_256, true, true, ARM64Reg::W0,
|
||||
EncodeRegTo64(addr_reg), gprs_to_push, fprs_to_push);
|
||||
|
||||
gpr.Unlock(ARM64Reg::W0);
|
||||
gpr.Unlock(ARM64Reg::W0, ARM64Reg::W30);
|
||||
}
|
||||
|
||||
void JitArm64::eieio(UGeckoInstruction inst)
|
||||
|
|
Loading…
Reference in New Issue