JitArm64: Fix LSL/LSR/ROR/ASR wrappers.
The other method has a latency of 2 cycles. This also improves the throughput a lot.
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@ -1542,19 +1542,22 @@ void ARM64XEmitter::MVN(ARM64Reg Rd, ARM64Reg Rm)
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}
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}
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void ARM64XEmitter::LSL(ARM64Reg Rd, ARM64Reg Rm, int shift)
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void ARM64XEmitter::LSL(ARM64Reg Rd, ARM64Reg Rm, int shift)
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{
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{
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ORR(Rd, Is64Bit(Rd) ? ZR : WZR, Rm, ArithOption(Rm, ST_LSL, shift));
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int bits = Is64Bit(Rd) ? 64 : 32;
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UBFM(Rd, Rm, (bits - shift) & (bits - 1), bits - shift - 1);
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}
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}
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void ARM64XEmitter::LSR(ARM64Reg Rd, ARM64Reg Rm, int shift)
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void ARM64XEmitter::LSR(ARM64Reg Rd, ARM64Reg Rm, int shift)
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{
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{
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ORR(Rd, Is64Bit(Rd) ? ZR : WZR, Rm, ArithOption(Rm, ST_LSR, shift));
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int bits = Is64Bit(Rd) ? 64 : 32;
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UBFM(Rd, Rm, shift, bits - 1);
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}
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}
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void ARM64XEmitter::ASR(ARM64Reg Rd, ARM64Reg Rm, int shift)
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void ARM64XEmitter::ASR(ARM64Reg Rd, ARM64Reg Rm, int shift)
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{
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{
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ORR(Rd, Is64Bit(Rd) ? ZR : WZR, Rm, ArithOption(Rm, ST_ASR, shift));
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int bits = Is64Bit(Rd) ? 64 : 32;
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SBFM(Rd, Rm, shift, bits - 1);
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}
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}
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void ARM64XEmitter::ROR(ARM64Reg Rd, ARM64Reg Rm, int shift)
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void ARM64XEmitter::ROR(ARM64Reg Rd, ARM64Reg Rm, int shift)
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{
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{
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ORR(Rd, Is64Bit(Rd) ? ZR : WZR, Rm, ArithOption(Rm, ST_ROR, shift));
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EXTR(Rd, Rm, Rm, shift);
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}
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}
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// Logical (immediate)
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// Logical (immediate)
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@ -721,7 +721,7 @@ public:
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void MOV(ARM64Reg Rd, ARM64Reg Rm);
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void MOV(ARM64Reg Rd, ARM64Reg Rm);
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void MVN(ARM64Reg Rd, ARM64Reg Rm);
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void MVN(ARM64Reg Rd, ARM64Reg Rm);
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// TODO: These are "slow" as they use arith+shift, should be replaced with UBFM/EXTR variants.
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// Convenience wrappers around UBFM/EXTR.
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void LSR(ARM64Reg Rd, ARM64Reg Rm, int shift);
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void LSR(ARM64Reg Rd, ARM64Reg Rm, int shift);
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void LSL(ARM64Reg Rd, ARM64Reg Rm, int shift);
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void LSL(ARM64Reg Rd, ARM64Reg Rm, int shift);
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void ASR(ARM64Reg Rd, ARM64Reg Rm, int shift);
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void ASR(ARM64Reg Rd, ARM64Reg Rm, int shift);
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