Compile fixes for Windows-on-ARM64
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6fcb1c6c46
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@ -364,6 +364,8 @@ void ARM64XEmitter::FlushIcacheSection(u8* start, u8* end)
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#if defined(IOS)
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// Header file says this is equivalent to: sys_icache_invalidate(start, end - start);
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sys_cache_control(kCacheFunctionPrepareForExecution, start, end - start);
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#elif defined(WIN32)
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FlushInstructionCache(GetCurrentProcess(), start, end - start);
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#else
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// Don't rely on GCC's __clear_cache implementation, as it caches
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// icache/dcache cache line sizes, that can vary between cores on
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@ -2172,6 +2174,8 @@ void ARM64XEmitter::ABI_PopRegisters(BitSet32 registers, BitSet32 ignore_mask)
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ARM64Reg second;
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if (!(num_regs & 1))
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second = (ARM64Reg)(X0 + *it++);
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else
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second = {};
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// 8 byte per register, but 16 byte alignment, so we may have to padd one register.
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// Only update the SP on the last load to avoid the dependency between those loads.
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@ -4164,20 +4168,19 @@ void ARM64XEmitter::ANDSI2R(ARM64Reg Rd, ARM64Reg Rn, u64 imm, ARM64Reg scratch)
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void ARM64XEmitter::AddImmediate(ARM64Reg Rd, ARM64Reg Rn, u64 imm, bool shift, bool negative,
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bool flags)
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{
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switch ((negative << 1) | flags)
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if (!negative)
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{
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case 0:
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if (!flags)
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ADD(Rd, Rn, imm, shift);
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break;
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case 1:
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else
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ADDS(Rd, Rn, imm, shift);
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break;
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case 2:
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}
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else
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{
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if (!flags)
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SUB(Rd, Rn, imm, shift);
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break;
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case 3:
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else
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SUBS(Rd, Rn, imm, shift);
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break;
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}
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}
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@ -4185,7 +4188,7 @@ void ARM64XEmitter::ADDI2R_internal(ARM64Reg Rd, ARM64Reg Rn, u64 imm, bool nega
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ARM64Reg scratch)
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{
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bool has_scratch = scratch != INVALID_REG;
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u64 imm_neg = Is64Bit(Rd) ? -imm : -imm & 0xFFFFFFFFuLL;
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u64 imm_neg = Is64Bit(Rd) ? u64(-s64(imm)) : u64(-s64(imm)) & 0xFFFFFFFFuLL;
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bool neg_neg = negative ? false : true;
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// Fast paths, aarch64 immediate instructions
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@ -4232,20 +4235,19 @@ void ARM64XEmitter::ADDI2R_internal(ARM64Reg Rd, ARM64Reg Rn, u64 imm, bool nega
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(u32)imm);
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negative ^= MOVI2R2(scratch, imm, imm_neg);
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switch ((negative << 1) | flags)
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if (!negative)
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{
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case 0:
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if (!flags)
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ADD(Rd, Rn, scratch);
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break;
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case 1:
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else
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ADDS(Rd, Rn, scratch);
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break;
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case 2:
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}
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else
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{
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if (!flags)
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SUB(Rd, Rn, scratch);
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break;
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case 3:
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else
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SUBS(Rd, Rn, scratch);
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break;
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}
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}
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@ -2,13 +2,17 @@
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// Licensed under GPLv2+
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// Refer to the license.txt file included.
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#include <asm/hwcap.h>
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#include <cstring>
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#include <fstream>
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#include <sstream>
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#include <string>
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#include <thread>
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#ifndef _WIN32
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#include <asm/hwcap.h>
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#include <sys/auxv.h>
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#include <unistd.h>
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#endif
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#include <fmt/format.h>
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@ -16,6 +20,8 @@
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#include "Common/CommonTypes.h"
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#include "Common/FileUtil.h"
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#ifndef WIN32
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const char procfile[] = "/proc/cpuinfo";
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static std::string GetCPUString()
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@ -42,6 +48,8 @@ static std::string GetCPUString()
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return cpu_string;
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}
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#endif
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CPUInfo cpu_info;
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CPUInfo::CPUInfo()
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@ -60,6 +68,21 @@ void CPUInfo::Detect()
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Mode64bit = true;
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vendor = CPUVendor::ARM;
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#ifdef _WIN32
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num_cores = std::thread::hardware_concurrency();
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// Windows does not provide any mechanism for querying the system registers on ARMv8, unlike Linux
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// which traps the register reads and emulates them in the kernel. There are environment variables
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// containing some of the CPU-specific values, which we could use for a lookup table in the
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// future. For now, assume all features are present as all known devices which are Windows-on-ARM
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// compatible also support these extensions.
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bFP = true;
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bASIMD = true;
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bAES = true;
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bCRC32 = true;
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bSHA1 = true;
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bSHA2 = true;
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#else
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// Get the information about the CPU
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num_cores = sysconf(_SC_NPROCESSORS_CONF);
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strncpy(cpu_string, GetCPUString().c_str(), sizeof(cpu_string));
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@ -71,6 +94,7 @@ void CPUInfo::Detect()
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bCRC32 = hwcaps & HWCAP_CRC32;
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bSHA1 = hwcaps & HWCAP_SHA1;
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bSHA2 = hwcaps & HWCAP_SHA2;
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#endif
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}
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// Turn the CPU info into a string we can show
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@ -11,7 +11,7 @@
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#include "Common/CommonFuncs.h"
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#include "Common/Intrinsics.h"
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#ifdef _M_ARM_64
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#if defined(_M_ARM_64) && !defined(_MSC_VER)
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#include <arm_acle.h>
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#endif
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@ -33,6 +33,10 @@ typedef CONTEXT SContext;
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#define CTX_R14 R14
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#define CTX_R15 R15
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#define CTX_RIP Rip
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#elif _M_ARM64
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#define CTX_REG(x) X[x]
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#define CTX_SP Sp
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#define CTX_PC Pc
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#else
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#error No context definition for architecture
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#endif
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@ -754,9 +754,9 @@ void JitArm64::DoJit(u32 em_address, JitBlock* b, u32 nextPC)
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LDR(INDEX_UNSIGNED, WA, PPC_REG, PPCSTATE_OFF(msr));
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FixupBranch b1 = TBNZ(WA, 13); // Test FP enabled bit
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FixupBranch far = B();
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FixupBranch far_addr = B();
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SwitchToFarCode();
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SetJumpTarget(far);
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SetJumpTarget(far_addr);
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gpr.Flush(FLUSH_MAINTAIN_STATE);
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fpr.Flush(FLUSH_MAINTAIN_STATE);
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@ -143,9 +143,9 @@ void JitArm64::bcx(UGeckoInstruction inst)
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JumpIfCRFieldBit(inst.BI >> 2, 3 - (inst.BI & 3), !(inst.BO_2 & BO_BRANCH_IF_TRUE));
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}
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FixupBranch far = B();
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FixupBranch far_addr = B();
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SwitchToFarCode();
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SetJumpTarget(far);
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SetJumpTarget(far_addr);
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if (inst.LK)
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{
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@ -160,12 +160,12 @@ void JitArm64::bcx(UGeckoInstruction inst)
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if (js.op->branchIsIdleLoop)
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{
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// make idle loops go faster
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ARM64Reg WA = gpr.GetReg();
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ARM64Reg XA = EncodeRegTo64(WA);
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ARM64Reg WA2 = gpr.GetReg();
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ARM64Reg XA2 = EncodeRegTo64(WA2);
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MOVP2R(XA, &CoreTiming::Idle);
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BLR(XA);
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gpr.Unlock(WA);
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MOVP2R(XA2, &CoreTiming::Idle);
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BLR(XA2);
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gpr.Unlock(WA2);
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WriteExceptionExit(js.op->branchTo);
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}
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@ -260,9 +260,9 @@ void JitArm64::bclrx(UGeckoInstruction inst)
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if (conditional)
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{
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FixupBranch far = B();
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FixupBranch far_addr = B();
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SwitchToFarCode();
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SetJumpTarget(far);
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SetJumpTarget(far_addr);
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}
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LDR(INDEX_UNSIGNED, WA, PPC_REG, PPCSTATE_OFF(spr[SPR_LR]));
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@ -35,7 +35,7 @@ void JitArm64::fp_arith(UGeckoInstruction inst)
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bool inputs_are_singles = fpr.IsSingle(a, !packed) && (!use_b || fpr.IsSingle(b, !packed)) &&
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(!use_c || fpr.IsSingle(c, !packed));
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ARM64Reg VA, VB, VC, VD;
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ARM64Reg VA{}, VB{}, VC{}, VD{};
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if (packed)
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{
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@ -368,7 +368,11 @@ void JitArm64::cntlzwx(UGeckoInstruction inst)
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if (gpr.IsImm(s))
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{
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#ifdef _MSC_VER
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gpr.SetImmediate(a, _CountLeadingZeros(gpr.GetImm(s)));
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#else
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gpr.SetImmediate(a, __builtin_clz(gpr.GetImm(s)));
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#endif
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if (inst.Rc)
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ComputeRC0(gpr.GetImm(a));
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}
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@ -931,7 +935,7 @@ void JitArm64::subfex(UGeckoInstruction inst)
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// d = ~a + b + carry;
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if (gpr.IsImm(a))
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MOVI2R(WA, ~gpr.GetImm(a));
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MOVI2R(WA, u32(~gpr.GetImm(a)));
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else
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MVN(WA, gpr.R(a));
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ADCS(gpr.R(d), WA, gpr.R(b));
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@ -1187,7 +1191,7 @@ void JitArm64::divwx(UGeckoInstruction inst)
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if (inst.Rc)
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ComputeRC0(imm_d);
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}
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else if (gpr.IsImm(b) && gpr.GetImm(b) != 0 && gpr.GetImm(b) != -1u)
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else if (gpr.IsImm(b) && gpr.GetImm(b) != 0 && gpr.GetImm(b) != UINT32_C(0xFFFFFFFF))
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{
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ARM64Reg WA = gpr.GetReg();
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MOVI2R(WA, gpr.GetImm(b));
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@ -408,7 +408,7 @@ void JitArm64::stX(UGeckoInstruction inst)
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gpr.BindToRegister(a, false);
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ARM64Reg WA = gpr.GetReg();
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ARM64Reg RB;
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ARM64Reg RB = {};
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ARM64Reg RA = gpr.R(a);
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if (regOffset != -1)
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RB = gpr.R(regOffset);
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@ -549,9 +549,9 @@ void JitArm64::dcbx(UGeckoInstruction inst)
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LSR(value, value, addr); // move current bit to bit 0
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FixupBranch bit_not_set = TBZ(value, 0);
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FixupBranch far = B();
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FixupBranch far_addr = B();
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SwitchToFarCode();
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SetJumpTarget(far);
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SetJumpTarget(far_addr);
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BitSet32 gprs_to_push = gpr.GetCallerSavedUsed();
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BitSet32 fprs_to_push = fpr.GetCallerSavedUsed();
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@ -568,10 +568,10 @@ void JitArm64::dcbx(UGeckoInstruction inst)
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m_float_emit.ABI_PopRegisters(fprs_to_push, X30);
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ABI_PopRegisters(gprs_to_push);
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FixupBranch near = B();
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FixupBranch near_addr = B();
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SwitchToNearCode();
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SetJumpTarget(bit_not_set);
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SetJumpTarget(near);
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SetJumpTarget(near_addr);
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gpr.Unlock(addr, value, W30);
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}
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@ -149,6 +149,7 @@ Arm64GPRCache::GuestRegInfo Arm64GPRCache::GetGuestByIndex(size_t index)
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if (index >= GUEST_CR_OFFSET && index < GUEST_CR_OFFSET + GUEST_CR_COUNT)
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return GetGuestCR(index - GUEST_CR_OFFSET);
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ASSERT_MSG(DYNA_REC, false, "Invalid index for guest register");
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return GetGuestGPR(0);
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}
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void Arm64GPRCache::FlushRegister(size_t index, bool maintain_state)
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@ -161,7 +162,7 @@ void Arm64GPRCache::FlushRegister(size_t index, bool maintain_state)
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{
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ARM64Reg host_reg = reg.GetReg();
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if (reg.IsDirty())
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m_emit->STR(INDEX_UNSIGNED, host_reg, PPC_REG, guest_reg.ppc_offset);
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m_emit->STR(INDEX_UNSIGNED, host_reg, PPC_REG, u32(guest_reg.ppc_offset));
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if (!maintain_state)
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{
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@ -173,14 +174,14 @@ void Arm64GPRCache::FlushRegister(size_t index, bool maintain_state)
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{
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if (!reg.GetImm())
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{
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m_emit->STR(INDEX_UNSIGNED, bitsize == 64 ? ZR : WZR, PPC_REG, guest_reg.ppc_offset);
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m_emit->STR(INDEX_UNSIGNED, bitsize == 64 ? ZR : WZR, PPC_REG, u32(guest_reg.ppc_offset));
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}
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else
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{
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ARM64Reg host_reg = bitsize != 64 ? GetReg() : EncodeRegTo64(GetReg());
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m_emit->MOVI2R(host_reg, reg.GetImm());
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m_emit->STR(INDEX_UNSIGNED, host_reg, PPC_REG, guest_reg.ppc_offset);
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m_emit->STR(INDEX_UNSIGNED, host_reg, PPC_REG, u32(guest_reg.ppc_offset));
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UnlockRegister(DecodeReg(host_reg));
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}
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@ -207,7 +208,7 @@ void Arm64GPRCache::FlushRegisters(BitSet32 regs, bool maintain_state)
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size_t ppc_offset = GetGuestByIndex(i).ppc_offset;
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ARM64Reg RX1 = R(GetGuestByIndex(i));
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ARM64Reg RX2 = R(GetGuestByIndex(i + 1));
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m_emit->STP(INDEX_SIGNED, RX1, RX2, PPC_REG, ppc_offset);
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m_emit->STP(INDEX_SIGNED, RX1, RX2, PPC_REG, u32(ppc_offset));
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if (!maintain_state)
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{
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UnlockRegister(DecodeReg(RX1));
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@ -285,7 +286,7 @@ ARM64Reg Arm64GPRCache::R(const GuestRegInfo& guest_reg)
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ARM64Reg host_reg = bitsize != 64 ? GetReg() : EncodeRegTo64(GetReg());
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reg.Load(host_reg);
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reg.SetDirty(false);
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m_emit->LDR(INDEX_UNSIGNED, host_reg, PPC_REG, guest_reg.ppc_offset);
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m_emit->LDR(INDEX_UNSIGNED, host_reg, PPC_REG, u32(guest_reg.ppc_offset));
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return host_reg;
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}
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break;
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@ -318,7 +319,7 @@ void Arm64GPRCache::BindToRegister(const GuestRegInfo& guest_reg, bool do_load)
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ARM64Reg host_reg = bitsize != 64 ? GetReg() : EncodeRegTo64(GetReg());
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reg.Load(host_reg);
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if (do_load)
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m_emit->LDR(INDEX_UNSIGNED, host_reg, PPC_REG, guest_reg.ppc_offset);
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m_emit->LDR(INDEX_UNSIGNED, host_reg, PPC_REG, u32(guest_reg.ppc_offset));
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}
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}
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@ -450,7 +451,7 @@ ARM64Reg Arm64FPRCache::R(size_t preg, RegType type)
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// Load the high 64bits from the file and insert them in to the high 64bits of the host
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// register
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ARM64Reg tmp_reg = GetReg();
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m_float_emit->LDR(64, INDEX_UNSIGNED, tmp_reg, PPC_REG, PPCSTATE_OFF(ps[preg].ps1));
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m_float_emit->LDR(64, INDEX_UNSIGNED, tmp_reg, PPC_REG, u32(PPCSTATE_OFF(ps[preg].ps1)));
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m_float_emit->INS(64, host_reg, 1, tmp_reg, 0);
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UnlockRegister(tmp_reg);
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@ -503,7 +504,8 @@ ARM64Reg Arm64FPRCache::R(size_t preg, RegType type)
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reg.Load(host_reg, REG_LOWER_PAIR);
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}
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reg.SetDirty(false);
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m_float_emit->LDR(load_size, INDEX_UNSIGNED, host_reg, PPC_REG, PPCSTATE_OFF(ps[preg].ps0));
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m_float_emit->LDR(load_size, INDEX_UNSIGNED, host_reg, PPC_REG,
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u32(PPCSTATE_OFF(ps[preg].ps0)));
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return host_reg;
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}
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default:
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@ -551,7 +553,7 @@ ARM64Reg Arm64FPRCache::RW(size_t preg, RegType type)
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// We are doing a full 128bit store because it takes 2 cycles on a Cortex-A57 to do a 128bit
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// store.
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// It would take longer to do an insert to a temporary and a 64bit store than to just do this.
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m_float_emit->STR(128, INDEX_UNSIGNED, flush_reg, PPC_REG, PPCSTATE_OFF(ps[preg].ps0));
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m_float_emit->STR(128, INDEX_UNSIGNED, flush_reg, PPC_REG, u32(PPCSTATE_OFF(ps[preg].ps0)));
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break;
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case REG_DUP_SINGLE:
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flush_reg = GetReg();
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@ -559,7 +561,7 @@ ARM64Reg Arm64FPRCache::RW(size_t preg, RegType type)
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[[fallthrough]];
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case REG_DUP:
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// Store PSR1 (which is equal to PSR0) in memory.
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m_float_emit->STR(64, INDEX_UNSIGNED, flush_reg, PPC_REG, PPCSTATE_OFF(ps[preg].ps1));
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m_float_emit->STR(64, INDEX_UNSIGNED, flush_reg, PPC_REG, u32(PPCSTATE_OFF(ps[preg].ps1)));
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break;
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default:
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// All other types doesn't store anything in PSR1.
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@ -684,7 +686,10 @@ void Arm64FPRCache::FlushRegister(size_t preg, bool maintain_state)
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store_size = 64;
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if (dirty)
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m_float_emit->STR(store_size, INDEX_UNSIGNED, host_reg, PPC_REG, PPCSTATE_OFF(ps[preg].ps0));
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{
|
||||
m_float_emit->STR(store_size, INDEX_UNSIGNED, host_reg, PPC_REG,
|
||||
u32(PPCSTATE_OFF(ps[preg].ps0)));
|
||||
}
|
||||
|
||||
if (!maintain_state)
|
||||
{
|
||||
|
@ -700,8 +705,8 @@ void Arm64FPRCache::FlushRegister(size_t preg, bool maintain_state)
|
|||
// Too bad moving them would break savestate compatibility between x86_64 and AArch64
|
||||
// m_float_emit->STP(64, INDEX_SIGNED, host_reg, host_reg, PPC_REG,
|
||||
// PPCSTATE_OFF(ps[preg].ps0));
|
||||
m_float_emit->STR(64, INDEX_UNSIGNED, host_reg, PPC_REG, PPCSTATE_OFF(ps[preg].ps0));
|
||||
m_float_emit->STR(64, INDEX_UNSIGNED, host_reg, PPC_REG, PPCSTATE_OFF(ps[preg].ps1));
|
||||
m_float_emit->STR(64, INDEX_UNSIGNED, host_reg, PPC_REG, u32(PPCSTATE_OFF(ps[preg].ps0)));
|
||||
m_float_emit->STR(64, INDEX_UNSIGNED, host_reg, PPC_REG, u32(PPCSTATE_OFF(ps[preg].ps1)));
|
||||
}
|
||||
|
||||
if (!maintain_state)
|
||||
|
|
|
@ -32,6 +32,7 @@ FixupBranch JitArm64::JumpIfCRFieldBit(int field, int bit, bool jump_if_set)
|
|||
return jump_if_set ? TBNZ(XA, 62) : TBZ(XA, 62);
|
||||
default:
|
||||
ASSERT_MSG(DYNA_REC, false, "Invalid CR bit");
|
||||
return {};
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -196,9 +197,9 @@ void JitArm64::twx(UGeckoInstruction inst)
|
|||
SetJumpTarget(fixup);
|
||||
}
|
||||
|
||||
FixupBranch far = B();
|
||||
FixupBranch far_addr = B();
|
||||
SwitchToFarCode();
|
||||
SetJumpTarget(far);
|
||||
SetJumpTarget(far_addr);
|
||||
|
||||
gpr.Flush(FlushMode::FLUSH_MAINTAIN_STATE);
|
||||
fpr.Flush(FlushMode::FLUSH_MAINTAIN_STATE);
|
||||
|
|
|
@ -379,7 +379,7 @@ void VertexLoaderARM64::GenerateVertexLoader()
|
|||
bool has_tc_scale = false;
|
||||
for (int i = 0; i < 8; i++)
|
||||
{
|
||||
has_tc |= tc[i];
|
||||
has_tc |= tc[i] != 0;
|
||||
has_tc_scale |= !!m_VtxAttr.texCoord[i].Frac;
|
||||
}
|
||||
|
||||
|
|
|
@ -17,14 +17,21 @@
|
|||
#include "Core/ConfigManager.h"
|
||||
#include "Core/Core.h"
|
||||
|
||||
// OpenGL is not available on Windows-on-ARM64
|
||||
#if !defined(_WIN32) || !defined(_M_ARM64)
|
||||
#define HAS_OPENGL 1
|
||||
#endif
|
||||
|
||||
// TODO: ugly
|
||||
#ifdef _WIN32
|
||||
#include "VideoBackends/D3D/VideoBackend.h"
|
||||
#include "VideoBackends/D3D12/VideoBackend.h"
|
||||
#endif
|
||||
#include "VideoBackends/Null/VideoBackend.h"
|
||||
#ifdef HAS_OPENGL
|
||||
#include "VideoBackends/OGL/VideoBackend.h"
|
||||
#include "VideoBackends/Software/VideoBackend.h"
|
||||
#endif
|
||||
#include "VideoBackends/Vulkan/VideoBackend.h"
|
||||
|
||||
#include "VideoCommon/AsyncRequests.h"
|
||||
|
@ -182,13 +189,17 @@ u16 VideoBackendBase::Video_GetBoundingBox(int index)
|
|||
void VideoBackendBase::PopulateList()
|
||||
{
|
||||
// OGL > D3D11 > Vulkan > SW > Null
|
||||
#ifdef HAS_OPENGL
|
||||
g_available_video_backends.push_back(std::make_unique<OGL::VideoBackend>());
|
||||
#endif
|
||||
#ifdef _WIN32
|
||||
g_available_video_backends.push_back(std::make_unique<DX11::VideoBackend>());
|
||||
g_available_video_backends.push_back(std::make_unique<DX12::VideoBackend>());
|
||||
#endif
|
||||
g_available_video_backends.push_back(std::make_unique<Vulkan::VideoBackend>());
|
||||
#ifdef HAS_OPENGL
|
||||
g_available_video_backends.push_back(std::make_unique<SW::VideoSoftware>());
|
||||
#endif
|
||||
g_available_video_backends.push_back(std::make_unique<Null::VideoBackend>());
|
||||
|
||||
const auto iter =
|
||||
|
|
Loading…
Reference in New Issue