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DIMAR only ignores bits 0-4, not the upper bits 

Based on a hardware test on a Wii.  The alignment code was originally added in 743641965a.
This commit is contained in:
Pokechu22 2019-10-26 15:35:29 -07:00
parent c564d64104
commit d3aad1d6d5
1 changed files with 1 additions and 1 deletions
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2
Source/Core/Core/HW/DVD/DVDInterface.cpp
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@ -594,7 +594,7 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
// handle things like address alignment) and complex write on the DMA // handle things like address alignment) and complex write on the DMA
// control register that will trigger the DMA. // control register that will trigger the DMA.
mmio->Register(base | DI_DMA_ADDRESS_REGISTER, MMIO::DirectRead<u32>(&s_DIMAR), mmio->Register(base | DI_DMA_ADDRESS_REGISTER, MMIO::DirectRead<u32>(&s_DIMAR),
MMIO::DirectWrite<u32>(&s_DIMAR, ~0xFC00001F)); MMIO::DirectWrite<u32>(&s_DIMAR, ~0x1F));
mmio->Register(base | DI_DMA_LENGTH_REGISTER, MMIO::DirectRead<u32>(&s_DILENGTH), mmio->Register(base | DI_DMA_LENGTH_REGISTER, MMIO::DirectRead<u32>(&s_DILENGTH),
MMIO::DirectWrite<u32>(&s_DILENGTH, ~0x1F)); MMIO::DirectWrite<u32>(&s_DILENGTH, ~0x1F));
mmio->Register(base | DI_DMA_CONTROL_REGISTER, MMIO::DirectRead<u32>(&s_DICR.Hex), mmio->Register(base | DI_DMA_CONTROL_REGISTER, MMIO::DirectRead<u32>(&s_DICR.Hex),