VideoSoftware: Cleanup PE perf metrics; returning the proper value now.

This commit is contained in:
NeoBrainX 2013-03-01 00:52:15 +01:00
parent 7682ed22c6
commit d0dbcc6369
5 changed files with 57 additions and 27 deletions

View File

@ -91,7 +91,7 @@ void SWBPWritten(int address, int newvalue)
SWPixelEngine::pereg.boxTop = newvalue & 0x3ff;
break;
case BPMEM_CLEAR_PIXEL_PERF:
// TODO: Parameter?
// TODO: I didn't test if the value written to this register affects the amount of cleared registers
SWPixelEngine::pereg.perfZcompInputZcomplocLo = 0;
SWPixelEngine::pereg.perfZcompInputZcomplocHi = 0;
SWPixelEngine::pereg.perfZcompOutputZcomplocLo = 0;

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@ -150,18 +150,15 @@ inline void Draw(s32 x, s32 y, s32 xi, s32 yi)
if (bpmem.zcontrol.early_ztest && bpmem.zmode.testenable && g_SWVideoConfig.bZComploc)
{
// TODO: Verify that perf regs are being incremented even if test is disabled
if (++SWPixelEngine::pereg.perfZcompInputZcomplocLo == 0)
SWPixelEngine::pereg.perfZcompInputZcomplocHi++;
// TODO: Test if perf regs are incremented even if test is disabled
SWPixelEngine::pereg.IncZInputQuadCount(true);
if (bpmem.zmode.testenable)
{
// early z
if (!EfbInterface::ZCompare(x, y, z))
return;
}
if (++SWPixelEngine::pereg.perfZcompOutputZcomplocLo == 0)
SWPixelEngine::pereg.perfZcompOutputZcomplocHi++;
SWPixelEngine::pereg.IncZOutputQuadCount(true);
}
RasterBlockPixel& pixel = rasterBlock.Pixel[xi][yi];

View File

@ -81,17 +81,6 @@ void Read16(u16& _uReturnValue, const u32 _iAddress)
if (address <= 0x2e)
_uReturnValue = ((u16*)&pereg)[address >> 1];
if (address > 0x16)
{
ERROR_LOG(PIXELENGINE, "addr %#08x, ret %#04x; %#04x%04x, %#04x%04x, %#04x%04x, %#04x%04x, %#04x%04x, %#04x%04x\n", address, _uReturnValue,
pereg.perfZcompInputZcomplocHi, pereg.perfZcompInputZcomplocLo,
pereg.perfZcompOutputZcomplocHi, pereg.perfZcompOutputZcomplocLo,
pereg.perfZcompInputHi, pereg.perfZcompInputLo,
pereg.perfZcompOutputHi, pereg.perfZcompOutputLo,
pereg.perfBlendInputHi, pereg.perfBlendInputLo,
pereg.perfEfbCopyClocksHi, pereg.perfEfbCopyClocksLo);
}
}
void Write32(const u32 _iValue, const u32 _iAddress)

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@ -158,6 +158,54 @@ namespace SWPixelEngine
u16 perfBlendInputHi;
u16 perfEfbCopyClocksLo;
u16 perfEfbCopyClocksHi;
// NOTE: hardware doesn't process individual pixels but quads instead. Current software renderer architecture works on pixels though, so we have this "quad" hack here to only increment the registers on every fourth rendered pixel
void IncZInputQuadCount(bool early_ztest)
{
static int quad = 0;
if (++quad != 3)
return;
quad = 0;
if (early_ztest)
{
if (++perfZcompInputZcomplocLo == 0)
perfZcompInputZcomplocHi++;
}
else
{
if (++perfZcompInputLo == 0)
perfZcompInputHi++;
}
}
void IncZOutputQuadCount(bool early_ztest)
{
static int quad = 0;
if (++quad != 3)
return;
quad = 0;
if (early_ztest)
{
if (++perfZcompOutputZcomplocLo == 0)
perfZcompOutputZcomplocHi++;
}
else
{
if (++perfZcompOutputLo == 0)
perfZcompOutputHi++;
}
}
void IncBlendInputQuadCount()
{
static int quad = 0;
if (++quad != 3)
return;
quad = 0;
if (++perfBlendInputLo == 0)
perfBlendInputHi++;
}
};
extern PEReg pereg;

View File

@ -789,14 +789,12 @@ void Tev::Draw()
if (late_ztest && bpmem.zmode.testenable)
{
// TODO: Check against hw if these values get incremented even if depth testing is disabled
if (++SWPixelEngine::pereg.perfZcompInputLo == 0)
SWPixelEngine::pereg.perfZcompInputHi++;
SWPixelEngine::pereg.IncZInputQuadCount(false);
if (!EfbInterface::ZCompare(Position[0], Position[1], Position[2]))
return;
if (!EfbInterface::ZCompare(Position[0], Position[1], Position[2]))
return;
if (++SWPixelEngine::pereg.perfZcompOutputLo == 0)
SWPixelEngine::pereg.perfZcompOutputHi++;
SWPixelEngine::pereg.IncZOutputQuadCount(false);
}
#if ALLOW_TEV_DUMPS
@ -820,9 +818,7 @@ void Tev::Draw()
#endif
INCSTAT(swstats.thisFrame.tevPixelsOut);
if (++SWPixelEngine::pereg.perfBlendInputLo == 0)
SWPixelEngine::pereg.perfBlendInputHi++;
SWPixelEngine::pereg.IncBlendInputQuadCount();
EfbInterface::BlendTev(Position[0], Position[1], output);
}