Compile the ARAM DMA exception checks into the JIT block in a similar style to FIFO writes. This ensures that the ARAM DMA is handled soon after the DMA completes. Fixes issue 7122 and issue 7342.
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23e2301223
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@ -38,6 +38,7 @@
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#include "Core/HW/MMIO.h"
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#include "Core/HW/ProcessorInterface.h"
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#include "Core/PowerPC/PowerPC.h"
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#include "Core/PowerPC/JitCommon/JitBase.h"
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namespace DSP
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{
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@ -441,6 +442,21 @@ static void UpdateInterrupts()
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bool ints_set = (((g_dspState.DSPControl.Hex >> 1) & g_dspState.DSPControl.Hex & (INT_DSP | INT_ARAM | INT_AID)) != 0);
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ProcessorInterface::SetInterrupt(ProcessorInterface::INT_CAUSE_DSP, ints_set);
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if ((g_dspState.DSPControl.Hex >> 1) & g_dspState.DSPControl.Hex & (INT_DSP | INT_ARAM | INT_AID))
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{
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if (jit && PC != 0 && (jit->js.dspARAMAddresses.find(PC)) == (jit->js.dspARAMAddresses.end()) && (g_dspState.DSPControl.ARAM & g_dspState.DSPControl.ARAM_mask))
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{
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int type = GetOpInfo(Memory::ReadUnchecked_U32(PC))->type;
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if (type == OPTYPE_STORE || type == OPTYPE_STOREFP || (type == OPTYPE_PS && GetOpInfo(Memory::ReadUnchecked_U32(PC))->opname == "psq_st"))
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{
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jit->js.dspARAMAddresses.insert(PC);
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// Invalidate the JIT block so that it gets recompiled with the external exception check included.
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jit->GetBlockCache()->InvalidateICache(PC, 4);
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}
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}
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}
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}
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static void GenerateDSPInterrupt(u64 DSPIntType, int cyclesLate)
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@ -518,25 +534,11 @@ static void Do_ARAM_DMA()
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g_dspState.DSPControl.DMAState = 1;
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if (g_arDMA.Cnt.count == 32)
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{
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// Beyond Good and Evil (GGEE41) sends count 32
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// Lost Kingdoms 2 needs the exception check here in DSP HLE mode
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CompleteARAM(0, 0);
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CoreTiming::ForceExceptionCheck(100);
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}
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else
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{
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CoreTiming::ScheduleEvent_Threadsafe(0, et_CompleteARAM);
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// Force an early exception check on large transfers. Fixes RE2 audio.
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// NFS:HP2 (<= 6144)
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// Viewtiful Joe (<= 6144)
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// Sonic Mega Collection (> 2048)
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// Paper Mario battles (> 32)
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// Mario Super Baseball (> 32)
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// Knockout Kings 2003 loading (> 32)
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// WWE DOR (> 32)
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if (g_arDMA.Cnt.count > 2048 && g_arDMA.Cnt.count <= 6144)
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CoreTiming::ForceExceptionCheck(100);
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}
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// Real hardware DMAs in 32byte chunks, but we can get by with 8byte chunks
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@ -697,7 +697,8 @@ const u8* Jit64::DoJit(u32 em_address, PPCAnalyst::CodeBuffer *code_buf, JitBloc
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}
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// Add an external exception check if the instruction writes to the FIFO.
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if (jit->js.fifoWriteAddresses.find(ops[i].address) != jit->js.fifoWriteAddresses.end())
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if (jit->js.fifoWriteAddresses.find(ops[i].address) != jit->js.fifoWriteAddresses.end() ||
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jit->js.dspARAMAddresses.find(ops[i].address) != jit->js.dspARAMAddresses.end())
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{
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TEST(32, PPCSTATE(Exceptions), Imm32(EXCEPTION_ISI | EXCEPTION_PROGRAM | EXCEPTION_SYSCALL | EXCEPTION_FPU_UNAVAILABLE | EXCEPTION_DSI | EXCEPTION_ALIGNMENT));
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FixupBranch clearInt = J_CC(CC_NZ);
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@ -707,7 +708,14 @@ const u8* Jit64::DoJit(u32 em_address, PPCAnalyst::CodeBuffer *code_buf, JitBloc
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SetJumpTarget(extException);
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TEST(32, PPCSTATE(msr), Imm32(0x0008000));
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FixupBranch noExtIntEnable = J_CC(CC_Z, true);
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TEST(32, M((void *)&ProcessorInterface::m_InterruptCause), Imm32(ProcessorInterface::INT_CAUSE_CP | ProcessorInterface::INT_CAUSE_PE_TOKEN | ProcessorInterface::INT_CAUSE_PE_FINISH));
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if (jit->js.fifoWriteAddresses.find(ops[i].address) != jit->js.fifoWriteAddresses.end())
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{
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TEST(32, M((void *)&ProcessorInterface::m_InterruptCause), Imm32(ProcessorInterface::INT_CAUSE_CP | ProcessorInterface::INT_CAUSE_PE_TOKEN | ProcessorInterface::INT_CAUSE_PE_FINISH));
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}
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else
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{
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TEST(32, M((void *)&ProcessorInterface::m_InterruptCause), Imm32(ProcessorInterface::INT_CAUSE_DSP));
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}
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FixupBranch noCPInt = J_CC(CC_Z, true);
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gpr.Flush(FLUSH_MAINTAIN_STATE);
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@ -97,6 +97,7 @@ protected:
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JitBlock *curBlock;
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std::unordered_set<u32> fifoWriteAddresses;
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std::unordered_set<u32> dspARAMAddresses;
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};
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PPCAnalyst::CodeBlock code_block;
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