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JitIL: Make LoadCarry work correctly. 

git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@2202 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
magumagu9 2009-02-10 12:20:30 +00:00
parent 6daae62df3
commit cf5fc063ce
2 changed files with 10 additions and 3 deletions
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11
Source/Core/Core/Src/PowerPC/Jit64IL/IR.cpp
View File

@ -259,7 +259,7 @@ InstLoc IRBuilder::FoldZeroOp(unsigned Opcode, unsigned extra) {
} }
if (Opcode == LoadCarry) { if (Opcode == LoadCarry) {
if (!CarryCache) if (!CarryCache)
CarryCache = EmitZeroOp(LoadGReg, extra); CarryCache = EmitZeroOp(LoadCarry, extra);
return CarryCache; return CarryCache;
} }
if (Opcode == LoadCR) { if (Opcode == LoadCR) {
@ -1409,6 +1409,15 @@ static void DoWriteCode(IRBuilder* ibuild, Jit64* Jit, bool UseProfile) {
RI.regs[reg] = I; RI.regs[reg] = I;
break; break;
} }
case LoadCarry: {
if (!thisUsed) break;
X64Reg reg = regFindFreeReg(RI);
Jit->MOV(32, R(reg), M(&PowerPC::ppcState.spr[SPR_XER]));
Jit->SHR(32, R(reg), Imm8(29));
Jit->AND(32, R(reg), Imm8(1));
RI.regs[reg] = I;
break;
}
case StoreGReg: { case StoreGReg: {
unsigned ppcreg = *I >> 16; unsigned ppcreg = *I >> 16;
regStoreInstToConstLoc(RI, 32, getOp1(I), regStoreInstToConstLoc(RI, 32, getOp1(I),

2
Source/Core/Core/Src/PowerPC/Jit64IL/Jit_Integer.cpp
View File

@ -341,8 +341,6 @@
void Jit64::addzex(UGeckoInstruction inst) void Jit64::addzex(UGeckoInstruction inst)
{ {
Default(inst); return;
// FIXME: There's a bug in here somewhere!
INSTRUCTION_START INSTRUCTION_START
IREmitter::InstLoc lhs = ibuild.EmitLoadGReg(inst.RA), IREmitter::InstLoc lhs = ibuild.EmitLoadGReg(inst.RA),
val, newcarry; val, newcarry;