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Fix bloody printf specifiers. 

In particular, even in code that only runs on x86-64, you can't use
PRIx64 for size_t because, on OS X, one is unsigned long and the other
is unsigned long long and clang whines about the difference.  I guess
you could make a size_t specifier macro, but those are horribly ugly, so
I just used casting.

Anyone want to make a nice (and slow) template-based printf?

Now without bare 'unsigned'.
This commit is contained in:
comex 2014-08-23 15:27:33 -04:00
parent e0f35e0e59
commit cf01f47b52
5 changed files with 31 additions and 30 deletions
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38
Source/Core/Core/DSP/Jit/DSPJitRegCache.cpp
View File

@ -284,26 +284,26 @@ void DSPJitRegCache::flushRegs(DSPJitRegCache &cache, bool emit)
{
_assert_msg_(DSPLLE,
xregs[i].guest_reg == cache.xregs[i].guest_reg,
"cache and current xreg guest_reg mismatch for %" PRIx64, i);
"cache and current xreg guest_reg mismatch for %u", (unsigned int) i);
}
for (i = 0; i <= DSP_REG_MAX_MEM_BACKED; i++)
{
_assert_msg_(DSPLLE,
regs[i].loc.IsImm() == cache.regs[i].loc.IsImm(),
"cache and current reg loc mismatch for %zi", i);
"cache and current reg loc mismatch for %i", (unsigned int) i);
_assert_msg_(DSPLLE,
regs[i].loc.GetSimpleReg() == cache.regs[i].loc.GetSimpleReg(),
"cache and current reg loc mismatch for %zi", i);
"cache and current reg loc mismatch for %i", (unsigned int) i);
_assert_msg_(DSPLLE,
regs[i].dirty || !cache.regs[i].dirty,
"cache and current reg dirty mismatch for %zi", i);
"cache and current reg dirty mismatch for %i", (unsigned int) i);
_assert_msg_(DSPLLE,
regs[i].used == cache.regs[i].used,
"cache and current reg used mismatch for %zi", i);
"cache and current reg used mismatch for %i", (unsigned int) i);
_assert_msg_(DSPLLE,
regs[i].shift == cache.regs[i].shift,
"cache and current reg shift mismatch for %zi", i);
"cache and current reg shift mismatch for %i", (unsigned int) i);
}
use_ctr = cache.use_ctr;
@ -560,11 +560,11 @@ X64Reg DSPJitRegCache::makeABICallSafe(X64Reg reg)
void DSPJitRegCache::movToHostReg(size_t reg, X64Reg host_reg, bool load)
{
_assert_msg_(DSPLLE, reg <= DSP_REG_MAX_MEM_BACKED,
"bad register name %" PRIx64, reg);
"bad register name %u", (unsigned int) reg);
_assert_msg_(DSPLLE, regs[reg].parentReg == DSP_REG_NONE,
"register %" PRIx64 " is proxy for %d", reg, regs[reg].parentReg);
"register %u is proxy for %d", (unsigned int) reg, regs[reg].parentReg);
_assert_msg_(DSPLLE, !regs[reg].used,
"moving to host reg in use guest reg %" PRIx64, reg);
"moving to host reg in use guest reg %u", (unsigned int) reg);
X64Reg old_reg = regs[reg].loc.GetSimpleReg();
if (old_reg == host_reg)
{
@ -606,11 +606,11 @@ void DSPJitRegCache::movToHostReg(size_t reg, X64Reg host_reg, bool load)
void DSPJitRegCache::movToHostReg(size_t reg, bool load)
{
_assert_msg_(DSPLLE, reg <= DSP_REG_MAX_MEM_BACKED,
"bad register name %" PRIx64, reg);
"bad register name %u", (unsigned int) reg);
_assert_msg_(DSPLLE, regs[reg].parentReg == DSP_REG_NONE,
"register %" PRIx64 " is proxy for %d", reg, regs[reg].parentReg);
"register %u is proxy for %d", (unsigned int) reg, regs[reg].parentReg);
_assert_msg_(DSPLLE, !regs[reg].used,
"moving to host reg in use guest reg %" PRIx64, reg);
"moving to host reg in use guest reg %u", (unsigned int) reg);
if (regs[reg].loc.IsSimpleReg())
{
@ -638,13 +638,13 @@ void DSPJitRegCache::movToHostReg(size_t reg, bool load)
void DSPJitRegCache::rotateHostReg(size_t reg, int shift, bool emit)
{
_assert_msg_(DSPLLE, reg <= DSP_REG_MAX_MEM_BACKED,
"bad register name %" PRIx64, reg);
"bad register name %u", (unsigned int) reg);
_assert_msg_(DSPLLE, regs[reg].parentReg == DSP_REG_NONE,
"register %" PRIx64 " is proxy for %d", reg, regs[reg].parentReg);
"register %u is proxy for %d", (unsigned int) reg, regs[reg].parentReg);
_assert_msg_(DSPLLE, regs[reg].loc.IsSimpleReg(),
"register %" PRIx64 " is not a simple reg", reg);
"register %u is not a simple reg", (unsigned int) reg);
_assert_msg_(DSPLLE, !regs[reg].used,
"rotating in use guest reg %" PRIx64, reg);
"rotating in use guest reg %u", (unsigned int) reg);
if (shift > regs[reg].shift && emit)
{
@ -682,11 +682,11 @@ void DSPJitRegCache::rotateHostReg(size_t reg, int shift, bool emit)
void DSPJitRegCache::movToMemory(size_t reg)
{
_assert_msg_(DSPLLE, reg <= DSP_REG_MAX_MEM_BACKED,
"bad register name %" PRIx64, reg);
"bad register name %u", (unsigned int) reg);
_assert_msg_(DSPLLE, regs[reg].parentReg == DSP_REG_NONE,
"register %" PRIx64 " is proxy for %d", reg, regs[reg].parentReg);
"register %u is proxy for %d", (unsigned int) reg, regs[reg].parentReg);
_assert_msg_(DSPLLE, !regs[reg].used,
"moving to memory in use guest reg %" PRIx64, reg);
"moving to memory in use guest reg %u", (unsigned int) reg);
if (regs[reg].used)
{

2
Source/Core/Core/PowerPC/Interpreter/Interpreter.cpp
View File

@ -82,7 +82,7 @@ static void Trace(UGeckoInstruction& instCode)
}
std::string ppc_inst = GekkoDisassembler::Disassemble(instCode.hex, PC);
DEBUG_LOG(POWERPC, "INTER PC: %08x SRR0: %08x SRR1: %08x CRval: %016lx FPSCR: %08x MSR: %08x LR: %08x %s %08x %s", PC, SRR0, SRR1, PowerPC::ppcState.cr_val[0], PowerPC::ppcState.fpscr, PowerPC::ppcState.msr, PowerPC::ppcState.spr[8], regs.c_str(), instCode.hex, ppc_inst.c_str());
DEBUG_LOG(POWERPC, "INTER PC: %08x SRR0: %08x SRR1: %08x CRval: %016lx FPSCR: %08x MSR: %08x LR: %08x %s %08x %s", PC, SRR0, SRR1, (unsigned long) PowerPC::ppcState.cr_val[0], PowerPC::ppcState.fpscr, PowerPC::ppcState.msr, PowerPC::ppcState.spr[8], regs.c_str(), instCode.hex, ppc_inst.c_str());
}
int Interpreter::SingleStepInner(void)

12
Source/Core/Core/PowerPC/Jit64/JitRegCache.cpp
View File

@ -311,7 +311,7 @@ void FPURegCache::LoadRegister(size_t preg, X64Reg newLoc)
{
if (!regs[preg].location.IsImm() && (regs[preg].location.offset & 0xF))
{
PanicAlert("WARNING - misaligned fp register location %" PRIx64, preg);
PanicAlert("WARNING - misaligned fp register location %u", (unsigned int) preg);
}
emit->MOVAPD(newLoc, regs[preg].location);
}
@ -323,17 +323,17 @@ void FPURegCache::StoreRegister(size_t preg, OpArg newLoc)
void RegCache::Flush(FlushMode mode)
{
for (size_t i = 0; i < xregs.size(); i++)
for (unsigned int i = 0; i < xregs.size(); i++)
{
if (xregs[i].locked)
PanicAlert("Someone forgot to unlock X64 reg %" PRIx64, i);
PanicAlert("Someone forgot to unlock X64 reg %u", i);
}
for (size_t i = 0; i < regs.size(); i++)
for (unsigned int i = 0; i < regs.size(); i++)
{
if (regs[i].locked)
{
PanicAlert("Someone forgot to unlock PPC reg %" PRIx64 " (X64 reg %i).", i, RX(i));
PanicAlert("Someone forgot to unlock PPC reg %u (X64 reg %i).", i, RX(i));
}
if (regs[i].away)
@ -344,7 +344,7 @@ void RegCache::Flush(FlushMode mode)
}
else
{
_assert_msg_(DYNA_REC,0,"Jit64 - Flush unhandled case, reg %" PRIx64 " PC: %08x", i, PC);
_assert_msg_(DYNA_REC,0,"Jit64 - Flush unhandled case, reg %u PC: %08x", i, PC);
}
}
}

2
Source/Core/Core/PowerPC/Jit64/JitRegCache.h
View File

@ -97,7 +97,7 @@ public:
if (IsBound(preg))
return regs[preg].location.GetSimpleReg();
PanicAlert("Not so simple - %" PRIx64, preg);
PanicAlert("Not so simple - %u", (unsigned int) preg);
return Gen::INVALID_REG;
}
virtual Gen::OpArg GetDefaultLocation(size_t reg) const = 0;

7
Source/Core/Core/PowerPC/Jit64IL/JitIL.cpp
View File

@ -496,9 +496,10 @@ void JitIL::Trace()
#endif
DEBUG_LOG(DYNA_REC, "JITIL PC: %08x SRR0: %08x SRR1: %08x CRval: %016lx%016lx%016lx%016lx%016lx%016lx%016lx%016lx FPSCR: %08x MSR: %08x LR: %08x %s %s",
PC, SRR0, SRR1, PowerPC::ppcState.cr_val[0], PowerPC::ppcState.cr_val[1], PowerPC::ppcState.cr_val[2], PowerPC::ppcState.cr_val[3],
PowerPC::ppcState.cr_val[4], PowerPC::ppcState.cr_val[5], PowerPC::ppcState.cr_val[6], PowerPC::ppcState.cr_val[7], PowerPC::ppcState.fpscr,
PowerPC::ppcState.msr, PowerPC::ppcState.spr[8], regs.c_str(), fregs.c_str());
PC, SRR0, SRR1, (unsigned long) PowerPC::ppcState.cr_val[0], (unsigned long) PowerPC::ppcState.cr_val[1], (unsigned long) PowerPC::ppcState.cr_val[2],
(unsigned long) PowerPC::ppcState.cr_val[3], (unsigned long) PowerPC::ppcState.cr_val[4], (unsigned long) PowerPC::ppcState.cr_val[5],
(unsigned long) PowerPC::ppcState.cr_val[6], (unsigned long) PowerPC::ppcState.cr_val[7], PowerPC::ppcState.fpscr, PowerPC::ppcState.msr,
PowerPC::ppcState.spr[8], regs.c_str(), fregs.c_str());
}
void STACKALIGN JitIL::Jit(u32 em_address)