DSPSpy: Add a test for looped addressing when using address increments. Delete unused old code.
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@3123 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
hrydgard
parent
6048f8a679
commit
cd50850bca
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@ -213,6 +213,8 @@ irq:
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; DMA:s the current state of the registers back to the PowerPC. To do this,
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; it must write the contents of all regs to DRAM.
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; Unfortunately, this loop uses AR0 so it's best to use AR1 and friends for testing
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; when messing with indexing.
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send_back:
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; make state safe.
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set16
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@ -1,614 +0,0 @@
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; This is the trojan program we send to the DSP from DSPSpy to figure it out.
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REGS_BASE: equ 0x0f80
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MEM_HI: equ 0x0f7E
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MEM_LO: equ 0x0f7F
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;
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; CODE STARTS HERE.
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; Interrupt vectors 8 vectors, 2 opcodes each
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jmp irq0
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jmp irq1
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jmp irq2
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jmp irq3
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jmp irq4
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jmp irq5
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jmp irq6
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jmp irq7
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; Main code at 0x10
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sbset #0x02
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sbset #0x03
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sbclr #0x04
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sbset #0x05
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sbset #0x06
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set16
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lri $CR, #0x00ff
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; Why do we have a main label here?
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main:
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clr $ACC1
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clr $ACC0
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; get address of memory dump and copy it to DRAM
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call wait_for_dsp_mbox
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si @DMBH, #0x8888
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si @DMBL, #0xdead
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si @DIRQ, #0x0001
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call wait_for_cpu_mbox
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lrs $AC0.M, @CMBL
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andi $ac1.m, #0x7fff
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sr @MEM_HI, $AC1.M
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sr @MEM_LO, $AC0.M
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lri $ax0.l, #0
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lri $ax1.l, #0 ;(DSP_CR_IMEM | DSP_CR_TO_CPU)
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lri $ax0.h, #0x2000
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lr $ac0.l, @MEM_HI
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lr $ac0.m, @MEM_LO
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call do_dma
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; get address of registers and DMA them to ram
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call wait_for_dsp_mbox
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si @DMBH, #0x8888
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si @DMBL, #0xbeef
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si @DIRQ, #0x0001
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call wait_for_cpu_mbox
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lrs $AC0.M, @CMBL
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andi $ac1.m, #0x7fff
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sr @MEM_HI, $AC1.M
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sr @MEM_LO, $AC0.M
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lri $ax0.l, #REGS_BASE
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lri $ax1.l, #0 ;(DSP_CR_IMEM | DSP_CR_TO_CPU)
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lri $ax0.h, #0x80
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lr $ac0.l, @MEM_HI
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lr $ac0.m, @MEM_LO
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call do_dma
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; Read in all the registers from RAM
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lri $ar0, #REGS_BASE+1
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lrri $ar1, @$ar0
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lrri $ar2, @$ar0
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lrri $ar3, @$ar0
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lrri $ix0, @$ar0
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lrri $ix1, @$ar0
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lrri $ix2, @$ar0
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lrri $ix3, @$ar0
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lrri $r08, @$ar0
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lrri $r09, @$ar0
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lrri $r10, @$ar0
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lrri $r11, @$ar0
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lrri $st0, @$ar0
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lrri $st1, @$ar0
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lrri $st2, @$ar0
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lrri $st3, @$ar0
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lrri $ac0.h, @$ar0
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lrri $ac1.h, @$ar0
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lrri $cr, @$ar0
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lrri $sr, @$ar0
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lrri $prod.l, @$ar0
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lrri $prod.m1, @$ar0
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lrri $prod.h, @$ar0
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lrri $prod.m2, @$ar0
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lrri $ax0.l, @$ar0
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lrri $ax1.l, @$ar0
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lrri $ax0.h, @$ar0
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lrri $ax1.h, @$ar0
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lrri $ac0.l, @$ar0
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lrri $ac1.l, @$ar0
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lrri $ac0.m, @$ar0
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lrri $ac1.m, @$ar0
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lr $ar0, @REGS_BASE
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; Right here we are at a specific predetermined state.
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; Ideal environment to try instructions.
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; We can call send_back at any time to send data back to the PowerPC.
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; Calling set40 here seemed to crash the dsp tester in strange ways
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; until I added set16 in send_back. Seems clear that it affects something important.
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nop
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nop
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lris $AC0.M, #0xcc
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lris $AC1.M, #0xcc
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nop
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mrr $ar0, $sr
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call send_back
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set40
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nop
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lris $AC0.M, #0xcc
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lris $AC1.M, #0xcc
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nop
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nop
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mrr $ar0, $sr
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call send_back
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cw 0xa100
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call send_back
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cw 0xa900
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call send_back
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set40
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cw 0xa100
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call send_back
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set40
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cw 0xa900
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call send_back
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; We're done - currently we only test one opcode, in this case 0x8600.
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; It's possible to test many more in one go - just call send_back after each one.
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jmp ende
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; Below here is tons of random leftover test code from whoever last experimented with this.
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; call dump_memory
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; call send_back
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cw 0x00de
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cw 0x03f1
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call send_back
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cw 0x0200
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cw 0x0a60
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call send_back
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cw 0x1c7e
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call send_back
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cw 0x8100
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call send_back
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cw 0x8900
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call send_back
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cw 0x009f
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cw 0x00a0
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call send_back
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cw 0x00de
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cw 0x03f1
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call send_back
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cw 0x5d00
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call send_back
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cw 0x0e50
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call send_back
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cw 0x0750
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call send_back
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cw 0x0270
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call send_back
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cw 0x5d00
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call send_back
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cw 0x00da
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cw 0x03f2
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call send_back
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cw 0x8600
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call send_back
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JNS g_0c4d
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; cw 0x0290
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; cw 0x0c4d
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; call send_back JX0
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cw 0x00de
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cw 0x03f3
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call send_back
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cw 0x5c00
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call send_back
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JLE g_0c38
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; cw 0x0293
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; cw 0x0c38 JX3
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; call send_back
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JMP g_0c52
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; cw 0x029f
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; cw 0x0c52
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; call send_back
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g_0c38:
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cw 0x00db
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cw 0x03f7
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call send_back
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cw 0x009e
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cw 0x8000
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call send_back
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cw 0x4600
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call send_back
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JMP g_0c44
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; cw 0x029f
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; cw 0x0c44
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; call send_back
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g_0c3f:
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cw 0x00db
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cw 0x03f7
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call send_back
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cw 0x009e
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cw 0x8000
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call send_back
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cw 0x5600
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call send_back
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g_0c44:
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cw 0x00fe
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cw 0x03f5
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call send_back
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cw 0x1fda
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call send_back
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cw 0x7c00
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call send_back
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cw 0x1f5e
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call send_back
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cw 0x00fe
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cw 0x03f2
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call send_back
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JMP g_0c52
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; cw 0x029f
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; cw 0x0c52
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; call send_back
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g_0c4d:
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cw 0x00de
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cw 0x03f4
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call send_back
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cw 0x5d00
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call send_back
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JLE g_0c3f
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; cw 0x0293
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; cw 0x0c3f
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; call send_back
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g_0c52:
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cw 0x8900
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call send_back
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cw 0x00dd
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cw 0x03f5
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call send_back
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cw 0x1501
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call send_back
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cw 0x8100
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call send_back
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cw 0x00dc
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cw 0x03f6
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call send_back
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cw 0x008b
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cw 0x009f
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call send_back
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cw 0x0080
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cw 0x0a00
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call send_back
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cw 0x0900
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call send_back
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BLOOPI #0x50, g_0c65
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; cw 0x1150
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; cw 0x0c65
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; call send_back
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cw 0x1878
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call send_back
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cw 0x4c00
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call send_back
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cw 0x1cfe
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call send_back
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cw 0x001f
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call send_back
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cw 0x1fd9
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call send_back
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g_0c65:
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cw 0x1b18
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call send_back
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cw 0x009f
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cw 0x0a60
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call send_back
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cw 0x1fc3
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call send_back
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cw 0x5c00
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call send_back
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cw 0x00fe
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cw 0x03f1
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call send_back
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cw 0x00fc
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cw 0x03f6
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call send_back
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cw 0x008b
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cw 0xffff
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call send_back
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; This is where we jump when we're done testing, see above.
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ende:
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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; We just fall into a loop, playing dead until someone resets the DSP.
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dead_loop:
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jmp dead_loop
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; Utility function to do DMA.
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; ac0.l:ac0.m - external address.
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; ax0.l - address in DSP
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do_dma:
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sr @DSMAH, $ac0.l
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sr @DSMAL, $ac0.m
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sr @DSPA, $ax0.l
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sr @DSCR, $ax1.l
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sr @DSBL, $ax0.h ; This kicks off the DMA.
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; Waits for said DMA to complete by watching a bit in DSCR.
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wait_dma:
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LRS $AC1.M, @DSCR
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andcf $ac1.m, #0x0004
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JLZ wait_dma
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RET
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; This waits for a mail to arrive in the DSP in-mailbox.
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wait_for_dsp_mbox:
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lrs $AC1.M, @DMBH
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andcf $ac1.m, #0x8000
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jlz wait_for_dsp_mbox
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ret
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; This waits for the CPU to grab a mail that we just sent from the DSP.
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wait_for_cpu_mbox:
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lrs $AC1.M, @cmbh
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andcf $ac1.m, #0x8000
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jlnz wait_for_cpu_mbox
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ret
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; IRQ handlers. Not entirely sure what good they do currently.
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irq0:
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lri $ac0.m, #0x0000
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jmp irq
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irq1:
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lri $ac0.m, #0x0001
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jmp irq
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irq2:
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lri $ac0.m, #0x0002
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jmp irq
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irq3:
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lri $ac0.m, #0x0003
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jmp irq
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irq4:
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lri $ac0.m, #0x0004
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jmp irq
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irq5:
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; No idea what this code is doing.
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set16
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mrr $st1, $ac0.l
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mrr $st1, $ac0.m
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clr $acc0
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mrr $ac0.m, $st1
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mrr $ac0.l, $st1
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nop ; Or why there's a nop sled here.
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nop
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nop
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nop
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nop
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nop
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rti
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lri $ac0.m, #0x0005
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jmp irq
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irq6:
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lri $ac0.m, #0x0006
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jmp irq
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irq7:
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lri $ac0.m, #0x0007
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jmp irq
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irq:
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lrs $AC1.M, @DMBH
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andcf $ac1.m, #0x8000
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jlz irq
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si @DMBH, #0x8BAD
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sr @DMBL, $r11
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;sr @DMBL, $ac0.m
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si @DIRQ, #0x0001
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halt
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; DMA:s the current state of the registers back to the PowerPC. To do this,
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; it must write the contents of all regs to DRAM.
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send_back:
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; make state safe.
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set16
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; store registers to reg table
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sr @REGS_BASE, $ar0
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lri $ar0, #(REGS_BASE + 1)
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srri @$ar0, $ar1
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srri @$ar0, $ar2
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srri @$ar0, $ar3
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srri @$ar0, $ix0
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srri @$ar0, $ix1
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srri @$ar0, $ix2
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srri @$ar0, $ix3
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srri @$ar0, $r08
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srri @$ar0, $r09
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srri @$ar0, $r10
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srri @$ar0, $r11
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srri @$ar0, $st0
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srri @$ar0, $st1
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srri @$ar0, $st2
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srri @$ar0, $st3
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srri @$ar0, $ac0.h
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srri @$ar0, $ac1.h
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srri @$ar0, $cr
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srri @$ar0, $sr
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srri @$ar0, $prod.l
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srri @$ar0, $prod.m1
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srri @$ar0, $prod.h
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srri @$ar0, $prod.m2
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srri @$ar0, $ax0.l
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srri @$ar0, $ax1.l
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srri @$ar0, $ax0.h
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srri @$ar0, $ax1.h
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srri @$ar0, $ac0.l
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srri @$ar0, $ac1.l
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srri @$ar0, $ac0.m
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srri @$ar0, $ac1.m
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; Regs are stored. Prepare DMA.
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lri $ax0.l, #0x0000
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lri $ax1.l, #1 ;(DSP_CR_IMEM | DSP_CR_TO_CPU)
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lri $ax0.h, #0x200
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lr $ac0.l, @MEM_HI
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lr $ac0.m, @MEM_LO
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lri $ar1, #8+8
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; Now, why are we looping here?
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bloop $ar1, dma_copy
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call do_dma
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addi $ac0.m, #0x200
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mrr $ac1.m, $ax0.l
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addi $ac1.m, #0x100
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mrr $ax0.l, $ac1.m
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nop
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dma_copy:
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nop
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||||
|
||||
; Wait for the CPU to send us a mail.
|
||||
call wait_for_dsp_mbox
|
||||
si @DMBH, #0x8888
|
||||
si @DMBL, #0xfeeb
|
||||
si @DIRQ, #0x0001
|
||||
|
||||
; wait for the CPU to recieve our response before we execute the next op
|
||||
call wait_for_cpu_mbox
|
||||
lrs $AC0.M, @CMBL
|
||||
andi $ac1.m, #0x7fff
|
||||
|
||||
; Restore all regs again so we're ready to execute another op.
|
||||
lri $ar0, #REGS_BASE+1
|
||||
lrri $ar1, @$ar0
|
||||
lrri $ar2, @$ar0
|
||||
lrri $ar3, @$ar0
|
||||
lrri $ix0, @$ar0
|
||||
lrri $ix1, @$ar0
|
||||
lrri $ix2, @$ar0
|
||||
lrri $ix3, @$ar0
|
||||
lrri $r08, @$ar0
|
||||
lrri $r09, @$ar0
|
||||
lrri $r10, @$ar0
|
||||
lrri $r11, @$ar0
|
||||
lrri $st0, @$ar0
|
||||
lrri $st1, @$ar0
|
||||
lrri $st2, @$ar0
|
||||
lrri $st3, @$ar0
|
||||
lrri $ac0.h, @$ar0
|
||||
lrri $ac1.h, @$ar0
|
||||
lrri $cr, @$ar0
|
||||
lrri $sr, @$ar0
|
||||
lrri $prod.l, @$ar0
|
||||
lrri $prod.m1, @$ar0
|
||||
lrri $prod.h, @$ar0
|
||||
lrri $prod.m2, @$ar0
|
||||
lrri $ax0.l, @$ar0
|
||||
lrri $ax1.l, @$ar0
|
||||
lrri $ax0.h, @$ar0
|
||||
lrri $ax1.h, @$ar0
|
||||
lrri $ac0.l, @$ar0
|
||||
lrri $ac1.l, @$ar0
|
||||
lrri $ac0.m, @$ar0
|
||||
lrri $ac1.m, @$ar0
|
||||
lr $ar0, @REGS_BASE
|
||||
|
||||
ret ; from send_back
|
||||
|
||||
; If you are in set40 mode, use this instead of send_back if you want to stay
|
||||
; in set40 mode.
|
||||
send_back_40:
|
||||
set16
|
||||
call send_back
|
||||
set40
|
||||
ret
|
||||
|
||||
; This one's odd. Doesn't look like it should work since it uses ac0.m but
|
||||
; increments acm0... (acc0)
|
||||
dump_memory:
|
||||
lri $ar2, #0x0000
|
||||
lri $ac0.m, #0x1000
|
||||
|
||||
lri $ar1, #0x1000
|
||||
bloop $ar1, _fill_loop2
|
||||
|
||||
mrr $ar3, $ac0.m
|
||||
nx'ld : $AX0.H, $AX1.H, @$AR0
|
||||
|
||||
mrr $ac1.m, $ar0
|
||||
mrr $ar0, $ar2
|
||||
srri @$ar0, $ax1.h
|
||||
mrr $ar2, $ar0
|
||||
mrr $ar0, $ac1.m
|
||||
|
||||
addis $acc0, #0x1
|
||||
|
||||
_fill_loop2:
|
||||
nop
|
||||
ret ; from dump_memory
|
||||
|
|
@ -0,0 +1,319 @@
|
|||
; This test checks the effect of the index looping registers (R8-R11)
|
||||
incdir "tests"
|
||||
include "dsp_base.inc"
|
||||
|
||||
; First theories, fitting tests with nice masks in the loop registers
|
||||
; IR THEORY: if ((ar & lp) == lp) ar &= ~lp;
|
||||
; DR THEORY: if ((ar & lp) == 0) ar |= lp;
|
||||
; These were proven FALSE though by the following:
|
||||
|
||||
; Tests done using AR1 = 0x0010, IX1 = 0
|
||||
; LP1 = 0
|
||||
; 10, 11, 11, 11, 11......
|
||||
; LP1 = 1
|
||||
; 10, 11, 10, 11, 10......
|
||||
; LP1 = 2
|
||||
; 10, 11, 12, 13, 11, 12, 13, 11, 12, 13 ......
|
||||
; LP1 = 3
|
||||
; 10, 11, 12, 13, 10, 11, 12, 13, 10, 11, 12, 13.......
|
||||
; LP1 = 4
|
||||
; 10, 11, 12, 13, 14, 15, 16, 17, 13, 14, 15, 16, 17, 13, 14, 15 ......
|
||||
; LP1 = 5
|
||||
; 10, 11, 12, 13, 14, 15, 16, 17, 12, 13, 14, 15 ...
|
||||
; LP1 = 6
|
||||
; 10, 11, 12, 13, 14, 15, 16, 17, 11, 12, 13, 14...
|
||||
; LP1 = 7
|
||||
; 10, 11, 12, 13, 14, 15, 16, 17, 10, 11, ....
|
||||
; LP1 = 8
|
||||
; 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1a, 1b, 1c, 1d, 1e, 1f, 17, 18, 19, 1a, 1b.....
|
||||
|
||||
|
||||
; I really don't know how the above could possibly be efficiently implemented in hardware.
|
||||
; And thus it's tricky to implement in software too :p
|
||||
|
||||
; test using indexing register 1 - 0 is used in send_back
|
||||
lri $AR1, #16
|
||||
lri $IX1, #32
|
||||
lri $R09, #0
|
||||
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
|
||||
lri $AR1, #16
|
||||
lri $R09, #1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
|
||||
lri $AR1, #16
|
||||
lri $R09, #2
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
|
||||
lri $AR1, #16
|
||||
lri $R09, #3
|
||||
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
|
||||
lri $AR1, #16
|
||||
lri $R09, #4
|
||||
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
|
||||
lri $AR1, #16
|
||||
lri $R09, #5
|
||||
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
|
||||
lri $AR1, #16
|
||||
lri $R09, #6
|
||||
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
|
||||
lri $AR1, #16
|
||||
lri $R09, #7
|
||||
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
|
||||
lri $AR1, #16
|
||||
lri $R09, #8
|
||||
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
|
||||
|
||||
lri $R09, #0xFFFF
|
||||
|
||||
; We're done, DO NOT DELETE THIS LINE
|
||||
jmp end_of_test
|
||||
Loading…
Reference in New Issue