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implement clrl (clral0/1) in the table 

git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@2910 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
nakeee 2009-04-06 21:55:50 +00:00
parent 24991b60a3
commit cd439cdce0
3 changed files with 22 additions and 2 deletions
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19
Source/Plugins/Plugin_DSP_LLE-testing/Src/DSPInterpreter.cpp
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@ -432,6 +432,9 @@ void tstaxh(const UDSPInstruction& opc)
Update_SR_Register16(val);
}
// CLR $acR
// 1000 r001 xxxx xxxx
// Clears accumulator $acR
void clr(const UDSPInstruction& opc)
{
u8 reg = (opc.hex >> 11) & 0x1;
@ -441,8 +444,24 @@ void clr(const UDSPInstruction& opc)
Update_SR_Register64((s64)0); // really?
}
// CLRL $acR.l
// 1111 110r xxxx xxxx
// Clears $acR.l - low 16 bits of accumulator $acR.
void clrl(const UDSPInstruction& opc)
{
u16 reg = DSP_REG_ACL0 + ((opc.hex >> 11) & 0x1);
g_dsp.r[reg] &= 0xFF00;
// Should this be 64bit?
Update_SR_Register64((s64)reg);
}
// CLRP
// 1000 0100 xxxx xxxx
// Clears product register $prod.
void clrp(const UDSPInstruction& opc)
{
// Magic numbers taken from doddie's doc
g_dsp.r[0x14] = 0x0000;
g_dsp.r[0x15] = 0xfff0;
g_dsp.r[0x16] = 0x00ff;

1
Source/Plugins/Plugin_DSP_LLE-testing/Src/DSPInterpreter.h
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@ -53,6 +53,7 @@ void sr(const UDSPInstruction& opc);
void si(const UDSPInstruction& opc);
void tstaxh(const UDSPInstruction& opc);
void clr(const UDSPInstruction& opc);
void clrl(const UDSPInstruction& opc);
void clrp(const UDSPInstruction& opc);
void mulc(const UDSPInstruction& opc);
void cmpar(const UDSPInstruction& opc);

4
Source/Plugins/Plugin_DSP_LLE-testing/Src/DSPTables.cpp
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@ -239,8 +239,8 @@ DSPOPCTemplate opcodes[] =
// This op does NOT exist, at least not under this name, in duddie's docs!
{"CMPAR" , 0xc100, 0xe7ff, DSPInterpreter::cmpar, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
{"CLRAL0", 0xfc00, 0xffff, nop, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi}, // clear acl0
{"CLRAL1", 0xfd00, 0xffff, nop, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi}, // clear acl1
{"CLRAL0", 0xfc00, 0xffff, DSPInterpreter::clrl, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi}, // clear acl0
{"CLRAL1", 0xfd00, 0xffff, DSPInterpreter::clrl, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi}, // clear acl1
{"CLRA0", 0x8100, 0xffff, DSPInterpreter::clr, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi}, // clear acc0
{"CLRA1", 0x8900, 0xffff, DSPInterpreter::clr, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi}, // clear acc1
{"CLRP", 0x8400, 0xffff, DSPInterpreter::clrp, nop, 1 | P_EXT, 0, {}, },