Implement a few more store instructions on ARM
This commit is contained in:
Ryan Houdek
parent
62adcaf552
commit
ccf1cee203
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@ -171,6 +171,9 @@ public:
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void lhz(UGeckoInstruction _inst);
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void lwz(UGeckoInstruction _inst);
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void lwzx(UGeckoInstruction _inst);
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void stbu(UGeckoInstruction _inst);
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void sth(UGeckoInstruction _inst);
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void sthu(UGeckoInstruction _inst);
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void stw(UGeckoInstruction _inst);
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void stwu(UGeckoInstruction _inst);
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@ -50,38 +50,48 @@ static void BackPatchError(const std::string &text, u8 *codePtr, u32 emAddress)
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bool DisamLoadStore(const u32 inst, ARMReg &rD, u8 &accessSize, bool &Store)
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{
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u8 op = (inst >> 20) & 0xFF;
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rD = (ARMReg)((inst >> 12) & 0xF);
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switch (op)
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{
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case 0x58: // STR
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{
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rD = (ARMReg)((inst >> 12) & 0xF);
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Store = true;
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accessSize = 32;
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}
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break;
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case 0x59: // LDR
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{
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rD = (ARMReg)((inst >> 12) & 0xF);
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Store = false;
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accessSize = 32;
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}
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break;
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case 0x05: // LDRH
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case 0x1D: // LDRH
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{
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rD = (ARMReg)((inst >> 12) & 0xF);
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Store = false;
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accessSize = 16;
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}
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break;
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case 0x45 + 0x18: // LDRB
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{
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rD = (ARMReg)((inst >> 12) & 0xF);
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Store = false;
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accessSize = 8;
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}
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break;
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case 0x44 + 0x18: // STRB
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case 0x5C: // STRB
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{
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Store = true;
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accessSize = 8;
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}
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break;
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case 0x1C: // STRH
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{
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Store = true;
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accessSize = 16;
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}
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break;
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default:
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printf("Op is 0x%02x\n", op);
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return false;
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}
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return true;
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@ -110,11 +120,11 @@ const u8 *JitArm::BackPatch(u8 *codePtr, int accessType, u32 emAddress, void *ct
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switch (accessSize)
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{
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case 8: // 8bit
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//emitter.MOVI2R(R14, (u32)&Memory::Write_U8, false); // 1-2
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emitter.MOVI2R(R14, (u32)&Memory::Write_U8, false); // 1-2
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return 0;
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break;
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case 16: // 16bit
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//emitter.MOVI2R(R14, (u32)&Memory::Write_U16, false); // 1-2
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emitter.MOVI2R(R14, (u32)&Memory::Write_U16, false); // 1-2
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return 0;
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break;
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case 32: // 32bit
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@ -36,6 +36,118 @@
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#else
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#define FASTMEM 1
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#endif
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void JitArm::stbu(UGeckoInstruction inst)
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{
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INSTRUCTION_START
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JITDISABLE(LoadStore)
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ARMReg RA = gpr.R(inst.RA);
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ARMReg RS = gpr.R(inst.RS);
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ARMReg ValueReg = gpr.GetReg();
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ARMReg Addr = gpr.GetReg();
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ARMReg Function = gpr.GetReg();
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MOVI2R(Addr, inst.SIMM_16);
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ADD(Addr, Addr, RA);
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// Check for DSI exception prior to writing back address
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LDR(Function, R9, PPCSTATE_OFF(Exceptions));
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CMP(Function, EXCEPTION_DSI);
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FixupBranch DoNotWrite = B_CC(CC_EQ);
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MOV(RA, Addr);
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SetJumpTarget(DoNotWrite);
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MOV(ValueReg, RS);
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MOVI2R(Function, (u32)&Memory::Write_U8);
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PUSH(4, R0, R1, R2, R3);
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MOV(R0, ValueReg);
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MOV(R1, Addr);
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BL(Function);
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POP(4, R0, R1, R2, R3);
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gpr.Unlock(ValueReg, Addr, Function);
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}
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void JitArm::sth(UGeckoInstruction inst)
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{
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INSTRUCTION_START
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JITDISABLE(LoadStore)
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ARMReg RS = gpr.R(inst.RS);
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#if 0 // FASTMEM
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// R10 contains the dest address
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ARMReg Value = R11;
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ARMReg RA;
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if (inst.RA)
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RA = gpr.R(inst.RA);
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MOV(Value, RS);
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if (inst.RA)
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{
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MOVI2R(R10, inst.SIMM_16, false);
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ADD(R10, R10, RA);
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}
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else
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{
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MOVI2R(R10, (u32)inst.SIMM_16, false);
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NOP(1);
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}
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StoreFromReg(R10, Value, 16, 0);
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#else
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ARMReg ValueReg = gpr.GetReg();
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ARMReg Addr = gpr.GetReg();
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ARMReg Function = gpr.GetReg();
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MOV(ValueReg, RS);
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if (inst.RA)
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{
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MOVI2R(Addr, inst.SIMM_16);
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ARMReg RA = gpr.R(inst.RA);
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ADD(Addr, Addr, RA);
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}
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else
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MOVI2R(Addr, (u32)inst.SIMM_16);
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MOVI2R(Function, (u32)&Memory::Write_U16);
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PUSH(4, R0, R1, R2, R3);
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MOV(R0, ValueReg);
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MOV(R1, Addr);
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BL(Function);
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POP(4, R0, R1, R2, R3);
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gpr.Unlock(ValueReg, Addr, Function);
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#endif
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}
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void JitArm::sthu(UGeckoInstruction inst)
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{
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INSTRUCTION_START
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JITDISABLE(LoadStore)
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ARMReg RA = gpr.R(inst.RA);
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ARMReg RS = gpr.R(inst.RS);
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ARMReg ValueReg = gpr.GetReg();
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ARMReg Addr = gpr.GetReg();
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ARMReg Function = gpr.GetReg();
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MOVI2R(Addr, inst.SIMM_16);
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ADD(Addr, Addr, RA);
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// Check for DSI exception prior to writing back address
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LDR(Function, R9, PPCSTATE_OFF(Exceptions));
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CMP(Function, EXCEPTION_DSI);
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FixupBranch DoNotWrite = B_CC(CC_EQ);
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MOV(RA, Addr);
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SetJumpTarget(DoNotWrite);
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MOV(ValueReg, RS);
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MOVI2R(Function, (u32)&Memory::Write_U16);
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PUSH(4, R0, R1, R2, R3);
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MOV(R0, ValueReg);
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MOV(R1, Addr);
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BL(Function);
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POP(4, R0, R1, R2, R3);
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gpr.Unlock(ValueReg, Addr, Function);
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}
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void JitArm::stw(UGeckoInstruction inst)
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{
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INSTRUCTION_START
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@ -98,8 +210,7 @@ void JitArm::stwu(UGeckoInstruction inst)
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MOVI2R(Addr, inst.SIMM_16);
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ADD(Addr, Addr, RA);
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// Check and set the update before writing since calling a function can
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// mess with the "special registers R11+ which may cause some issues.
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// Check for DSI exception prior to writing back address
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LDR(Function, R9, PPCSTATE_OFF(Exceptions));
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CMP(Function, EXCEPTION_DSI);
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FixupBranch DoNotWrite = B_CC(CC_EQ);
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@ -144,10 +255,10 @@ void JitArm::StoreFromReg(ARMReg dest, ARMReg value, int accessSize, s32 offset)
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STR(value, dest); // 8
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break;
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case 16:
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// Not implemented
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STRH(value, dest);
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break;
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case 8:
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// Not implemented
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STRB(value, dest);
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break;
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}
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gpr.Unlock(rA);
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@ -256,14 +367,11 @@ void JitArm::lhz(UGeckoInstruction inst)
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if (inst.RA)
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{
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ARMReg RA = gpr.R(inst.RA);
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printf("lhz jump to here: 0x%08x\n", (u32)GetCodePtr());
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MOV(R10, RA); // - 4
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}
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else
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{
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printf("lhz jump to here: 0x%08x\n", (u32)GetCodePtr());
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MOV(R10, 0); // - 4
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}
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LoadToReg(RD, R10, 16, (u32)inst.SIMM_16);
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#else
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@ -87,12 +87,12 @@ static GekkoOPTemplate primarytable[] =
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{42, &JitArm::Default}, //"lha", OPTYPE_LOAD, FL_OUT_D | FL_IN_A}},
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{43, &JitArm::Default}, //"lhau", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A}},
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{44, &JitArm::Default}, //"sth", OPTYPE_STORE, FL_IN_A | FL_IN_S}},
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{45, &JitArm::Default}, //"sthu", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_S}},
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{44, &JitArm::sth}, //"sth", OPTYPE_STORE, FL_IN_A | FL_IN_S}},
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{45, &JitArm::sthu}, //"sthu", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_S}},
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{36, &JitArm::stw}, //"stw", OPTYPE_STORE, FL_IN_A | FL_IN_S}},
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{37, &JitArm::stwu}, //"stwu", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_S}},
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{38, &JitArm::Default}, //"stb", OPTYPE_STORE, FL_IN_A | FL_IN_S}},
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{39, &JitArm::Default}, //"stbu", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_S}},
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{39, &JitArm::stbu}, //"stbu", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_S}},
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{46, &JitArm::Default}, //"lmw", OPTYPE_SYSTEM, FL_EVIL, 10}},
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{47, &JitArm::Default}, //"stmw", OPTYPE_SYSTEM, FL_EVIL, 10}},
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