Commit r5970 part #2: Jit64::GenerateCarry() don't need a temporary register anymore
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@5973 8ced0084-cf51-0410-be5f-012b33b47a6e
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@ -136,7 +136,7 @@ public:
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void WriteCallInterpreter(UGeckoInstruction _inst);
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void WriteCallInterpreter(UGeckoInstruction _inst);
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void Cleanup();
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void Cleanup();
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void GenerateCarry(Gen::X64Reg temp_reg);
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void GenerateCarry();
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void tri_op(int d, int a, int b, bool reversible, void (XEmitter::*op)(Gen::X64Reg, Gen::OpArg));
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void tri_op(int d, int a, int b, bool reversible, void (XEmitter::*op)(Gen::X64Reg, Gen::OpArg));
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typedef u32 (*Operation)(u32 a, u32 b);
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typedef u32 (*Operation)(u32 a, u32 b);
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@ -25,12 +25,14 @@
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#include "JitAsm.h"
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#include "JitAsm.h"
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// Assumes that the flags were just set through an addition.
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// Assumes that the flags were just set through an addition.
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void Jit64::GenerateCarry(Gen::X64Reg temp_reg) {
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void Jit64::GenerateCarry() {
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// USES_XER
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// USES_XER
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SETcc(CC_C, R(temp_reg));
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FixupBranch pNoCarry = J_CC(CC_NC);
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OR(32, M(&PowerPC::ppcState.spr[SPR_XER]), Imm32(1 << 29));
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FixupBranch pContinue = J();
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SetJumpTarget(pNoCarry);
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AND(32, M(&PowerPC::ppcState.spr[SPR_XER]), Imm32(~(1 << 29)));
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AND(32, M(&PowerPC::ppcState.spr[SPR_XER]), Imm32(~(1 << 29)));
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SHL(32, R(temp_reg), Imm8(29));
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SetJumpTarget(pContinue);
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OR(32, M(&PowerPC::ppcState.spr[SPR_XER]), R(temp_reg));
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}
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}
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u32 Add(u32 a, u32 b) {return a + b;}
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u32 Add(u32 a, u32 b) {return a + b;}
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@ -55,7 +57,7 @@ void Jit64::regimmop(int d, int a, bool binary, u32 value, Operation doop, void
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gpr.LoadToX64(d, false);
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gpr.LoadToX64(d, false);
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(this->*op)(32, gpr.R(d), Imm32(value)); //m_GPR[d] = m_GPR[_inst.RA] + _inst.SIMM_16;
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(this->*op)(32, gpr.R(d), Imm32(value)); //m_GPR[d] = m_GPR[_inst.RA] + _inst.SIMM_16;
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if (carry)
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if (carry)
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GenerateCarry(EAX);
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GenerateCarry();
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}
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}
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}
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}
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else
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else
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@ -64,7 +66,7 @@ void Jit64::regimmop(int d, int a, bool binary, u32 value, Operation doop, void
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MOV(32, gpr.R(d), gpr.R(a));
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MOV(32, gpr.R(d), gpr.R(a));
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(this->*op)(32, gpr.R(d), Imm32(value)); //m_GPR[d] = m_GPR[_inst.RA] + _inst.SIMM_16;
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(this->*op)(32, gpr.R(d), Imm32(value)); //m_GPR[d] = m_GPR[_inst.RA] + _inst.SIMM_16;
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if (carry)
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if (carry)
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GenerateCarry(EAX);
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GenerateCarry();
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}
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}
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}
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}
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else if (doop == Add)
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else if (doop == Add)
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@ -378,7 +380,6 @@ void Jit64::subfic(UGeckoInstruction inst)
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INSTRUCTION_START
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INSTRUCTION_START
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JITDISABLE(Integer)
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JITDISABLE(Integer)
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int a = inst.RA, d = inst.RD;
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int a = inst.RA, d = inst.RD;
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gpr.FlushLockX(ECX);
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gpr.Lock(a, d);
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gpr.Lock(a, d);
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gpr.LoadToX64(d, a == d, true);
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gpr.LoadToX64(d, a == d, true);
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int imm = inst.SIMM_16;
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int imm = inst.SIMM_16;
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@ -386,9 +387,8 @@ void Jit64::subfic(UGeckoInstruction inst)
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NOT(32, R(EAX));
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NOT(32, R(EAX));
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ADD(32, R(EAX), Imm32(imm + 1));
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ADD(32, R(EAX), Imm32(imm + 1));
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MOV(32, gpr.R(d), R(EAX));
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MOV(32, gpr.R(d), R(EAX));
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GenerateCarry(ECX);
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GenerateCarry();
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gpr.UnlockAll();
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gpr.UnlockAll();
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gpr.UnlockAllX();
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// This instruction has no RC flag
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// This instruction has no RC flag
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}
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}
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@ -671,7 +671,6 @@ void Jit64::addex(UGeckoInstruction inst)
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INSTRUCTION_START
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INSTRUCTION_START
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JITDISABLE(Integer)
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JITDISABLE(Integer)
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int a = inst.RA, b = inst.RB, d = inst.RD;
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int a = inst.RA, b = inst.RB, d = inst.RD;
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gpr.FlushLockX(ECX);
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gpr.Lock(a, b, d);
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gpr.Lock(a, b, d);
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if (d != a && d != b)
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if (d != a && d != b)
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gpr.LoadToX64(d, false);
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gpr.LoadToX64(d, false);
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@ -682,9 +681,8 @@ void Jit64::addex(UGeckoInstruction inst)
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MOV(32, R(EAX), gpr.R(a));
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MOV(32, R(EAX), gpr.R(a));
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ADC(32, R(EAX), gpr.R(b));
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ADC(32, R(EAX), gpr.R(b));
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MOV(32, gpr.R(d), R(EAX));
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MOV(32, gpr.R(d), R(EAX));
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GenerateCarry(ECX);
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GenerateCarry();
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gpr.UnlockAll();
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gpr.UnlockAll();
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gpr.UnlockAllX();
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if (inst.Rc)
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if (inst.Rc)
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{
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{
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CALL((u8*)asm_routines.computeRc);
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CALL((u8*)asm_routines.computeRc);
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