From cac8fa8afc246dafce5ef132bb9ce0fcb34483de Mon Sep 17 00:00:00 2001 From: Marko Pusljar Date: Mon, 22 Mar 2010 16:32:48 +0000 Subject: [PATCH] DSPLLE - small fix git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@5221 8ced0084-cf51-0410-be5f-012b33b47a6e --- Source/Core/DSPCore/Src/DSPAnalyzer.cpp | 8 +- Source/Core/DSPCore/Src/DSPAnalyzer.h | 3 +- Source/Core/DSPCore/Src/DSPTables.cpp | 140 ++++++++++++------------ Source/Core/DSPCore/Src/DSPTables.h | 2 - Source/Core/DSPCore/Src/assemble.cpp | 4 +- Source/Core/DSPCore/Src/disassemble.cpp | 4 +- 6 files changed, 80 insertions(+), 81 deletions(-) diff --git a/Source/Core/DSPCore/Src/DSPAnalyzer.cpp b/Source/Core/DSPCore/Src/DSPAnalyzer.cpp index 2400f27274..80b86d728c 100644 --- a/Source/Core/DSPCore/Src/DSPAnalyzer.cpp +++ b/Source/Core/DSPCore/Src/DSPAnalyzer.cpp @@ -90,17 +90,18 @@ void AnalyzeRange(int start_addr, int end_addr) continue; } code_flags[addr] |= CODE_START_OF_INST; - addr += opcode->size; - - // Look for loops. + // Look for loops. (this is not used atm) if ((inst.hex & 0xffe0) == 0x0060 || (inst.hex & 0xff00) == 0x1100) { // BLOOP, BLOOPI u16 loop_end = dsp_imem_read(addr + 1); + code_flags[addr] |= CODE_LOOP_START; code_flags[loop_end] |= CODE_LOOP_END; } else if ((inst.hex & 0xffe0) == 0x0040 || (inst.hex & 0xff00) == 0x1000) { // LOOP, LOOPI + code_flags[addr] |= CODE_LOOP_START; code_flags[addr + 1] |= CODE_LOOP_END; } + addr += opcode->size; } // Next, we'll scan for potential idle skips. @@ -122,7 +123,6 @@ void AnalyzeRange(int start_addr, int end_addr) { NOTICE_LOG(DSPLLE, "Idle skip location found at %02x", addr); code_flags[addr] |= CODE_IDLE_SKIP; - // TODO: actually use this flag somewhere. } } } diff --git a/Source/Core/DSPCore/Src/DSPAnalyzer.h b/Source/Core/DSPCore/Src/DSPAnalyzer.h index 916ebb3024..135e3e70a7 100644 --- a/Source/Core/DSPCore/Src/DSPAnalyzer.h +++ b/Source/Core/DSPCore/Src/DSPAnalyzer.h @@ -30,7 +30,8 @@ enum { CODE_START_OF_INST = 1, CODE_IDLE_SKIP = 2, - CODE_LOOP_END = 4, + CODE_LOOP_START = 4, + CODE_LOOP_END = 8, }; // Easy to query array covering the whole of instruction memory. diff --git a/Source/Core/DSPCore/Src/DSPTables.cpp b/Source/Core/DSPCore/Src/DSPTables.cpp index f611158e4a..7b5326a3f3 100644 --- a/Source/Core/DSPCore/Src/DSPTables.cpp +++ b/Source/Core/DSPCore/Src/DSPTables.cpp @@ -177,96 +177,96 @@ const DSPOPCTemplate opcodes[] = // extended opcodes, note size of opcode will be set to 0 //3 - main opcode defined by 9 bits, extension defined by last 7 bits!! - {"XORR", 0x3000, 0xfc80, DSPInterpreter::xorr, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100},{P_REG1A, 1, 0, 9, 0x0200}}, true}, - {"ANDR", 0x3400, 0xfc80, DSPInterpreter::andr, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100},{P_REG1A, 1, 0, 9, 0x0200}}, true}, - {"ORR", 0x3800, 0xfc80, DSPInterpreter::orr, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100},{P_REG1A, 1, 0, 9, 0x0200}}, true}, - {"ANDC", 0x3c00, 0xfe80, DSPInterpreter::andc, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100},{P_ACCM_D, 1, 0, 8, 0x0100}}, true}, - {"ORC", 0x3e00, 0xfe80, DSPInterpreter::orc, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100},{P_ACCM_D, 1, 0, 8, 0x0100}}, true}, - {"XORC", 0x3080, 0xfe80, DSPInterpreter::xorc, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100},{P_ACCM_D, 1, 0, 8, 0x0100}}, true}, - {"NOT", 0x3280, 0xfe80, DSPInterpreter::notc, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, true}, - {"LSRNRX", 0x3480, 0xfc80, DSPInterpreter::lsrnrx, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100},{P_REG1A, 1, 0, 9, 0x0200}}, true}, - {"ASRNRX", 0x3880, 0xfc80, DSPInterpreter::asrnrx, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100},{P_REG1A, 1, 0, 9, 0x0200}}, true}, - {"LSRNR", 0x3c80, 0xfe80, DSPInterpreter::lsrnr, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100},{P_ACCM_D, 1, 0, 8, 0x0100}}, true}, - {"ASRNR", 0x3e80, 0xfe80, DSPInterpreter::asrnr, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100},{P_ACCM_D, 1, 0, 8, 0x0100}}, true}, + {"XORR", 0x3000, 0xfc80, DSPInterpreter::xorr, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100},{P_REG1A, 1, 0, 9, 0x0200}}, true}, + {"ANDR", 0x3400, 0xfc80, DSPInterpreter::andr, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100},{P_REG1A, 1, 0, 9, 0x0200}}, true}, + {"ORR", 0x3800, 0xfc80, DSPInterpreter::orr, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100},{P_REG1A, 1, 0, 9, 0x0200}}, true}, + {"ANDC", 0x3c00, 0xfe80, DSPInterpreter::andc, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100},{P_ACCM_D, 1, 0, 8, 0x0100}}, true}, + {"ORC", 0x3e00, 0xfe80, DSPInterpreter::orc, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100},{P_ACCM_D, 1, 0, 8, 0x0100}}, true}, + {"XORC", 0x3080, 0xfe80, DSPInterpreter::xorc, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100},{P_ACCM_D, 1, 0, 8, 0x0100}}, true}, + {"NOT", 0x3280, 0xfe80, DSPInterpreter::notc, nop, 1, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, true}, + {"LSRNRX", 0x3480, 0xfc80, DSPInterpreter::lsrnrx, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100},{P_REG1A, 1, 0, 9, 0x0200}}, true}, + {"ASRNRX", 0x3880, 0xfc80, DSPInterpreter::asrnrx, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100},{P_REG1A, 1, 0, 9, 0x0200}}, true}, + {"LSRNR", 0x3c80, 0xfe80, DSPInterpreter::lsrnr, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100},{P_ACCM_D, 1, 0, 8, 0x0100}}, true}, + {"ASRNR", 0x3e80, 0xfe80, DSPInterpreter::asrnr, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100},{P_ACCM_D, 1, 0, 8, 0x0100}}, true}, //4 - {"ADDR", 0x4000, 0xf800, DSPInterpreter::addr, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, true}, - {"ADDAX", 0x4800, 0xfc00, DSPInterpreter::addax, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_AX, 1, 0, 9, 0x0200}}, true}, - {"ADD", 0x4c00, 0xfe00, DSPInterpreter::add, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, true}, - {"ADDP", 0x4e00, 0xfe00, DSPInterpreter::addp, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true}, + {"ADDR", 0x4000, 0xf800, DSPInterpreter::addr, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, true}, + {"ADDAX", 0x4800, 0xfc00, DSPInterpreter::addax, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_AX, 1, 0, 9, 0x0200}}, true}, + {"ADD", 0x4c00, 0xfe00, DSPInterpreter::add, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, true}, + {"ADDP", 0x4e00, 0xfe00, DSPInterpreter::addp, nop, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true}, //5 - {"SUBR", 0x5000, 0xf800, DSPInterpreter::subr, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, true}, - {"SUBAX", 0x5800, 0xfc00, DSPInterpreter::subax, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_AX, 1, 0, 9, 0x0200}}, true}, - {"SUB", 0x5c00, 0xfe00, DSPInterpreter::sub, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, true}, - {"SUBP", 0x5e00, 0xfe00, DSPInterpreter::subp, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true}, + {"SUBR", 0x5000, 0xf800, DSPInterpreter::subr, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, true}, + {"SUBAX", 0x5800, 0xfc00, DSPInterpreter::subax, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_AX, 1, 0, 9, 0x0200}}, true}, + {"SUB", 0x5c00, 0xfe00, DSPInterpreter::sub, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, true}, + {"SUBP", 0x5e00, 0xfe00, DSPInterpreter::subp, nop, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true}, //6 - {"MOVR", 0x6000, 0xf800, DSPInterpreter::movr, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, true}, - {"MOVAX", 0x6800, 0xfc00, DSPInterpreter::movax, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_AX, 1, 0, 9, 0x0200}}, true}, - {"MOV", 0x6c00, 0xfe00, DSPInterpreter::mov, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, true}, - {"MOVP", 0x6e00, 0xfe00, DSPInterpreter::movp, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true}, + {"MOVR", 0x6000, 0xf800, DSPInterpreter::movr, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, true}, + {"MOVAX", 0x6800, 0xfc00, DSPInterpreter::movax, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_AX, 1, 0, 9, 0x0200}}, true}, + {"MOV", 0x6c00, 0xfe00, DSPInterpreter::mov, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, true}, + {"MOVP", 0x6e00, 0xfe00, DSPInterpreter::movp, nop, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true}, //7 - {"ADDAXL", 0x7000, 0xfc00, DSPInterpreter::addaxl, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0200}}, true}, - {"INCM", 0x7400, 0xfe00, DSPInterpreter::incm, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, true}, - {"INC", 0x7600, 0xfe00, DSPInterpreter::inc, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true}, - {"DECM", 0x7800, 0xfe00, DSPInterpreter::decm, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, true}, - {"DEC", 0x7a00, 0xfe00, DSPInterpreter::dec, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true}, - {"NEG", 0x7c00, 0xfe00, DSPInterpreter::neg, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true}, - {"MOVNP", 0x7e00, 0xfe00, DSPInterpreter::movnp, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true}, + {"ADDAXL", 0x7000, 0xfc00, DSPInterpreter::addaxl, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0200}}, true}, + {"INCM", 0x7400, 0xfe00, DSPInterpreter::incm, nop, 1, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, true}, + {"INC", 0x7600, 0xfe00, DSPInterpreter::inc, nop, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true}, + {"DECM", 0x7800, 0xfe00, DSPInterpreter::decm, nop, 1, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, true}, + {"DEC", 0x7a00, 0xfe00, DSPInterpreter::dec, nop, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true}, + {"NEG", 0x7c00, 0xfe00, DSPInterpreter::neg, nop, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true}, + {"MOVNP", 0x7e00, 0xfe00, DSPInterpreter::movnp, nop, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true}, //8 - {"NX", 0x8000, 0xf700, DSPInterpreter::nx, nop, 1 | P_EXT, 0, {}, true}, - {"CLR", 0x8100, 0xf700, DSPInterpreter::clr, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true}, - {"CMP", 0x8200, 0xff00, DSPInterpreter::cmp, nop, 1 | P_EXT, 0, {}, true}, - {"MULAXH", 0x8300, 0xff00, DSPInterpreter::mulaxh, nop, 1 | P_EXT, 0, {}, true}, - {"CLRP", 0x8400, 0xff00, DSPInterpreter::clrp, nop, 1 | P_EXT, 0, {}, true}, - {"TSTPROD", 0x8500, 0xff00, DSPInterpreter::tstprod, nop, 1 | P_EXT, 0, {}, true}, - {"TSTAXH", 0x8600, 0xfe00, DSPInterpreter::tstaxh, nop, 1 | P_EXT, 1, {{P_REG1A, 1, 0, 8, 0x0100}}, true}, - {"M2", 0x8a00, 0xff00, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, true}, - {"M0", 0x8b00, 0xff00, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, true}, - {"CLR15", 0x8c00, 0xff00, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, true}, - {"SET15", 0x8d00, 0xff00, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, true}, - {"SET16", 0x8e00, 0xff00, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, true}, - {"SET40", 0x8f00, 0xff00, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, true}, + {"NX", 0x8000, 0xf700, DSPInterpreter::nx, nop, 1, 0, {}, true}, + {"CLR", 0x8100, 0xf700, DSPInterpreter::clr, nop, 1, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true}, + {"CMP", 0x8200, 0xff00, DSPInterpreter::cmp, nop, 1, 0, {}, true}, + {"MULAXH", 0x8300, 0xff00, DSPInterpreter::mulaxh, nop, 1, 0, {}, true}, + {"CLRP", 0x8400, 0xff00, DSPInterpreter::clrp, nop, 1, 0, {}, true}, + {"TSTPROD", 0x8500, 0xff00, DSPInterpreter::tstprod, nop, 1, 0, {}, true}, + {"TSTAXH", 0x8600, 0xfe00, DSPInterpreter::tstaxh, nop, 1, 1, {{P_REG1A, 1, 0, 8, 0x0100}}, true}, + {"M2", 0x8a00, 0xff00, DSPInterpreter::srbith, nop, 1, 0, {}, true}, + {"M0", 0x8b00, 0xff00, DSPInterpreter::srbith, nop, 1, 0, {}, true}, + {"CLR15", 0x8c00, 0xff00, DSPInterpreter::srbith, nop, 1, 0, {}, true}, + {"SET15", 0x8d00, 0xff00, DSPInterpreter::srbith, nop, 1, 0, {}, true}, + {"SET16", 0x8e00, 0xff00, DSPInterpreter::srbith, nop, 1, 0, {}, true}, + {"SET40", 0x8f00, 0xff00, DSPInterpreter::srbith, nop, 1, 0, {}, true}, //9 - {"MUL", 0x9000, 0xf700, DSPInterpreter::mul, nop, 1 | P_EXT, 2, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}}, true}, - {"ASR16", 0x9100, 0xf700, DSPInterpreter::asr16, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true}, - {"MULMVZ", 0x9200, 0xf600, DSPInterpreter::mulmvz, nop, 1 | P_EXT, 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true}, - {"MULAC", 0x9400, 0xf600, DSPInterpreter::mulac, nop, 1 | P_EXT, 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true}, - {"MULMV", 0x9600, 0xf600, DSPInterpreter::mulmv, nop, 1 | P_EXT, 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true}, + {"MUL", 0x9000, 0xf700, DSPInterpreter::mul, nop, 1, 2, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}}, true}, + {"ASR16", 0x9100, 0xf700, DSPInterpreter::asr16, nop, 1, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true}, + {"MULMVZ", 0x9200, 0xf600, DSPInterpreter::mulmvz, nop, 1, 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true}, + {"MULAC", 0x9400, 0xf600, DSPInterpreter::mulac, nop, 1, 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true}, + {"MULMV", 0x9600, 0xf600, DSPInterpreter::mulmv, nop, 1, 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true}, //a-b - {"MULX", 0xa000, 0xe700, DSPInterpreter::mulx, nop, 1 | P_EXT, 2, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}}, true}, - {"ABS", 0xa100, 0xf700, DSPInterpreter::abs, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true}, - {"MULXMVZ", 0xa200, 0xe600, DSPInterpreter::mulxmvz, nop, 1 | P_EXT, 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true}, - {"MULXAC", 0xa400, 0xe600, DSPInterpreter::mulxac, nop, 1 | P_EXT, 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true}, - {"MULXMV", 0xa600, 0xe600, DSPInterpreter::mulxmv, nop, 1 | P_EXT, 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true}, - {"TST", 0xb100, 0xf700, DSPInterpreter::tst, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true}, + {"MULX", 0xa000, 0xe700, DSPInterpreter::mulx, nop, 1, 2, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}}, true}, + {"ABS", 0xa100, 0xf700, DSPInterpreter::abs, nop, 1, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true}, + {"MULXMVZ", 0xa200, 0xe600, DSPInterpreter::mulxmvz, nop, 1, 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true}, + {"MULXAC", 0xa400, 0xe600, DSPInterpreter::mulxac, nop, 1, 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true}, + {"MULXMV", 0xa600, 0xe600, DSPInterpreter::mulxmv, nop, 1, 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true}, + {"TST", 0xb100, 0xf700, DSPInterpreter::tst, nop, 1, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true}, //c-d - {"MULC", 0xc000, 0xe700, DSPInterpreter::mulc, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}}, true}, - {"CMPAR" , 0xc100, 0xe700, DSPInterpreter::cmpar, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}}, true}, - {"MULCMVZ", 0xc200, 0xe600, DSPInterpreter::mulcmvz, nop, 1 | P_EXT, 3, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true}, - {"MULCAC", 0xc400, 0xe600, DSPInterpreter::mulcac, nop, 1 | P_EXT, 3, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true}, - {"MULCMV", 0xc600, 0xe600, DSPInterpreter::mulcmv, nop, 1 | P_EXT, 3, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true}, + {"MULC", 0xc000, 0xe700, DSPInterpreter::mulc, nop, 1, 2, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}}, true}, + {"CMPAR" , 0xc100, 0xe700, DSPInterpreter::cmpar, nop, 1, 2, {{P_ACC, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}}, true}, + {"MULCMVZ", 0xc200, 0xe600, DSPInterpreter::mulcmvz, nop, 1, 3, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true}, + {"MULCAC", 0xc400, 0xe600, DSPInterpreter::mulcac, nop, 1, 3, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true}, + {"MULCMV", 0xc600, 0xe600, DSPInterpreter::mulcmv, nop, 1, 3, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true}, //e - {"MADDX", 0xe000, 0xfc00, DSPInterpreter::maddx, nop, 1 | P_EXT, 2, {{P_REGM18, 1, 0, 8, 0x0200}, {P_REGM19, 1, 0, 7, 0x0100}}, true}, - {"MSUBX", 0xe400, 0xfc00, DSPInterpreter::msubx, nop, 1 | P_EXT, 2, {{P_REGM18, 1, 0, 8, 0x0200}, {P_REGM19, 1, 0, 7, 0x0100}}, true}, - {"MADDC", 0xe800, 0xfc00, DSPInterpreter::maddc, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 9, 0x0200}, {P_REG19, 1, 0, 7, 0x0100}}, true}, - {"MSUBC", 0xec00, 0xfc00, DSPInterpreter::msubc, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 9, 0x0200}, {P_REG19, 1, 0, 7, 0x0100}}, true}, + {"MADDX", 0xe000, 0xfc00, DSPInterpreter::maddx, nop, 1, 2, {{P_REGM18, 1, 0, 8, 0x0200}, {P_REGM19, 1, 0, 7, 0x0100}}, true}, + {"MSUBX", 0xe400, 0xfc00, DSPInterpreter::msubx, nop, 1, 2, {{P_REGM18, 1, 0, 8, 0x0200}, {P_REGM19, 1, 0, 7, 0x0100}}, true}, + {"MADDC", 0xe800, 0xfc00, DSPInterpreter::maddc, nop, 1, 2, {{P_ACCM, 1, 0, 9, 0x0200}, {P_REG19, 1, 0, 7, 0x0100}}, true}, + {"MSUBC", 0xec00, 0xfc00, DSPInterpreter::msubc, nop, 1, 2, {{P_ACCM, 1, 0, 9, 0x0200}, {P_REG19, 1, 0, 7, 0x0100}}, true}, //f - {"LSL16", 0xf000, 0xfe00, DSPInterpreter::lsl16, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true}, - {"MADD", 0xf200, 0xfe00, DSPInterpreter::madd, nop, 1 | P_EXT, 2, {{P_REG18, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 8, 0x0100}}, true}, - {"LSR16", 0xf400, 0xfe00, DSPInterpreter::lsr16, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true}, - {"MSUB", 0xf600, 0xfe00, DSPInterpreter::msub , nop, 1 | P_EXT, 2, {{P_REG18, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 8, 0x0100}}, true}, - {"ADDPAXZ", 0xf800, 0xfc00, DSPInterpreter::addpaxz, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 9, 0x0200}, {P_AX, 1, 0, 8, 0x0100}}, true}, //Think the args are wrong - {"CLRL", 0xfc00, 0xfe00, DSPInterpreter::clrl, nop, 1 | P_EXT, 1, {{P_ACCL, 1, 0, 11, 0x0800}}, true}, // clear acl0 - {"MOVPZ", 0xfe00, 0xfe00, DSPInterpreter::movpz, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true}, + {"LSL16", 0xf000, 0xfe00, DSPInterpreter::lsl16, nop, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true}, + {"MADD", 0xf200, 0xfe00, DSPInterpreter::madd, nop, 1, 2, {{P_REG18, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 8, 0x0100}}, true}, + {"LSR16", 0xf400, 0xfe00, DSPInterpreter::lsr16, nop, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true}, + {"MSUB", 0xf600, 0xfe00, DSPInterpreter::msub , nop, 1, 2, {{P_REG18, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 8, 0x0100}}, true}, + {"ADDPAXZ", 0xf800, 0xfc00, DSPInterpreter::addpaxz, nop, 1, 2, {{P_ACC, 1, 0, 9, 0x0200}, {P_AX, 1, 0, 8, 0x0100}}, true}, //Think the args are wrong + {"CLRL", 0xfc00, 0xfe00, DSPInterpreter::clrl, nop, 1, 1, {{P_ACCL, 1, 0, 11, 0x0800}}, true}, // clear acl0 + {"MOVPZ", 0xfe00, 0xfe00, DSPInterpreter::movpz, nop, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true}, }; const DSPOPCTemplate cw = diff --git a/Source/Core/DSPCore/Src/DSPTables.h b/Source/Core/DSPCore/Src/DSPTables.h index 6180d2543c..6e4fbdc6da 100644 --- a/Source/Core/DSPCore/Src/DSPTables.h +++ b/Source/Core/DSPCore/Src/DSPTables.h @@ -64,8 +64,6 @@ enum partype_t // P_AX_D = P_REG | 0x2280, }; -#define P_EXT 0x80 - #define OPTABLE_SIZE 0xffff + 1 #define EXT_OPTABLE_SIZE 0xff + 1 diff --git a/Source/Core/DSPCore/Src/assemble.cpp b/Source/Core/DSPCore/Src/assemble.cpp index adde65fa3b..a8a24e45c2 100644 --- a/Source/Core/DSPCore/Src/assemble.cpp +++ b/Source/Core/DSPCore/Src/assemble.cpp @@ -976,13 +976,13 @@ bool DSPAssembler::AssembleFile(const char *fname, int pass) if (!opc) opc = &cw; - opcode_size = opc->size & ~P_EXT; + opcode_size = opc->size; VerifyParams(opc, params, params_count); const opc_t *opc_ext = NULL; // Check for opcode extensions. - if (opc->size & P_EXT) + if (opc->extended) { if (opcode_ext) { diff --git a/Source/Core/DSPCore/Src/disassemble.cpp b/Source/Core/DSPCore/Src/disassemble.cpp index 5d785f3cf6..aef78c866a 100644 --- a/Source/Core/DSPCore/Src/disassemble.cpp +++ b/Source/Core/DSPCore/Src/disassemble.cpp @@ -270,7 +270,7 @@ bool DSPDisassembler::DisOpcode(const u16 *binbuf, int base_addr, int pass, u16 u32 op2; // Size 2 - the op has a large immediate. - if ((opc->size & ~P_EXT) == 2) + if (opc->size == 2) { op2 = binbuf[(*pc + 1) & 0x0fff]; if (settings_.show_hex) @@ -327,7 +327,7 @@ bool DSPDisassembler::DisOpcode(const u16 *binbuf, int base_addr, int pass, u16 if (extended) *pc += opc_ext->size; else - *pc += opc->size & ~P_EXT; + *pc += opc->size; if (pass == 2) dest.append(buffer);