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Merge Update_SR_Register64_Carry functions

This commit is contained in:
Sintendo 2015-02-04 22:18:28 +01:00
parent 34afe08de9
commit ca0790e9c9
3 changed files with 22 additions and 49 deletions
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3
Source/Core/Core/DSP/DSPEmitter.h
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@ -41,8 +41,7 @@ public:
// CC Util // CC Util
void Update_SR_Register64(Gen::X64Reg val = Gen::EAX); void Update_SR_Register64(Gen::X64Reg val = Gen::EAX);
void Update_SR_Register64_Carry(Gen::X64Reg val, Gen::X64Reg carry_ovfl); void Update_SR_Register64_Carry(Gen::X64Reg val, Gen::X64Reg carry_ovfl, bool carry_eq = false);
void Update_SR_Register64_Carry2(Gen::X64Reg val, Gen::X64Reg carry_ovfl);
void Update_SR_Register16(Gen::X64Reg val = Gen::EAX); void Update_SR_Register16(Gen::X64Reg val = Gen::EAX);
void Update_SR_Register16_OverS32(Gen::X64Reg val = Gen::EAX); void Update_SR_Register16_OverS32(Gen::X64Reg val = Gen::EAX);

20
Source/Core/Core/DSP/Jit/DSPJitArithmetic.cpp
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@ -179,7 +179,7 @@ void DSPEmitter::cmp(const UDSPInstruction opc)
SUB(64, R(RAX), R(RDX)); SUB(64, R(RAX), R(RDX));
// Update_SR_Register64(res, isCarry2(acc0, res), isOverflow(acc0, -acc1, res)); // CF -> influence on ABS/0xa100 // Update_SR_Register64(res, isCarry2(acc0, res), isOverflow(acc0, -acc1, res)); // CF -> influence on ABS/0xa100
NEG(64, R(RDX)); NEG(64, R(RDX));
Update_SR_Register64_Carry2(EAX, tmp1); Update_SR_Register64_Carry(EAX, tmp1, true);
gpr.putXReg(tmp1); gpr.putXReg(tmp1);
} }
} }
@ -210,7 +210,7 @@ void DSPEmitter::cmpar(const UDSPInstruction opc)
SUB(64, R(RAX), R(RDX)); SUB(64, R(RAX), R(RDX));
// Update_SR_Register64(res, isCarry2(sr, res), isOverflow(sr, -rr, res)); // Update_SR_Register64(res, isCarry2(sr, res), isOverflow(sr, -rr, res));
NEG(64, R(RDX)); NEG(64, R(RDX));
Update_SR_Register64_Carry2(EAX, tmp1); Update_SR_Register64_Carry(EAX, tmp1, true);
gpr.putXReg(tmp1); gpr.putXReg(tmp1);
} }
} }
@ -239,7 +239,7 @@ void DSPEmitter::cmpi(const UDSPInstruction opc)
SUB(64, R(RAX), R(RDX)); SUB(64, R(RAX), R(RDX));
// Update_SR_Register64(res, isCarry2(val, res), isOverflow(val, -imm, res)); // Update_SR_Register64(res, isCarry2(val, res), isOverflow(val, -imm, res));
NEG(64, R(RDX)); NEG(64, R(RDX));
Update_SR_Register64_Carry2(EAX, tmp1); Update_SR_Register64_Carry(EAX, tmp1, true);
gpr.putXReg(tmp1); gpr.putXReg(tmp1);
} }
} }
@ -268,7 +268,7 @@ void DSPEmitter::cmpis(const UDSPInstruction opc)
SUB(64, R(RAX), R(RDX)); SUB(64, R(RAX), R(RDX));
// Update_SR_Register64(res, isCarry2(acc, res), isOverflow(acc, -val, res)); // Update_SR_Register64(res, isCarry2(acc, res), isOverflow(acc, -val, res));
NEG(64, R(RDX)); NEG(64, R(RDX));
Update_SR_Register64_Carry2(EAX, tmp1); Update_SR_Register64_Carry(EAX, tmp1, true);
gpr.putXReg(tmp1); gpr.putXReg(tmp1);
} }
} }
@ -862,7 +862,7 @@ void DSPEmitter::subr(const UDSPInstruction opc)
NEG(64, R(RDX)); NEG(64, R(RDX));
MOV(64, R(RCX), R(RAX)); MOV(64, R(RCX), R(RAX));
set_long_acc(dreg, RCX); set_long_acc(dreg, RCX);
Update_SR_Register64_Carry2(EAX, tmp1); Update_SR_Register64_Carry(EAX, tmp1, true);
} }
else else
{ {
@ -898,7 +898,7 @@ void DSPEmitter::subax(const UDSPInstruction opc)
NEG(64, R(RDX)); NEG(64, R(RDX));
MOV(64, R(RCX), R(RAX)); MOV(64, R(RCX), R(RAX));
set_long_acc(dreg, RCX); set_long_acc(dreg, RCX);
Update_SR_Register64_Carry2(EAX, tmp1); Update_SR_Register64_Carry(EAX, tmp1, true);
} }
else else
{ {
@ -932,7 +932,7 @@ void DSPEmitter::sub(const UDSPInstruction opc)
NEG(64, R(RDX)); NEG(64, R(RDX));
MOV(64, R(RCX), R(RAX)); MOV(64, R(RCX), R(RAX));
set_long_acc(dreg, RCX); set_long_acc(dreg, RCX);
Update_SR_Register64_Carry2(EAX, tmp1); Update_SR_Register64_Carry(EAX, tmp1, true);
} }
else else
{ {
@ -966,7 +966,7 @@ void DSPEmitter::subp(const UDSPInstruction opc)
NEG(64, R(RDX)); NEG(64, R(RDX));
MOV(64, R(RCX), R(RAX)); MOV(64, R(RCX), R(RAX));
set_long_acc(dreg, RCX); set_long_acc(dreg, RCX);
Update_SR_Register64_Carry2(EAX, tmp1); Update_SR_Register64_Carry(EAX, tmp1, true);
} }
else else
{ {
@ -999,7 +999,7 @@ void DSPEmitter::decm(const UDSPInstruction opc)
MOV(64, R(RDX), Imm64(-subtract)); MOV(64, R(RDX), Imm64(-subtract));
MOV(64, R(RCX), R(RAX)); MOV(64, R(RCX), R(RAX));
set_long_acc(dreg, RCX); set_long_acc(dreg, RCX);
Update_SR_Register64_Carry2(EAX, tmp1); Update_SR_Register64_Carry(EAX, tmp1, true);
} }
else else
{ {
@ -1031,7 +1031,7 @@ void DSPEmitter::dec(const UDSPInstruction opc)
MOV(64, R(RDX), Imm64(-1)); MOV(64, R(RDX), Imm64(-1));
MOV(64, R(RCX), R(RAX)); MOV(64, R(RCX), R(RAX));
set_long_acc(dreg, RCX); set_long_acc(dreg, RCX);
Update_SR_Register64_Carry2(EAX, tmp1); Update_SR_Register64_Carry(EAX, tmp1, true);
} }
else else
{ {

48
Source/Core/Core/DSP/Jit/DSPJitCCUtil.cpp
View File

@ -67,7 +67,7 @@ void DSPEmitter::Update_SR_Register64(Gen::X64Reg val)
// In: (val): s64 _Value // In: (val): s64 _Value
// In: (carry_ovfl): 1 = carry, 2 = overflow // In: (carry_ovfl): 1 = carry, 2 = overflow
// Clobbers RDX // Clobbers RDX
void DSPEmitter::Update_SR_Register64_Carry(X64Reg val, X64Reg carry_ovfl) void DSPEmitter::Update_SR_Register64_Carry(X64Reg val, X64Reg carry_ovfl, bool carry_eq)
{ {
OpArg sr_reg; OpArg sr_reg;
gpr.getReg(DSP_REG_SR,sr_reg); gpr.getReg(DSP_REG_SR,sr_reg);
@ -79,7 +79,8 @@ void DSPEmitter::Update_SR_Register64_Carry(X64Reg val, X64Reg carry_ovfl)
// 0x01 // 0x01
// g_dsp.r[DSP_REG_SR] |= SR_CARRY; // g_dsp.r[DSP_REG_SR] |= SR_CARRY;
// Carry = (acc>res) // Carry = (acc>res)
FixupBranch noCarry = J_CC(CC_BE); // Carry2 = (acc>=res)
FixupBranch noCarry = J_CC(carry_eq ? CC_B : CC_BE);
OR(16, sr_reg, Imm16(SR_CARRY)); OR(16, sr_reg, Imm16(SR_CARRY));
SetJumpTarget(noCarry); SetJumpTarget(noCarry);
@ -95,41 +96,14 @@ void DSPEmitter::Update_SR_Register64_Carry(X64Reg val, X64Reg carry_ovfl)
SetJumpTarget(noOverflow); SetJumpTarget(noOverflow);
gpr.putReg(DSP_REG_SR); gpr.putReg(DSP_REG_SR);
Update_SR_Register(val); if (carry_eq)
} {
Update_SR_Register();
// In: (val): s64 _Value }
// In: (carry_ovfl): 1 = carry, 2 = overflow else
// Clobbers RDX {
void DSPEmitter::Update_SR_Register64_Carry2(X64Reg val, X64Reg carry_ovfl) Update_SR_Register(val);
{ }
OpArg sr_reg;
gpr.getReg(DSP_REG_SR,sr_reg);
// g_dsp.r[DSP_REG_SR] &= ~SR_CMP_MASK;
AND(16, sr_reg, Imm16(~SR_CMP_MASK));
CMP(64, R(carry_ovfl), R(val));
// 0x01
// g_dsp.r[DSP_REG_SR] |= SR_CARRY;
// Carry2 = (acc>=res)
FixupBranch noCarry2 = J_CC(CC_B);
OR(16, sr_reg, Imm16(SR_CARRY));
SetJumpTarget(noCarry2);
// 0x02 and 0x80
// g_dsp.r[DSP_REG_SR] |= SR_OVERFLOW;
// g_dsp.r[DSP_REG_SR] |= SR_OVERFLOW_STICKY;
// Overflow = ((acc ^ res) & (ax ^ res)) < 0
XOR(64, R(carry_ovfl), R(val));
XOR(64, R(RDX), R(val));
TEST(64, R(carry_ovfl), R(RDX));
FixupBranch noOverflow = J_CC(CC_GE);
OR(16, sr_reg, Imm16(SR_OVERFLOW | SR_OVERFLOW_STICKY));
SetJumpTarget(noOverflow);
gpr.putReg(DSP_REG_SR);
Update_SR_Register();
} }
// In: RAX: s64 _Value // In: RAX: s64 _Value