diff --git a/Source/Core/Core/PowerPC/JitArm64/JitAsm.cpp b/Source/Core/Core/PowerPC/JitArm64/JitAsm.cpp index db5b2344f2..0cfece976c 100644 --- a/Source/Core/Core/PowerPC/JitArm64/JitAsm.cpp +++ b/Source/Core/Core/PowerPC/JitArm64/JitAsm.cpp @@ -115,10 +115,14 @@ void JitArm64::GenerateAsm() } else { - // iCache[(address >> 2) & iCache_Mask]; ARM64Reg pc_masked = ARM64Reg::W8; ARM64Reg cache_base = ARM64Reg::X9; ARM64Reg block = ARM64Reg::X10; + ARM64Reg pc = ARM64Reg::W11; + ARM64Reg msr = ARM64Reg::W12; + ARM64Reg msr2 = ARM64Reg::W13; + + // iCache[(address >> 2) & iCache_Mask]; ORR(pc_masked, ARM64Reg::WZR, LogicalImm(JitBaseBlockCache::FAST_BLOCK_MAP_FALLBACK_MASK << 3, 32)); AND(pc_masked, pc_masked, DISPATCHER_PC, ArithOption(DISPATCHER_PC, ShiftType::LSL, 1)); @@ -127,22 +131,21 @@ void JitArm64::GenerateAsm() FixupBranch not_found = CBZ(block); // b.effectiveAddress != addr || b.msrBits != msr - ARM64Reg pc_and_msr = ARM64Reg::W11; - ARM64Reg pc_and_msr2 = ARM64Reg::W12; - LDR(IndexType::Unsigned, pc_and_msr, block, offsetof(JitBlockData, effectiveAddress)); - CMP(pc_and_msr, DISPATCHER_PC); + static_assert(offsetof(JitBlockData, msrBits) + 4 == + offsetof(JitBlockData, effectiveAddress)); + LDP(IndexType::Signed, msr, pc, block, offsetof(JitBlockData, effectiveAddress)); + CMP(pc, DISPATCHER_PC); FixupBranch pc_mismatch = B(CC_NEQ); - LDR(IndexType::Unsigned, pc_and_msr2, PPC_REG, PPCSTATE_OFF(msr)); - AND(pc_and_msr2, pc_and_msr2, LogicalImm(JitBaseBlockCache::JIT_CACHE_MSR_MASK, 32)); - LDR(IndexType::Unsigned, pc_and_msr, block, offsetof(JitBlockData, msrBits)); - CMP(pc_and_msr, pc_and_msr2); - + LDR(IndexType::Unsigned, msr2, PPC_REG, PPCSTATE_OFF(msr)); + AND(msr2, msr2, LogicalImm(JitBaseBlockCache::JIT_CACHE_MSR_MASK, 32)); + CMP(msr, msr2); FixupBranch msr_mismatch = B(CC_NEQ); // return blocks[block_num].normalEntry; LDR(IndexType::Unsigned, block, block, offsetof(JitBlockData, normalEntry)); BR(block); + SetJumpTarget(not_found); SetJumpTarget(pc_mismatch); SetJumpTarget(msr_mismatch);