Merged JIT crXXX instructions (thanks XTra.KrazzY)
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@6012 8ced0084-cf51-0410-be5f-012b33b47a6e
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@ -209,14 +209,7 @@ public:
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void mcrf(UGeckoInstruction inst);
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void mcrxr(UGeckoInstruction inst);
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void crand(UGeckoInstruction inst);
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void crandc(UGeckoInstruction inst);
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void creqv(UGeckoInstruction inst);
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void crnand(UGeckoInstruction inst);
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void crnor(UGeckoInstruction inst);
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void cror(UGeckoInstruction inst);
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void crorc(UGeckoInstruction inst);
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void crxor(UGeckoInstruction inst);
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void crXXX(UGeckoInstruction inst);
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void reg_imm(UGeckoInstruction inst);
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@ -174,14 +174,14 @@ static GekkoOPTemplate table19[] =
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{
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{528, &Jit64::bcctrx}, //"bcctrx", OPTYPE_BRANCH, FL_ENDBLOCK}},
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{16, &Jit64::bclrx}, //"bclrx", OPTYPE_BRANCH, FL_ENDBLOCK}},
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{257, &Jit64::crand}, //"crand", OPTYPE_CR, FL_EVIL}},
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{129, &Jit64::crandc}, //"crandc", OPTYPE_CR, FL_EVIL}},
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{289, &Jit64::creqv}, //"creqv", OPTYPE_CR, FL_EVIL}},
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{225, &Jit64::crnand}, //"crnand", OPTYPE_CR, FL_EVIL}},
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{33, &Jit64::crnor}, //"crnor", OPTYPE_CR, FL_EVIL}},
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{449, &Jit64::cror}, //"cror", OPTYPE_CR, FL_EVIL}},
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{417, &Jit64::crorc}, //"crorc", OPTYPE_CR, FL_EVIL}},
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{193, &Jit64::crxor}, //"crxor", OPTYPE_CR, FL_EVIL}},
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{257, &Jit64::crXXX}, //"crand", OPTYPE_CR, FL_EVIL}},
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{129, &Jit64::crXXX}, //"crandc", OPTYPE_CR, FL_EVIL}},
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{289, &Jit64::crXXX}, //"creqv", OPTYPE_CR, FL_EVIL}},
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{225, &Jit64::crXXX}, //"crnand", OPTYPE_CR, FL_EVIL}},
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{33, &Jit64::crXXX}, //"crnor", OPTYPE_CR, FL_EVIL}},
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{449, &Jit64::crXXX}, //"cror", OPTYPE_CR, FL_EVIL}},
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{417, &Jit64::crXXX}, //"crorc", OPTYPE_CR, FL_EVIL}},
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{193, &Jit64::crXXX}, //"crxor", OPTYPE_CR, FL_EVIL}},
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{150, &Jit64::DoNothing}, //"isync", OPTYPE_ICACHE, FL_EVIL}},
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{0, &Jit64::mcrf}, //"mcrf", OPTYPE_SYSTEM, FL_EVIL}},
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@ -219,10 +219,11 @@ void Jit64::mcrxr(UGeckoInstruction inst)
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AND(32, M(&PowerPC::ppcState.spr[SPR_XER]), Imm32(0x0FFFFFFF));
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}
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void Jit64::crand(UGeckoInstruction inst)
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void Jit64::crXXX(UGeckoInstruction inst)
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{
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INSTRUCTION_START
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JITDISABLE(SystemRegisters)
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_dbg_assert_msg_(DYNA_REC, inst.OPCD == 19, "Invalid crXXX");
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// USES_CR
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@ -244,257 +245,45 @@ void Jit64::crand(UGeckoInstruction inst)
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SHR(8, R(ECX), Imm8(shiftB));
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// Compute combined bit
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AND(8, R(EAX), R(ECX));
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// Store result bit in CRBD
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AND(8, R(EAX), Imm8(0x8 >> (inst.CRBD & 3)));
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AND(8, M(&PowerPC::ppcState.cr_fast[inst.CRBD >> 2]), Imm8(~(0x8 >> (inst.CRBD & 3))));
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OR(8, M(&PowerPC::ppcState.cr_fast[inst.CRBD >> 2]), R(EAX));
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gpr.UnlockAllX();
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}
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void Jit64::crandc(UGeckoInstruction inst)
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{
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INSTRUCTION_START
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JITDISABLE(SystemRegisters)
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// USES_CR
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// Get bit CRBA in EAX aligned with bit CRBD
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int shiftA = (inst.CRBD & 3) - (inst.CRBA & 3);
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MOV(8, R(EAX), M(&PowerPC::ppcState.cr_fast[inst.CRBA >> 2]));
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if (shiftA < 0)
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SHL(8, R(EAX), Imm8(-shiftA));
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else if (shiftA > 0)
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SHR(8, R(EAX), Imm8(shiftA));
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// Get bit CRBB in ECX aligned with bit CRBD
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gpr.FlushLockX(ECX);
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int shiftB = (inst.CRBD & 3) - (inst.CRBB & 3);
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MOV(8, R(ECX), M(&PowerPC::ppcState.cr_fast[inst.CRBB >> 2]));
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if (shiftB < 0)
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SHL(8, R(ECX), Imm8(-shiftB));
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else if (shiftB > 0)
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SHR(8, R(ECX), Imm8(shiftB));
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// Compute combined bit
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NOT(8, R(ECX));
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AND(8, R(EAX), R(ECX));
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// Store result bit in CRBD
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AND(8, R(EAX), Imm8(0x8 >> (inst.CRBD & 3)));
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AND(8, M(&PowerPC::ppcState.cr_fast[inst.CRBD >> 2]), Imm8(~(0x8 >> (inst.CRBD & 3))));
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OR(8, M(&PowerPC::ppcState.cr_fast[inst.CRBD >> 2]), R(EAX));
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gpr.UnlockAllX();
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}
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void Jit64::creqv(UGeckoInstruction inst)
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{
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INSTRUCTION_START
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JITDISABLE(SystemRegisters)
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// USES_CR
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// Get bit CRBA in EAX aligned with bit CRBD
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int shiftA = (inst.CRBD & 3) - (inst.CRBA & 3);
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MOV(8, R(EAX), M(&PowerPC::ppcState.cr_fast[inst.CRBA >> 2]));
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if (shiftA < 0)
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SHL(8, R(EAX), Imm8(-shiftA));
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else if (shiftA > 0)
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SHR(8, R(EAX), Imm8(shiftA));
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// Get bit CRBB in ECX aligned with bit CRBD
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gpr.FlushLockX(ECX);
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int shiftB = (inst.CRBD & 3) - (inst.CRBB & 3);
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MOV(8, R(ECX), M(&PowerPC::ppcState.cr_fast[inst.CRBB >> 2]));
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if (shiftB < 0)
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SHL(8, R(ECX), Imm8(-shiftB));
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else if (shiftB > 0)
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SHR(8, R(ECX), Imm8(shiftB));
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// Compute combined bit
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XOR(8, R(EAX), R(ECX));
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NOT(8, R(EAX));
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// Store result bit in CRBD
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AND(8, R(EAX), Imm8(0x8 >> (inst.CRBD & 3)));
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AND(8, M(&PowerPC::ppcState.cr_fast[inst.CRBD >> 2]), Imm8(~(0x8 >> (inst.CRBD & 3))));
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OR(8, M(&PowerPC::ppcState.cr_fast[inst.CRBD >> 2]), R(EAX));
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gpr.UnlockAllX();
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}
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void Jit64::crnand(UGeckoInstruction inst)
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{
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INSTRUCTION_START
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JITDISABLE(SystemRegisters)
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// USES_CR
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// Get bit CRBA in EAX aligned with bit CRBD
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int shiftA = (inst.CRBD & 3) - (inst.CRBA & 3);
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MOV(8, R(EAX), M(&PowerPC::ppcState.cr_fast[inst.CRBA >> 2]));
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if (shiftA < 0)
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SHL(8, R(EAX), Imm8(-shiftA));
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else if (shiftA > 0)
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SHR(8, R(EAX), Imm8(shiftA));
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// Get bit CRBB in ECX aligned with bit CRBD
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gpr.FlushLockX(ECX);
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int shiftB = (inst.CRBD & 3) - (inst.CRBB & 3);
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MOV(8, R(ECX), M(&PowerPC::ppcState.cr_fast[inst.CRBB >> 2]));
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if (shiftB < 0)
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SHL(8, R(ECX), Imm8(-shiftB));
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else if (shiftB > 0)
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SHR(8, R(ECX), Imm8(shiftB));
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// Compute combined bit
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AND(8, R(EAX), R(ECX));
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NOT(8, R(EAX));
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// Store result bit in CRBD
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AND(8, R(EAX), Imm8(0x8 >> (inst.CRBD & 3)));
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AND(8, M(&PowerPC::ppcState.cr_fast[inst.CRBD >> 2]), Imm8(~(0x8 >> (inst.CRBD & 3))));
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OR(8, M(&PowerPC::ppcState.cr_fast[inst.CRBD >> 2]), R(EAX));
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gpr.UnlockAllX();
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}
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void Jit64::crnor(UGeckoInstruction inst)
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{
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INSTRUCTION_START
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JITDISABLE(SystemRegisters)
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// USES_CR
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// Get bit CRBA in EAX aligned with bit CRBD
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int shiftA = (inst.CRBD & 3) - (inst.CRBA & 3);
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MOV(8, R(EAX), M(&PowerPC::ppcState.cr_fast[inst.CRBA >> 2]));
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if (shiftA < 0)
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SHL(8, R(EAX), Imm8(-shiftA));
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else if (shiftA > 0)
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SHR(8, R(EAX), Imm8(shiftA));
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// Get bit CRBB in ECX aligned with bit CRBD
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gpr.FlushLockX(ECX);
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int shiftB = (inst.CRBD & 3) - (inst.CRBB & 3);
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MOV(8, R(ECX), M(&PowerPC::ppcState.cr_fast[inst.CRBB >> 2]));
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if (shiftB < 0)
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SHL(8, R(ECX), Imm8(-shiftB));
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else if (shiftB > 0)
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SHR(8, R(ECX), Imm8(shiftB));
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// Compute combined bit
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OR(8, R(EAX), R(ECX));
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NOT(8, R(EAX));
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// Store result bit in CRBD
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AND(8, R(EAX), Imm8(0x8 >> (inst.CRBD & 3)));
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AND(8, M(&PowerPC::ppcState.cr_fast[inst.CRBD >> 2]), Imm8(~(0x8 >> (inst.CRBD & 3))));
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OR(8, M(&PowerPC::ppcState.cr_fast[inst.CRBD >> 2]), R(EAX));
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gpr.UnlockAllX();
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}
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void Jit64::cror(UGeckoInstruction inst)
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{
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INSTRUCTION_START
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JITDISABLE(SystemRegisters)
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// USES_CR
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// Get bit CRBA in EAX aligned with bit CRBD
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int shiftA = (inst.CRBD & 3) - (inst.CRBA & 3);
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MOV(8, R(EAX), M(&PowerPC::ppcState.cr_fast[inst.CRBA >> 2]));
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if (shiftA < 0)
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SHL(8, R(EAX), Imm8(-shiftA));
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else if (shiftA > 0)
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SHR(8, R(EAX), Imm8(shiftA));
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// Get bit CRBB in ECX aligned with bit CRBD
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gpr.FlushLockX(ECX);
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int shiftB = (inst.CRBD & 3) - (inst.CRBB & 3);
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MOV(8, R(ECX), M(&PowerPC::ppcState.cr_fast[inst.CRBB >> 2]));
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if (shiftB < 0)
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SHL(8, R(ECX), Imm8(-shiftB));
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else if (shiftB > 0)
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SHR(8, R(ECX), Imm8(shiftB));
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// Compute combined bit
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OR(8, R(EAX), R(ECX));
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// Store result bit in CRBD
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AND(8, R(EAX), Imm8(0x8 >> (inst.CRBD & 3)));
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AND(8, M(&PowerPC::ppcState.cr_fast[inst.CRBD >> 2]), Imm8(~(0x8 >> (inst.CRBD & 3))));
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OR(8, M(&PowerPC::ppcState.cr_fast[inst.CRBD >> 2]), R(EAX));
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gpr.UnlockAllX();
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}
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void Jit64::crorc(UGeckoInstruction inst)
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{
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INSTRUCTION_START
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JITDISABLE(SystemRegisters)
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// USES_CR
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// Get bit CRBA in EAX aligned with bit CRBD
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int shiftA = (inst.CRBD & 3) - (inst.CRBA & 3);
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MOV(8, R(EAX), M(&PowerPC::ppcState.cr_fast[inst.CRBA >> 2]));
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if (shiftA < 0)
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SHL(8, R(EAX), Imm8(-shiftA));
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else if (shiftA > 0)
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SHR(8, R(EAX), Imm8(shiftA));
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// Get bit CRBB in ECX aligned with bit CRBD
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gpr.FlushLockX(ECX);
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int shiftB = (inst.CRBD & 3) - (inst.CRBB & 3);
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MOV(8, R(ECX), M(&PowerPC::ppcState.cr_fast[inst.CRBB >> 2]));
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if (shiftB < 0)
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SHL(8, R(ECX), Imm8(-shiftB));
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else if (shiftB > 0)
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SHR(8, R(ECX), Imm8(shiftB));
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// Compute combined bit
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NOT(8, R(ECX));
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OR(8, R(EAX), R(ECX));
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// Store result bit in CRBD
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AND(8, R(EAX), Imm8(0x8 >> (inst.CRBD & 3)));
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AND(8, M(&PowerPC::ppcState.cr_fast[inst.CRBD >> 2]), Imm8(~(0x8 >> (inst.CRBD & 3))));
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OR(8, M(&PowerPC::ppcState.cr_fast[inst.CRBD >> 2]), R(EAX));
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gpr.UnlockAllX();
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}
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void Jit64::crxor(UGeckoInstruction inst)
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{
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INSTRUCTION_START
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JITDISABLE(SystemRegisters)
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// USES_CR
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// Get bit CRBA in EAX aligned with bit CRBD
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int shiftA = (inst.CRBD & 3) - (inst.CRBA & 3);
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MOV(8, R(EAX), M(&PowerPC::ppcState.cr_fast[inst.CRBA >> 2]));
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if (shiftA < 0)
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SHL(8, R(EAX), Imm8(-shiftA));
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else if (shiftA > 0)
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SHR(8, R(EAX), Imm8(shiftA));
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// Get bit CRBB in ECX aligned with bit CRBD
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gpr.FlushLockX(ECX);
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int shiftB = (inst.CRBD & 3) - (inst.CRBB & 3);
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MOV(8, R(ECX), M(&PowerPC::ppcState.cr_fast[inst.CRBB >> 2]));
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if (shiftB < 0)
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SHL(8, R(ECX), Imm8(-shiftB));
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else if (shiftB > 0)
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SHR(8, R(ECX), Imm8(shiftB));
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// Compute combined bit
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XOR(8, R(EAX), R(ECX));
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switch(inst.SUBOP10)
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{
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case 33: // crnor
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OR(8, R(EAX), R(ECX));
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NOT(8, R(EAX));
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break;
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case 129: // crandc
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NOT(8, R(ECX));
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AND(8, R(EAX), R(ECX));
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break;
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case 193: // crxor
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XOR(8, R(EAX), R(ECX));
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break;
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case 225: // crnand
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AND(8, R(EAX), R(ECX));
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NOT(8, R(EAX));
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break;
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case 257: // crand
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AND(8, R(EAX), R(ECX));
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break;
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case 289: // creqv
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XOR(8, R(EAX), R(ECX));
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NOT(8, R(EAX));
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break;
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case 417: // crorc
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NOT(8, R(ECX));
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OR(8, R(EAX), R(ECX));
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break;
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case 449: // cror
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OR(8, R(EAX), R(ECX));
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break;
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}
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// Store result bit in CRBD
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AND(8, R(EAX), Imm8(0x8 >> (inst.CRBD & 3)));
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