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Merge pull request #11114 from JosJuice/jitarm64-divwx-imm 

JitArm64: Fix divwx BindToRegister condition
This commit is contained in:
Admiral H. Curtiss 2022-10-02 01:10:48 +02:00 committed by GitHub
parent 6911e1b730 8984777749
commit c84835c53c
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 6 additions and 4 deletions
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10
Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp
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@ -476,9 +476,11 @@ void JitArm64::addx(UGeckoInstruction inst)
{
int imm_reg = gpr.IsImm(a) ? a : b;
int in_reg = gpr.IsImm(a) ? b : a;
int imm_value = gpr.GetImm(imm_reg);
gpr.BindToRegister(d, d == in_reg);
ARM64Reg WA = gpr.GetReg();
ADDI2R(gpr.R(d), gpr.R(in_reg), gpr.GetImm(imm_reg), WA);
ADDI2R(gpr.R(d), gpr.R(in_reg), imm_value, WA);
gpr.Unlock(WA);
if (inst.Rc)
ComputeRC0(gpr.R(d));
@ -745,11 +747,11 @@ void JitArm64::rlwnmx(UGeckoInstruction inst)
}
else if (gpr.IsImm(b))
{
int imm_value = gpr.GetImm(b) & 0x1f;
gpr.BindToRegister(a, a == s);
ARM64Reg WA = gpr.GetReg();
ArithOption Shift(gpr.R(s), ShiftType::ROR, 32 - (gpr.GetImm(b) & 0x1f));
MOVI2R(WA, mask);
AND(gpr.R(a), WA, gpr.R(s), Shift);
AND(gpr.R(a), WA, gpr.R(s), ArithOption(gpr.R(s), ShiftType::ROR, 32 - imm_value));
gpr.Unlock(WA);
if (inst.Rc)
ComputeRC0(gpr.R(a));
@ -1433,7 +1435,7 @@ void JitArm64::divwx(UGeckoInstruction inst)
{
const u32 dividend = gpr.GetImm(a);
gpr.BindToRegister(d, d == b);
gpr.BindToRegister(d, d == a || d == b);
ARM64Reg RB = gpr.R(b);
ARM64Reg RD = gpr.R(d);