JitArm64: CR field cleanup.
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3405f5ac1a
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c69903eb42
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@ -313,8 +313,7 @@ void JitArm64::fcmpX(UGeckoInstruction inst)
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}
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SetJumpTarget(continue1);
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STR(INDEX_UNSIGNED, XA, PPC_REG,
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PPCSTATE_OFF(cr_val[0]) + (sizeof(PowerPC::ppcState.cr_val[0]) * crf));
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STR(INDEX_UNSIGNED, XA, PPC_REG, PPCSTATE_OFF(cr_val[crf]));
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gpr.Unlock(WA);
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}
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@ -423,8 +423,7 @@ void JitArm64::cmp(UGeckoInstruction inst)
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SXTW(XB, RB);
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SUB(XA, XA, XB);
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STR(INDEX_UNSIGNED, XA, PPC_REG,
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PPCSTATE_OFF(cr_val[0]) + (sizeof(PowerPC::ppcState.cr_val[0]) * crf));
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STR(INDEX_UNSIGNED, XA, PPC_REG, PPCSTATE_OFF(cr_val[crf]));
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gpr.Unlock(WA, WB);
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}
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@ -451,8 +450,7 @@ void JitArm64::cmpl(UGeckoInstruction inst)
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ARM64Reg WA = gpr.GetReg();
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ARM64Reg XA = EncodeRegTo64(WA);
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SUB(XA, EncodeRegTo64(gpr.R(a)), EncodeRegTo64(gpr.R(b)));
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STR(INDEX_UNSIGNED, XA, PPC_REG,
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PPCSTATE_OFF(cr_val[0]) + (sizeof(PowerPC::ppcState.cr_val[0]) * crf));
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STR(INDEX_UNSIGNED, XA, PPC_REG, PPCSTATE_OFF(cr_val[crf]));
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gpr.Unlock(WA);
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}
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@ -502,8 +500,7 @@ void JitArm64::cmpli(UGeckoInstruction inst)
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SUBI2R(XA, EncodeRegTo64(gpr.R(a)), inst.UIMM, XA);
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STR(INDEX_UNSIGNED, XA, PPC_REG,
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PPCSTATE_OFF(cr_val[0]) + (sizeof(PowerPC::ppcState.cr_val[0]) * crf));
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STR(INDEX_UNSIGNED, XA, PPC_REG, PPCSTATE_OFF(cr_val[crf]));
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gpr.Unlock(WA);
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}
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@ -417,7 +417,7 @@ void JitArm64::crXXX(UGeckoInstruction inst)
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ARM64Reg WA = gpr.GetReg();
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ARM64Reg XA = EncodeRegTo64(WA);
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LDR(INDEX_UNSIGNED, XA, PPC_REG, PPCSTATE_OFF(cr_val) + 8 * field);
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LDR(INDEX_UNSIGNED, XA, PPC_REG, PPCSTATE_OFF(cr_val[field]));
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switch (bit)
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{
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case CR_SO_BIT:
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@ -436,7 +436,7 @@ void JitArm64::crXXX(UGeckoInstruction inst)
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AND(XA, XA, 64 - 63, 62, true); // XA & ~(1<<62)
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break;
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}
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STR(INDEX_UNSIGNED, XA, PPC_REG, PPCSTATE_OFF(cr_val) + 8 * field);
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STR(INDEX_UNSIGNED, XA, PPC_REG, PPCSTATE_OFF(cr_val[field]));
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gpr.Unlock(WA);
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return;
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}
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@ -450,7 +450,7 @@ void JitArm64::crXXX(UGeckoInstruction inst)
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ARM64Reg WA = gpr.GetReg();
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ARM64Reg XA = EncodeRegTo64(WA);
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LDR(INDEX_UNSIGNED, XA, PPC_REG, PPCSTATE_OFF(cr_val) + 8 * field);
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LDR(INDEX_UNSIGNED, XA, PPC_REG, PPCSTATE_OFF(cr_val[field]));
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if (bit != CR_GT_BIT)
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{
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@ -483,7 +483,7 @@ void JitArm64::crXXX(UGeckoInstruction inst)
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ORR(XA, XA, 32, 0, true); // XA | 1<<32
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STR(INDEX_UNSIGNED, XA, PPC_REG, PPCSTATE_OFF(cr_val) + 8 * field);
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STR(INDEX_UNSIGNED, XA, PPC_REG, PPCSTATE_OFF(cr_val[field]));
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gpr.Unlock(WA);
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return;
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}
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@ -509,7 +509,7 @@ void JitArm64::crXXX(UGeckoInstruction inst)
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ARM64Reg WC = gpr.GetReg();
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ARM64Reg XC = EncodeRegTo64(WC);
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LDR(INDEX_UNSIGNED, XC, PPC_REG, PPCSTATE_OFF(cr_val) + 8 * field);
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LDR(INDEX_UNSIGNED, XC, PPC_REG, PPCSTATE_OFF(cr_val[field]));
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switch (bit)
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{
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case CR_SO_BIT: // check bit 61 set
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@ -565,7 +565,7 @@ void JitArm64::crXXX(UGeckoInstruction inst)
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int field = inst.CRBD >> 2;
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int bit = 3 - (inst.CRBD & 3);
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LDR(INDEX_UNSIGNED, XB, PPC_REG, PPCSTATE_OFF(cr_val) + 8 * field);
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LDR(INDEX_UNSIGNED, XB, PPC_REG, PPCSTATE_OFF(cr_val[field]));
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// Gross but necessary; if the input is totally zero and we set SO or LT,
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// or even just add the (1<<32), GT will suddenly end up set without us
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@ -603,7 +603,7 @@ void JitArm64::crXXX(UGeckoInstruction inst)
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}
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ORR(XA, XA, 32, 0, true); // XA | 1<<32
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STR(INDEX_UNSIGNED, XB, PPC_REG, PPCSTATE_OFF(cr_val) + 8 * field);
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STR(INDEX_UNSIGNED, XB, PPC_REG, PPCSTATE_OFF(cr_val[field]));
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gpr.Unlock(WA);
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gpr.Unlock(WB);
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@ -653,7 +653,7 @@ void JitArm64::mtcrf(UGeckoInstruction inst)
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}
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LDR(XA, XB, ArithOption(XA, true));
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STR(INDEX_UNSIGNED, XA, PPC_REG, PPCSTATE_OFF(cr_val) + 8 * i);
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STR(INDEX_UNSIGNED, XA, PPC_REG, PPCSTATE_OFF(cr_val[i]));
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}
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}
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gpr.Unlock(WA, WB);
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@ -629,7 +629,7 @@ void JitArm64::GenMfcr()
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const u8* start = GetCodePtr();
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for (int i = 0; i < 8; i++)
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{
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LDR(INDEX_UNSIGNED, X1, PPC_REG, PPCSTATE_OFF(cr_val) + 8 * i);
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LDR(INDEX_UNSIGNED, X1, PPC_REG, PPCSTATE_OFF(cr_val[i]));
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// SO
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if (i == 0)
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