From c6661a2272ca6882365ef266323baf11ee7ae69a Mon Sep 17 00:00:00 2001 From: Nolan Check Date: Mon, 20 Jul 2009 16:33:55 +0000 Subject: [PATCH] Re-enable BP irq clearing. If this doesn't fix MP1 then I might as well revert r3855. git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@3858 8ced0084-cf51-0410-be5f-012b33b47a6e --- Source/Core/Core/Src/HW/CommandProcessor.cpp | 23 ++++++-------------- 1 file changed, 7 insertions(+), 16 deletions(-) diff --git a/Source/Core/Core/Src/HW/CommandProcessor.cpp b/Source/Core/Core/Src/HW/CommandProcessor.cpp index 4e3242f55d..ebcc55a91b 100644 --- a/Source/Core/Core/Src/HW/CommandProcessor.cpp +++ b/Source/Core/Core/Src/HW/CommandProcessor.cpp @@ -422,33 +422,24 @@ void Write16(const u16 _Value, const u32 _Address) Common::AtomicStore(fifo.bFF_GPLinkEnable, tmpCtrl.GPLinkEnable); Common::AtomicStore(fifo.bFF_BPEnable, tmpCtrl.BPEnable); - if (m_CPCtrlReg.BPEnable && !tmpCtrl.BPEnable) - { - fifo.bFF_Breakpoint = 0; - } - // TOCHECK (mb2): could BP irq be cleared with w16 to STATUS_REGISTER? // funny hack: eg in MP1 if we disable the clear breakpoint ability by commenting this block // the game is of course faster but looks stable too. // Well, the hack is more stable than the "proper" way actualy :p ... it breaks MP2 when ship lands // So I let the hack for now. + // Checkmate re-enabled it, so please test // TODO (mb2): fix this! // BP interrupt is cleared here - /* + //if (tmpCtrl.CPIntEnable) - //if (!m_CPCtrlReg.CPIntEnable && tmpCtrl.Hex) // raising edge + if (!m_CPCtrlReg.CPIntEnable && tmpCtrl.CPIntEnable) // raising edge //if (m_CPCtrlReg.CPIntEnable && !tmpCtrl.Hex) // falling edge { - LOG(COMMANDPROCESSOR,"\t ClearBreakpoint interrupt"); - // yes an SC hack, single core mode isn't very gc spec compliant :D - // TODO / FIXME : fix SC BPs. Only because it's pretty ugly to have a if{} here just for that. - if (Core::g_CoreStartupParameter.bUseDualCore) - { - m_CPStatusReg.Breakpoint = 0; - InterlockedExchange((LONG*)&fifo.bFF_Breakpoint, 0); - } - }*/ + m_CPStatusReg.Breakpoint = 0; + Common::AtomicStore(fifo.bFF_Breakpoint, 0); + } + m_CPCtrlReg.Hex = tmpCtrl.Hex; UpdateInterrupts(); DEBUG_LOG(COMMANDPROCESSOR,"\t write to CTRL_REGISTER : %04x", _Value);