Add the missing FPR cache
This commit is contained in:
Ryan Houdek
parent
717b976875
commit
be7643cd2d
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// Copyright (C) 2003 Dolphin Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official SVN repository and contact information can be found at
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// http://code.google.com/p/dolphin-emu/
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#include "JitFPRCache.h"
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ArmFPRCache::ArmFPRCache()
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{
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emit = 0;
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}
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void ArmFPRCache::Init(ARMXEmitter *emitter)
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{
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emit = emitter;
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ARMReg *PPCRegs = GetPPCAllocationOrder(NUMPPCREG);
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ARMReg *Regs = GetAllocationOrder(NUMARMREG);
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for(u8 a = 0; a < NUMPPCREG; ++a)
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{
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ArmCRegs[a].PPCReg = 33;
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ArmCRegs[a].Reg = PPCRegs[a];
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ArmCRegs[a].LastLoad = 0;
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ArmCRegs[a].PS1 = false;
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}
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for(u8 a = 0; a < NUMARMREG; ++a)
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{
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ArmRegs[a].Reg = Regs[a];
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ArmRegs[a].free = true;
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}
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}
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void ArmFPRCache::Start(PPCAnalyst::BlockRegStats &stats)
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{
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for(u8 a = 0; a < NUMPPCREG; ++a)
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{
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ArmCRegs[a].PPCReg = 33;
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ArmCRegs[a].LastLoad = 0;
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}
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}
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ARMReg *ArmFPRCache::GetPPCAllocationOrder(int &count)
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{
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// This will return us the allocation order of the registers we can use on
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// the ppc side.
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static ARMReg allocationOrder[] =
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{
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D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
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D11, D12, D13, D14, D15, D16, D17, D18, D19,
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D20, D21, D22, D23, D24, D25, D26, D27
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};
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count = sizeof(allocationOrder) / sizeof(const int);
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return allocationOrder;
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}
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ARMReg *ArmFPRCache::GetAllocationOrder(int &count)
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{
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// This will return us the allocation order of the registers we can use on
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// the host side.
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static ARMReg allocationOrder[] =
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{
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D31, D30, D29, D28
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};
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count = sizeof(allocationOrder) / sizeof(const int);
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return allocationOrder;
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}
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ARMReg ArmFPRCache::GetReg(bool AutoLock)
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{
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for(u8 a = 0; a < NUMARMREG; ++a)
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if(ArmRegs[a].free)
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{
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// Alright, this one is free
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if (AutoLock)
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ArmRegs[a].free = false;
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return ArmRegs[a].Reg;
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}
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// Uh Oh, we have all them locked....
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_assert_msg_(_DYNA_REC_, false, "All available registers are locked dumb dumb");
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return D31;
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}
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void ArmFPRCache::Unlock(ARMReg V0)
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{
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for(u8 RegNum = 0; RegNum < NUMARMREG; ++RegNum)
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{
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if(ArmRegs[RegNum].Reg == V0)
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{
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_assert_msg_(_DYNA_REC, !ArmRegs[RegNum].free, "This register is already unlocked");
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ArmRegs[RegNum].free = true;
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}
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}
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}
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ARMReg ArmFPRCache::GetPPCReg(u32 preg, bool PS1, bool preLoad)
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{
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u32 HighestUsed = 0;
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u8 Num = 0;
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for(u8 a = 0; a < NUMPPCREG; ++a){
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++ArmCRegs[a].LastLoad;
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if (ArmCRegs[a].LastLoad > HighestUsed)
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{
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HighestUsed = ArmCRegs[a].LastLoad;
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Num = a;
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}
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}
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// Check if already Loaded
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for(u8 a = 0; a < NUMPPCREG; ++a)
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if (ArmCRegs[a].PPCReg == preg && ArmCRegs[a].PS1 == PS1)
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{
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ArmCRegs[a].LastLoad = 0;
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return ArmCRegs[a].Reg;
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}
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// Check if we have a free register
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for (u8 a = 0; a < NUMPPCREG; ++a)
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if (ArmCRegs[a].PPCReg == 33)
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{
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u16 offset = STRUCT_OFF(PowerPC::ppcState, ps) + (preg * 16) + (PS1 ? 8 : 0);
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if (preLoad)
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emit->VLDR(ArmCRegs[a].Reg, R9, offset);
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ArmCRegs[a].PPCReg = preg;
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ArmCRegs[a].LastLoad = 0;
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ArmCRegs[a].PS1 = PS1;
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return ArmCRegs[a].Reg;
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}
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// Alright, we couldn't get a free space, dump that least used register
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u16 offsetOld = STRUCT_OFF(PowerPC::ppcState, ps) + (ArmCRegs[Num].PPCReg * 16) + (ArmCRegs[Num].PS1 ? 8 : 0);
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emit->VSTR(ArmCRegs[Num].Reg, R9, offsetOld);
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u16 offsetNew = STRUCT_OFF(PowerPC::ppcState, ps) + (preg * 16) + (PS1 ? 8 : 0);
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if (preLoad)
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emit->VLDR(ArmCRegs[Num].Reg, R9, offsetNew);
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ArmCRegs[Num].PPCReg = preg;
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ArmCRegs[Num].LastLoad = 0;
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ArmCRegs[Num].PS1 = PS1;
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return ArmCRegs[Num].Reg;
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}
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ARMReg ArmFPRCache::R0(u32 preg, bool preLoad)
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{
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return GetPPCReg(preg, false, preLoad);
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}
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ARMReg ArmFPRCache::R1(u32 preg, bool preLoad)
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{
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return GetPPCReg(preg, true, preLoad);
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}
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void ArmFPRCache::Flush()
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{
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for(u8 a = 0; a < NUMPPCREG; ++a)
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if (ArmCRegs[a].PPCReg != 33)
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{
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u16 offset = STRUCT_OFF(PowerPC::ppcState, ps) + (ArmCRegs[a].PPCReg * 16) + (ArmCRegs[a].PS1 ? 8 : 0);
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emit->VSTR(ArmCRegs[a].Reg, R9, offset);
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ArmCRegs[a].PPCReg = 33;
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ArmCRegs[a].LastLoad = 0;
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}
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}
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@ -0,0 +1,62 @@
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// Copyright (C) 2003 Dolphin Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official SVN repository and contact information can be found at
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// http://code.google.com/p/dolphin-emu/
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#ifndef _JITARMFPRCACHE_H
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#define _JITARMFPRCACHE_H
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#include "ArmEmitter.h"
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#include "../Gekko.h"
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#include "../PPCAnalyst.h"
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#include "JitRegCache.h"
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#define ARMFPUREGS 32
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using namespace ArmGen;
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class ArmFPRCache
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{
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private:
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PPCCachedReg regs[32];
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JRCPPC ArmCRegs[ARMFPUREGS];
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JRCReg ArmRegs[ARMFPUREGS];
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int NUMPPCREG;
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int NUMARMREG;
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ARMReg *GetAllocationOrder(int &count);
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ARMReg *GetPPCAllocationOrder(int &count);
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ARMReg GetPPCReg(u32 preg, bool PS1, bool preLoad);
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protected:
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ARMXEmitter *emit;
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public:
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ArmFPRCache();
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~ArmFPRCache() {}
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void Init(ARMXEmitter *emitter);
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void Start(PPCAnalyst::BlockRegStats &stats);
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void SetEmitter(ARMXEmitter *emitter) {emit = emitter;}
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ARMReg GetReg(bool AutoLock = true); // Return a ARM register we can use.
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void Unlock(ARMReg V0);
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void Flush();
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ARMReg R0(u32 preg, bool preLoad = true); // Returns a cached register
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ARMReg R1(u32 preg, bool preLoad = true);
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};
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#endif
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