[ARM] stmw implementation.

Source/Core/Core/Src/PowerPC/JitArm32/Jit.h

@@ -181,6 +181,7 @@ public:
 	void stX(UGeckoInstruction _inst);
 	void lXX(UGeckoInstruction _inst);
 	void lmw(UGeckoInstruction _inst);
+	void stmw(UGeckoInstruction _inst);
 
 	void icbi(UGeckoInstruction _inst);
 	void dcbst(UGeckoInstruction _inst);

Source/Core/Core/Src/PowerPC/JitArm32/JitArm_LoadStore.cpp

@@ -493,6 +493,34 @@ void JitArm::lmw(UGeckoInstruction inst)
 	gpr.Unlock(rA, rB);
 }
 
+void JitArm::stmw(UGeckoInstruction inst)
+{
+	INSTRUCTION_START
+	JITDISABLE(bJITLoadStoreOff)
+	if (!Core::g_CoreStartupParameter.bFastmem){
+		Default(inst); return;
+	}
+
+	u32 a = inst.RA;
+	ARMReg rA = gpr.GetReg();
+	ARMReg rB = gpr.GetReg();
+	ARMReg rC = gpr.GetReg();
+	MOVI2R(rA, inst.SIMM_16);
+	if (a)
+		ADD(rA, rA, gpr.R(a));
+	Operand2 mask(3, 1); // ~(Memory::MEMVIEW32_MASK)
+	BIC(rA, rA, mask); // 3
+	MOVI2R(rB, (u32)Memory::base, false); // 4-5
+	ADD(rA, rA, rB); // 6
+
+	for (int i = inst.RD; i < 32; i++)
+	{
+		ARMReg RX = gpr.R(i);
+		REV(rC, RX);
+		STR(rC, rA, (i - inst.RD) * 4);
+	}
+	gpr.Unlock(rA, rB, rC);
+}
 void JitArm::dcbst(UGeckoInstruction inst)
 {
 	INSTRUCTION_START

Source/Core/Core/Src/PowerPC/JitArm32/JitArm_Tables.cpp

@@ -95,7 +95,7 @@ static GekkoOPTemplate primarytable[] =
 	{39, &JitArm::stX}, //"stbu", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_S}},
 
 	{46, &JitArm::lmw}, //"lmw",   OPTYPE_SYSTEM, FL_EVIL, 10}},
-	{47, &JitArm::Default}, //"stmw",  OPTYPE_SYSTEM, FL_EVIL, 10}},
+	{47, &JitArm::stmw}, //"stmw",  OPTYPE_SYSTEM, FL_EVIL, 10}},
 
 	{48, &JitArm::lfs}, //"lfs",  OPTYPE_LOADFP, FL_IN_A}},
 	{49, &JitArm::lfsu}, //"lfsu", OPTYPE_LOADFP, FL_OUT_A | FL_IN_A}},