Jit64: Flatten avx_op

Reduces indentation and places the "ugly" case last. No behavior change.
This commit is contained in:
JosJuice 2022-10-08 22:42:07 +02:00
parent 017f72f43e
commit bb3306701b
1 changed files with 29 additions and 32 deletions

View File

@ -752,32 +752,7 @@ void EmuCodeBlock::avx_op(void (XEmitter::*avxOp)(X64Reg, X64Reg, const OpArg&),
{
(this->*avxOp)(regOp, arg1.GetSimpleReg(), arg2);
}
else if (arg2.IsSimpleReg(regOp))
{
if (reversible)
{
(this->*sseOp)(regOp, arg1);
}
else
{
// The ugly case: regOp == arg2 without AVX, or with arg1 == memory
if (!arg1.IsSimpleReg(XMM0))
MOVAPD(XMM0, arg1);
if (cpu_info.bAVX)
{
(this->*avxOp)(regOp, XMM0, arg2);
}
else
{
(this->*sseOp)(XMM0, arg2);
if (packed)
MOVAPD(regOp, R(XMM0));
else
MOVSD(regOp, R(XMM0));
}
}
}
else
else if (!arg2.IsSimpleReg(regOp))
{
if (packed)
MOVAPD(regOp, arg1);
@ -785,6 +760,28 @@ void EmuCodeBlock::avx_op(void (XEmitter::*avxOp)(X64Reg, X64Reg, const OpArg&),
MOVSD(regOp, arg1);
(this->*sseOp)(regOp, arg1 == arg2 ? R(regOp) : arg2);
}
else if (reversible)
{
(this->*sseOp)(regOp, arg1);
}
else
{
// The ugly case: regOp == arg2 without AVX, or with arg1 == memory
if (!arg1.IsSimpleReg(XMM0))
MOVAPD(XMM0, arg1);
if (cpu_info.bAVX)
{
(this->*avxOp)(regOp, XMM0, arg2);
}
else
{
(this->*sseOp)(XMM0, arg2);
if (packed)
MOVAPD(regOp, R(XMM0));
else
MOVSD(regOp, R(XMM0));
}
}
}
// Abstract between AVX and SSE: automatically handle 3-operand instructions
@ -800,7 +797,12 @@ void EmuCodeBlock::avx_op(void (XEmitter::*avxOp)(X64Reg, X64Reg, const OpArg&,
{
(this->*avxOp)(regOp, arg1.GetSimpleReg(), arg2, imm);
}
else if (arg2.IsSimpleReg(regOp))
else if (!arg2.IsSimpleReg(regOp))
{
MOVAPD(regOp, arg1);
(this->*sseOp)(regOp, arg1 == arg2 ? R(regOp) : arg2, imm);
}
else
{
// The ugly case: regOp == arg2 without AVX, or with arg1 == memory
if (!arg1.IsSimpleReg(XMM0))
@ -816,11 +818,6 @@ void EmuCodeBlock::avx_op(void (XEmitter::*avxOp)(X64Reg, X64Reg, const OpArg&,
MOVAPD(regOp, R(XMM0));
}
}
else
{
MOVAPD(regOp, arg1);
(this->*sseOp)(regOp, arg1 == arg2 ? R(regOp) : arg2, imm);
}
}
alignas(16) static const u64 psMantissaTruncate[2] = {0xFFFFFFFFF8000000ULL, 0xFFFFFFFFF8000000ULL};