diff --git a/Readme.txt b/Readme.txt index c8a8c768c3..4132765d75 100644 --- a/Readme.txt +++ b/Readme.txt @@ -9,7 +9,7 @@ Open Source Release under GPL 2 Project Leaders: F|RES, ector -Team members: zerofrog, vincent.hamm, falc4ever, Sonicadvance1, tmator, shuffle2, gigaherz, mthuurne, drkIIRaziel, masken, daco, XTra.KrazzY, nakeee, memberTwo.mb2, donkopunchstania, jpeterson, omegadox, lpfaint99, bushing, magumagu9, mizvekov, cooliscool, facugaich +Team members: zerofrog, vincent.hamm, falc4ever, Sonicadvance1, tmator, shuffle2, gigaherz, mthuurne, drkIIRaziel, masken, DacoTaco, XTra.KrazzY, nakeee, memberTwo.mb2, donkopunchstania, jpeterson, omegadox, lpfaint99, bushing, magumagu9, mizvekov, cooliscool, facugaich Please read the FAQ before use: http://code.google.com/p/dolphin-emu/wiki/Facts_And_Questions diff --git a/docs/ActionReplay/CodeTypesGuide.txt b/docs/ActionReplay/CodeTypesGuide.txt new file mode 100644 index 0000000000..9483cceac9 --- /dev/null +++ b/docs/ActionReplay/CodeTypesGuide.txt @@ -0,0 +1,304 @@ +omments: 1 + +A Compendium of Gamecube Action Replay Code Types + +Note: This is note a Complete code type list. + +The purpose of this document is to catalogue and explain the effects of different AR code types in a clear, concise, and easy to read format. Please note that this document is not intended to explain EVERY code type, only those of interest to the amateur hacker. + +It would not have been possible to write this document without Kenobi's "GCN AR CODES TYPES EXPLANATION", found at www.GSCentral.com, so a big thank-you goes to Kenobi and Parasyte for their contributions to the GCN hacking scene. + +Kenobi's documentation is recommended reading as it is very complete, precise, and exact in it's explanations. However, that is also it's main flaw, it's TOO complex and technical for the casual or newbie hacker to understand. If "Address = ((0x0wXXXXXXX) AND 0x01FFFFFF) OR 0x80000000)" makes any sense to you, then I implore you to read Kenobi's guide instead. The intended audience for this document is people who'd rather have things explained in plain English. + +It should be noted that every decrypted AR code has a basic two-part format that is universal to every code. The first half contains the code type and address to be written to. The second half contains the value to be written. + +The Gamecube has a memory range of 80000000 - 817FFFFF (cached), or C0000000 - C17FFFFF (uncached). However for the sake of simplicity, the AR uses an offset number in the range of 00000000 - 017FFFFF. The code type identifier is an 8-bit value that is applied to the first two digits of the offset. For example, if your offset is 00012345, and you wish to perform a 32-bit write (04), you simply add (04000000) + (00012345) = 04012345. + +In order to conserve space and simplicity, only the 8-bit code type identifier and particulars of the second half of the code will be explained below, as the method for procuring the first half has already been described above ;) + +Terms: + +8-bit - Byte - 0x12 +16-bit - Halfword - 0x1234 +32-bit - Word - 0x12345678 + +---Writes--- + +(00) - NNNNNNXX +8-bit write. X is the value, N is the number of times to repeat. + +(02) NNNNXXXX +16-bit write. X is the value, N is the number of times to repeat. + +(04) XXXXXXXX +32-bit write. X is the value. + +Examples: + +00006500 00000312 +Will write byte 0x12 to 80006500, 80006501, 80006502, 800067503. + +02006500 00011234 +Will write halfword 0x1234 to 80006500, 80006502. + +05006500 12345678 +Will write word 0x12345678 to 81006500. + + +---Addition--- + +(80) - 000000XX +8-bit Addition. Load the byte at the address, add X to it, and save resulting byte. + +(82) - 0000XXXX +16-bit Addition. Load the halfword at the address, add X to it, and save resulting halfword. + +(84) - XXXXXXXX +32-bit Addition. Load the word at the address, add X to it, and save resulting word. + +---Single Line Activators--- + +***Equal*** +(08) 000000XX +8-bit Equal activator. + +(0A) 0000XXXX +16-bit Equal activator. + +(0C) XXXXXXXX +32-bit Equal activator. + +X is the value the address must equal to activate the next line of code. + +***NOT Equal*** +(10) 000000XX +8-bit NOT Equal activator. + +(12) 0000XXXX +16-bit NOT Equal activator. + +(14) XXXXXXXX +32-bit NOT Equal activator. + +If the value stored at the address is not equal to X, activate the next line of code. + +***If Lower (signed)*** +(18) 000000XX +8-bit If Lower (signed) activator. + +(1A) 0000XXXX +16-bit If Lower (signed) activator. + +(1C) XXXXXXXX +32-bit If Lower (signed) activator. + +If the value stored at the address is lower than X, activate the next line of code. + +***If Higher (signed)*** +(20) 000000XX +8-bit If Higher (signed) activator. + +(22) 0000XXXX +16-bit If Higher (signed) activator. + +(24) XXXXXXXX +32-bit If Higher (signed) activator. + +If the value stored at the address is higher than X, activate the next line of code. + +***If Lower (unsigned)*** +(28) 000000XX +8-bit If Lower (unsigned) activator. + +(2A) 0000XXXX +16-bit If Lower (unsigned) activator. + +(2C) XXXXXXXX +32-bit If Lower (unsigned) activator. + +If the value stored at the address is lower than X, activate the next line of code. + +***If Higher (unsigned)*** +(30) 000000XX +8-bit If Higher (unsigned) activator. + +(32) 0000XXXX +16-bit If Higher (unsigned) activator. + +(34) XXXXXXXX +32-bit If Higher (unsigned) activator. + +If the value stored at the address is higher than X, activate the next line of code. + +---Double Line Activators--- + +***Equal*** +(48) 000000XX +8-bit activator. + +(4A) 0000XXXX +16-bit activator. + +(4C) XXXXXXXX +32-bit activator. + +X is the value the address must equal to activate the next two lines of code. + +***NOT Equal*** +(50) 000000XX +8-bit NOT Equal activator. + +(52) 0000XXXX +16-bit NOT Equal activator. + +(54) XXXXXXXX +32-bit NOT Equal activator. + +If the value stored at the address is not equal to X, activate the next two lines of code. + +***If Lower (signed)*** +(58) 000000XX +8-bit If Lower (signed) activator. + +(5A) 0000XXXX +16-bit If Lower (signed) activator. + +(5C) XXXXXXXX +32-bit If Lower (signed) activator. + +If the value stored at the address is lower than X, activate the next two lines of code. + +***If Higher (signed)*** +(60) 000000XX +8-bit If Higher (signed) activator. + +(62) 0000XXXX +16-bit If Higher (signed) activator. + +(64) XXXXXXXX +32-bit If Higher (signed) activator. + +If the value stored at the address is higher than X, activate the next two lines of code. + +***If Lower (unsigned)*** +(68) 000000XX +8-bit If Lower (unsigned) activator. + +(6A) 0000XXXX +16-bit If Lower (unsigned) activator. + +(6C) XXXXXXXX +32-bit If Lower (unsigned) activator. + +If the value stored at the address is lower than X, activate the next two lines of code. + +***If Higher (unsigned)*** +(70) 000000XX +8-bit If Higher (unsigned) activator. + +(72) 0000XXXX +16-bit If Higher (unsigned) activator. + +(74) XXXXXXXX +32-bit If Higher (unsigned) activator. + +If the value stored at the address is higher than X, activate the next two lines of code. + +---Multi-Line Activators--- + +Note that all multi-line codes must end with the line 00000000 40000000. + +***Equal*** +(88) 000000XX +8-bit activator. + +(8A) 0000XXXX +16-bit activator. + +(8C) XXXXXXXX +32-bit activator. + +X is the value the address must equal to activate the next lines of code. + +***NOT Equal*** +(90) 000000XX +8-bit NOT Equal activator. + +(92) 0000XXXX +16-bit NOT Equal activator. + +(94) XXXXXXXX +32-bit NOT Equal activator. + +If the value stored at the address is not equal to X, activate the next lines of code. + +***If Lower (signed)*** +(98) 000000XX +8-bit If Lower (signed) activator. + +(9A) 0000XXXX +16-bit If Lower (signed) activator. + +(9C) XXXXXXXX +32-bit If Lower (signed) activator. + +If the value stored at the address is lower than X, activate the next lines of code. + +***If Higher (signed)*** +(A0) 000000XX +8-bit If Higher (signed) activator. + +(A2) 0000XXXX +16-bit If Higher (signed) activator. + +(A4) XXXXXXXX +32-bit If Higher (signed) activator. + +If the value stored at the address is higher than X, activate the next lines of code. + +***If Lower (unsigned)*** +(A8) 000000XX +8-bit If Lower (unsigned) activator. + +(AA) 0000XXXX +16-bit If Lower (unsigned) activator. + +(AC) XXXXXXXX +32-bit If Lower (unsigned) activator. + +If the value stored at the address is lower than X, activate the next lines of code. + +***If Higher (unsigned)*** +(B0) 000000XX +8-bit If Higher (unsigned) activator. + +(B2) 0000XXXX +16-bit If Higher (unsigned) activator. + +(B4) XXXXXXXX +32-bit If Higher (unsigned) activator. + +If the value stored at the address is higher than X, activate the next lines of code. + +---Alignment--- + +Codes must be properly aligned depending on the type of code. +8-bit codes can be used on ANY address. +16-bit codes must have an address that is a multiple of 2: 0,2,4,6,8,A,C,E. +32-bit codes must have an address that is a multiple of 4:0,4,8,C. +If codes aren't aligned, they may not work, or may cause your AR to spaz out and kill your cat (R.I.P. Snowball). + +---Signed & Unsigned Numbers--- + +Unsigned means : +For 8-bits : 0x00 -> 0xFF = 0 to 255. +For 16-bits: 0x0000 -> 0xFFFF = 0 to 65535. +For 32-bits: 0x00000000 -> 0xFFFFFFFF = 0 to 4294967295. + +Signed means : +For 8-bits : 0x00 -> 0x7F = 0 to 127. +0x80 -> 0xFF = -127 to -1. +For 16-bits: 0x0000 -> 0x7FFF = 0 to 32767. +0x8000 -> 0xFFFF = -32768 to -1. +For 32-bits: 0x00000000 -> 0x7FFFFFFF = 0 to 2147483647. +0x80000000 -> 0xFFFFFFFF = -2147483648 to -1. \ No newline at end of file diff --git a/docs/ActionReplay/GCNCodeTypes.txt b/docs/ActionReplay/GCNCodeTypes.txt new file mode 100644 index 0000000000..1099a1ee5a --- /dev/null +++ b/docs/ActionReplay/GCNCodeTypes.txt @@ -0,0 +1,955 @@ + + -------------------------------- + GCN AR CODES TYPES EXPLANATION + -------------------------------- + + v1.1 by kenobi + +History : + +v1.1 : Removed the 'NCT' codes types. + Added 'Byte Copy', 'Pointer Mod' and 'AND/OR' codes type. + Added some notes about the (m) codes, the 'write to CCxxxxxx' code. + Fixed some typos. + +v1.0 : Initial release. + +Special thanks to Parasyte for his help/informations about some codes types. + +This document has been written for educational purpose. +It may help you create codes for the GCN AR, or they might be useless +junk... Your call ! +If you know the GBA's ARv3 codes types, you'll find the GCN AR codes types +quite similar... +Also note that the PS2's AR MAX codes types are very close to the GCN ones. + + +Warning : This document is meant for advanced codes creators, NOT FOR +NEWBIES OR WANNABES. Sorry. +*************** If you are an experienced, known (by me or gscentral +admins) code hacker, and you don't + understand this document, you may try to ask help using the +www.gscentral.com forums + (or PM me there). + + +Special Note 1 : All adresses MUST be compatible with the data size you want +the codes are using. +*************** That means : -ANY address can be used for BYTE +reading/writing. + + -Address MUST be a multiple of 2 for HALFWORD +reading/writing. + (Last hex number of the address must be either +:0,2,4,6,8,A,C,E) + + -Address MUST be a multiple of 4 for WORD +reading/writing. + (Last hex number of the address must be either +:0,4,8,C) + + If you don't follow this rule, the codes won't work (or the +AR might crash)...! + + +Special Note 2 : All codes are formatted like that : XXXXXXXX YYYYYYYY. + I called ADDRESS (in caps) the XXXXXXXX, and VALUE (in +caps) the YYYYYYYY. + + +Special Note 3 : GCN memory range is 0x80000000 - 0x817FFFFF cached, and +0xC0000000 - 0xC17FFFFF uncached. + (don't ask what it means, I don't get it either :P). + The codes will usualy write to the cached area. + + +Special Note 4 : The codes type numbers I give after a code name is a number +created like this: + For "Type zX" codes , the number X is : + AAA (3 most significant bits of the code's "VALUE") + + For normal codes, the number in parenthesis after the name +of the code is : + AAABBCC (7 most significant bits of the code's +"ADDRESS") + AAA : type bits. + BB : subtype bits. + CC : value bits. + + You can use them as reference, or just ignore them... + + +Special Note 5 : Any "unused" data could be filled with random numbers to +create a "unique encryption", + which could "sign" your codes. I randomly explained how it +works. It might not work + with every code. This feature isn't really interessing, but +I felt like it should be + noticed. + +Special Note 6 : "Register 1BB4" is one of the register (= a given place in +the NGC memory) that the AR + uses to store some data while executing codes. + + +Special Note 7 : The addresses, values, and all the numbers starting by +"0x", or having the letter(s) + A, B, C, D, E and/or F in them are Hexadecimal numbers. If +you don't know what hexadecimal + is, make a search in Google. + + +Special Note 8 : If you don't know C/C++, be aware that "<<" means "Shift +left", and ">>" "Shift right". + "Shift left" is the "Lsh" button of the Windows calculator +(in "Scientific" mode). + "Shift right" is gotten by clicking the "Inv" checkbox, +then the "Lsh" button of the + Windows calculator (in "Scientific" mode). + + + + + ________________ + ---------------- + | Type z Codes | + ---------------- + + + +"Type z" are codes which have an ADDRESS eqal to 00000000 ("z" stands for +"zero"). + +For any "Type zX" codes : X = code type = (VALUE >> 29) AND 0x07. + (If X>4, the code will be skipped) + + +------------------------------- +// Type "z0" : END OF CODES // +------------------------------- + +1 line code. + +00000000 00000000 + +It means "end of the code" (or "no more codes are executed"). + +The AR will "give" back the hand to the game, and then will start execute +codes +from the very 1st of the list. + + + +-------------------------------------------- +// Type "z2" : Normal execution of codes // +-------------------------------------------- + +1 line code. + +00000000 40000000 + +Set register 1BB4 to 0. +It means that the AR goes back to the normal execution of codes. +(And it should break a "stop executing codes", set when register 1BB4 is = +2). + + +----------------------------------------------------- +// Type "z3" : Executes all codes in the same row // +----------------------------------------------------- + +1 line code. + +00000000 60000000 + +Set register 1BB4 to 1. +It means the AR will execute all the codes, without giving back the hand to +the +game, unless register 1BB4 changes value (with a "z2" code for exemple). + + +------------------------------- +// Type "z4" : Fill & Slide // +------------------------------- + +2 lines code. + +00000000 8XXXXXXX +Y1Y2Y3Y4 Z1Z2Z3Z4 + + +Address = 8XXXXXXX AND 0x81FFFFFF. + +Size = (address >> 25) AND 0x03. +(Size 0 = 8bits, Size 1 = 16 bits, Size 2 = 32 bits. Size 3 = Unused) + +Value = Y1Y2Y3Y4. + +Address increment = 0000Z3Z4 if (Z1 >> 3 = 0). + = FFFFZ3Z4 if (Z1 >> 3 = 1). + +NOTE : When using halfword (or word), make address increment >> 1 (or >> 2) +when + computing the code. + +Value increment = 00000000Z1 if (Z1 >> 3 = 0). + = FFFFFFFFZ1 if (Z1 >> 3 = 1). + +Number of values to write = Z2. + +NOTE : If Z2 = 0, nothing will be written (it'll be like the code isn't +executed). + + +Small note : +------------ +As the sign of the address increment and the value increment are shared, you +MUST start +from the 1st address when using a positive value increment, and start from +the last address +when using a negative value increment. + + +------------------------------------------ +// Type "z4 - Size 3" : Memory Copy // +------------------------------------------ + +These codes were 'created' by me (kenobi). +The only way to use them is to enter and enable the 'Enablers' codes. +You also HAVE TO add the Master Code flag to these Enabler codes' +indentifier +(or to include it into the (m) code), else they won't work properly. +Finally, the 'Enabler' codes and the actual codes must be entered +separately. +They should work on ANY AR (at least up to version 1.14b). + + +A - Memory Copy Without Pointer Support : +----------------------------------------- + +Enabler (must be on!) : +04001E48 48000769 +040025B0 5525043E +040025B4 4BFFF644 + + +Exemple of byte copy : +00000000 86393FA8 +80393FA0 00000001 + + +Here is how it works : +00000000 8XXXXXXX +YYYYYYYY 0000ZZZZ + +8XXXXXXX = [Destination address] OR 0x06000000. +YYYYYYYY = [Source address]. +ZZZZ = number of bytes to copy (0x0000 will copy 0 byte, 0xFFFF will copy +65535 bytes). + +Important : the 16-bits number before ZZZZ MUST BE '0000', else it'll create +errors !!! + +So, if you follow what I explained, you can see that my code exemple will +copy 2 bytes, +from 80393FA0 to 80393FA8. + + + + +B - Memory Copy With Pointers Support : +--------------------------------------- + +Enabler (must be on!) : +04001E48 48000769 +040025B0 5525043E +040025B4 2C060000 +040025B8 4182000C +040025BC 80630000 +040025C0 80840000 +040025C4 4BFFF634 + + +With this code, if you put any data in the 8 upper bits of the value, the AR +will use +the addresses in the code as pointers addresses + +Exemple : + +00000000 86002F04 +80002F00 01000138 + +Important : the 8-bits number before ZZZZ MUST BE '00', else it'll create +errors !!! + +As the value start with '01' (could have been anything, but '00'), the AR +will load +the 32bits value at 80002F00 and use it as the source address, then load the +32bits +value at 80002F04 and use it as the destination address, and finally will +copy 138 bytes +from the source address to the destination address. + +Note that if you put '00' in the start of the value, the code will work just +like +the 'Memory Copy Without Pointer Support' code. + +If you need to add an offset to the pointer addresses, you'll have to do +this trick : +copy the source pointer address to 80002F00, the destination pointer address +to 80002F04, +add the offset values to theses pointer addresses (using the 'Add' code +type), and finally +use the 'Memory Copy with Pointers Support' to copy the bytes. + + +Exemple : +00000000 86002F00 <- Copy the 32bits (=4 bytes) source pointer address +804C8268 00000004 from 804C8268 to 80002F00. + +00000000 86002F04 <- Copy the 32bits (=4 bytes) destination pointer address +804C8268 00000004 from 804C8268 to 80002F04. + +84002F00 00000098 <- Add the offset 0x98 to the source pointer address at +80002F00. + +84002F04 000001D0 <- Add the offset 0x1D0 to the source pointer address at +80002F04. + +4A44F0A8 00000030 <- (if the user press R+Z...). + +00000000 86002F04 <- Copy 0x138 bytes from the address stored at 80002F00 +(=pointer address+0x98) +80002F00 01000138 to the address stored at 80002F04 (=pointer address + +0x1D0). + + + + + + + + + + ________________ + ---------------- + | Normal Codes | + ---------------- + + + +For any "Normal Codes", you have : + +SubType = (ADDRESS >> 30) AND 0x03. + +Type = (ADDRESS >> 27) AND 0x07. + +Size = (ADDRESS >> 25) AND 0x03. + +(usually, Size 0 = 8bits, Size 1 = 16 bits, Size 2 = 32 bits. +For some codes, Size 3 = Floating point single precision) + + + + +------------ +// Type 0 // +------------ + +-------------------------------------- +// SubType 0 : Ram write (and fill) // (can be called "00", "01" and "02") +-------------------------------------- + +1 line code. + +0.0.x +----- + +0wXXXXXX Y1Y2Y3Y4 + +(w < 8!) + +Address = ((0x0wXXXXXXX) AND 0x01FFFFFF) OR 0x80000000). + +Size = (address >> 25) AND 0x03. + +If Size = 0 [00] : + fills area [Address ; Address + Y1Y2Y3] with value Y4. + +If Size = 1 [02] : + fills area [Address ; Address + (Y1Y2 << 1)] with value Y3Y4. + +If Size = 2 [04] : + writes word Y1Y2Y3Y4 to Address. + + +Examples : + +00023000 00000312 +will write byte 0x12 to 80023000, 80023001, 80023002, 80023003. + +02023000 00011234 +will write halfword 0x1234 to 80023000, 80023002. + +05023000 12345678 +will write halfword 0x12345678 to 81023000. + + + +------------------------------- +// SubType 1 : Write to pointer (can be called "04", "05" and "06") +------------------------------- + +1 line code. + +0.1.x +----- + +1 line code. + +4wXXXXXX Y1Y2Y3Y4 + +(w < 8!) + +Address = ((0x4wXXXXXX) AND 0x01FFFFFF) OR 0x80000000. + +Size = (Address >> 25) AND 0x03. + +Pointer Address = [Word stored at Address]. + +This code will make the AR load the word stored at the address provided in +the code, +(also called the "Pointer Address"), and check if it's a valid address (ie. +if it's in +the [80000000~81800000[ range). It it is one, it will add an offset to it, +and it will +write the data provided in the code to this new address. + + +If Size = 0 [40] : +AR will write the byte Y4 at [Pointer Address + Y1Y2Y3]. + +If Size = 1 [42] : +AR will write the halfword Y3Y4 at [Pointer Address + (Y1Y2 << 1)]. + +If Size = 2 [44] : +AR will write the word Y1Y2Y3Y4 at [Pointer Address]. + + + +REMOVE THE 'VALID ADDRESS' CHECK, AKA 'POINTER MOD' : +----------------------------------------------------- + +This code was 'created' by me (kenobi). +The only way to use it is to enter and enable the 'Enabler' code. +You also HAVE TO add the Master Code flag to these Enabler codes' +indentifier +(or to include it into the (m) code), else they won't work properly. +Finally, the 'Enabler' codes and the actual codes must be entered +separately. +It should work on ANY AR (at least up to version 1.14b). + + +Enabler (must be on) : +04001FA4 48000014 + +Once you use this code, the 'Write to Pointer' code will stop checking if +the address you +point to is a valid address. +That means that you can write to virtual memory without a TLB (m) code, but +you have to make +sure that the address the pointer code reads is a valid address (else, it'll +crash). + +Exemple (courtesy of donny2112) : +04002F0C 7FC39C9C +42002F0C 00010000 +42002F0C 03ED0000 +42002F0C 04F70000 +42002F0C 05BB0000 + +The first line will write '7FC39C9C' to 80002F0C. +Then, the other lines will write 0x0000 to 0x7FC39C9C+2*1, +0x7FC39C9C+2*0x3ED, 0x7FC39C9C+2*0x4F7, +and finally 0x7FC39C9C+2*0x5BB. + +The advantage of this code, over a TLB (m) code, is that it only needs a 1 +lines enabler, it is +compatible with all games and all ARs, and it allows you to use 8/16/32bits +ram write. + +The downside is that if you point to an invalid address, the GC will just +crash. +If you're not sure that you'll point to a valid address, you can use this +combinaison of code to check +it manually (in this exemple, I make sure that the address is in the +0x80000000~817F0000 range) : + +74XXXXXX 80000000 <- If value > 0x80000000 +2CXXXXXX 81800000 <- and If value < 0x81800000 +44XXXXXX Y1Y2Y3Y4 <- then execute this pointer code. + +XXXXXXXX being the address where the Pointer Address is stored. + + + + +----------------------- +// SubType 2 : Add code (can be called "08", "09" and "0A") +----------------------- + +1 line code. + +0.2.x +----- + +1 line code. + +8wXXXXXX Y1Y2Y3Y4 + +(w < 8!) + +Address = (0x8wXXXXXX AND 0x81FFFFFF). + +Size = (Address >> 25) AND 0x03. + +if Size = 0 [80] : + Loads byte stored at [Address], adds Y1Y2Y3Y4 to it, and stores the +resulting byte + (= result AND 0xFF) at [Address]. + +if Size = 1 [82] : + Loads halfword stored at [Address], adds Y1Y2Y3Y4 to it, and stores the +resulting halfword + (= result AND 0xFFFF) at [Address]. + +if Size = 2 [84] : + Loads word stored at [Address], adds Y1Y2Y3Y4 to it, and stores the result +at [Address]. + +if Size = 3 [86] : + Loads floating value stored at [Address], adds Y1Y2Y3Y4 (must be a +floating point single precision value) + to it, and stores the result at [Address]. + + +Change ADD to AND : +------------------ +This code was 'created' by me (kenobi). +The only way to use it is to enter and enable the 'Enabler' code. +You also HAVE TO add the Master Code flag to these Enabler codes' +indentifier +(or to include it into the (m) code), else they won't work properly. +Finally, the 'Enabler' codes and the actual codes must be entered +separately. +This change is definitive (until you reboot the Game) : + +Enable 8-bits AND : +0400200C 7C002038 + + +Enable 16-bits AND : +0400201C 7C002038 + + +Enable 32-bits AND : +0400202C 7C002038 + +Enable 8~32bits AND : +00000000 8400200C +7C002038 00030004 + + +Change ADD to OR : +------------------ +This code was 'created' by me (kenobi). +The only way to use it is to enter and enable the 'Enabler' code. +You also HAVE TO add the Master Code flag to these Enabler codes' +indentifier +(or to include it into the (m) code), else they won't work properly. +Finally, the 'Enabler' codes and the actual codes must be entered +separately. +This change is definitive (until you reboot the Game) : + +Enable 8-bits OR : +0400200C 7C002378 + +Enable 16-bits OR : +0400201C 7C002378 + +Enable 32-bits OR : +0400202C 7C002378 + +Enable 8~32bits OR : +00000000 8400200C +7C002378 00030004 + +Note : you can't mix 'ADD', 'AND' and 'OR' codes for the same code type +(8/16/32bits). + + + +---------------------------------------------- +// SubType 3 : Master Code & Write to CCXXXXXX (can be called "0E" and "0F") +---------------------------------------------- + +1 line code. + +0.3.x +----- + +1 line code. + +CwXXXXXX Y1Y2Y3Y4 + +(w < 8!) + +Address = ((0x6wXXXXXX) AND 0x01FFFFFF) OR 0x80000000). + +Size = (Address >> 25) AND 0x03. + + + + +If Size = 2 (0.3.2) : Master Code (C4XXXXXX Y1Y2Y3Y4) +----------------------------------------------------- + +Y4 = Master Code Number. + 0x00 : executed only once, just before the game bootup. + Only one (m) code can have the '00' number (the others will be +skipped), + and it must be the very one in the (m) code list (else it'll be +skipped). + + 0x01~0x0F : executed continuously during the game execution. + (2 (or more) master codes that have the same Master Code +Number can't + be executed correctly if they are put one just after +another. + Only the first one will be executed, the other(s) will be +skipped). + +Y3 = number of codes to execute each time the AR "has the hand". + +Y2 AND 0x03 = Master Code Type : + +Type 0 : create a branch to SUBROUTINE 1. + (Save : R0 R3 R28 R29 R30 R31) + +Type 1 : backup 4 asm lines from the game, and write a Branch to MAIN +ROUTINE. + (Save : R3 R28 R29 R30 R31, Destroys : R0?) + +Type 2 : create a branch to 1 copy of SUBROUTINE 1. + (Save : R0 R3 R28 R29 R30 R31) + +Type 3 : create a branch to MAIN ROUTINE START (will execute the 4 asm lines +backed up + in Type 1, if any). + (Save : R0 R3 R28 R29 R30 R31) + + +Note : Putting random numbers in Y1 should change the encryption, thus +"signing" your + code (untested). + +Note : Don't use the Type 1 alone with a Master Code Number >0, else the AR +will backup its own + hook, and enter an infinite loop. So put a conditional code type make +that this code isn't + executed more than once. + + + +If (Size = 3) AND ((address AND 0x01FFFFFF ) < 0x01000000) (0.3.3): +------------------------------------------------------------------- + + Write halfword to CCXXXXXX (C6XXXXXX Y1Y2Y3Y4) + ---------------------------------------------- + +Address = 0xCCXXXXXX +Stores the halfword Y3Y4 at Address. + +Note : Putting random numbers in Y1Y2 should change the encryption, thus +"signing" your + code (untested). + + +If (Size = 3) AND ((address AND 0x01FFFFFF ) >= 0x01000000) (0.3.3): +-------------------------------------------------------------------- + + Write word to CDXXXXXX (C7XXXXXX Y1Y2Y3Y4) + ------------------------------------------ + +Address = 0xCDXXXXXX +Stores the word Y1Y2Y3Y4 at Address. + +Note : Parasyte informed me that writing to 0xCDXXXXXX doesn't makes any +sense, and he thinks + it might be some kind of AR bug... + + + + + + + ************************************************** + * NOTES FOR ALL CONDITIONAL CODES (TYPE 1 TO 7). * + ************************************************** + +All the Conditional Codes are 1 line code, but you "need" to add another +line to make them work. +Conditional Code are used to trigger the next code(s) when an event happens, +for exemple give the +player 99 lifes when buttons L+R are pushed, or make the life becomes full +when it reaches 50% +of its value... + + +They all come in 3 "flavors" : 8, 16 and 32 bits. You select it by changing +the size data in the code. +Reminder : Size = (Address >> 25) AND 0x03 + +For all the Conditional Codes, you first take the value of the IN GAME data, +and compare it to +the value provided in the CODE data. The result, which should be read as +'True' (or 'False'), will +tell if the Conditional Code will activate the next codes. + +Anyway, Conditional Codes should be used by advanced code makers. +And don't ask for the "paddle" values, they seem to change for every game... +So find them yourself :-) + +The number I give as exemples has been made using BYTE size : + +08XXXXXX YYYYYY is the "If equal execute next code" generic value for a BYTE +comparison. +For halfwords, it'll be 0AXXXXXX YYYYYYYY, and for words 0CXXXXXX +YYYYYYYY... + + + +-------------------------- +// Type 1 : If equal... // (can be called "10", "11" and "12") +-------------------------- + +1.y.x +----- + +08XXXXXX YYYYYYYY + +(w >= 8!) + +Subtype 0 [08] : If equal, execute next line (else skip next line). +Subtype 1 [48] : If equal, execute next 2 lines (else skip next 2 lines). +Sybtype 2 [88] : If equal, execute all the codes below this one in the same +row (else execute + none of the codes below). +Subtype 3 [C8] : While NOT EQUAL,turn off all codes (infinite loop on the +code). + + + + + + +------------------------------ +// Type 2 : If NOT equal... // (can be called "20", "21" and "22") +------------------------------ + +2.y.x +----- + +10XXXXXX YYYYYYYY + + +Subtype 0 [10] : If NOT equal, execute next line (else skip next line). +Subtype 1 [50] : If NOT equal, execute next 2 lines (else skip next 2 +lines). +Sybtype 2 [90] : If NOT equal, execute all the codes below this one in the +same row (else execute + none of the codes below). +Subtype 3 [D0] : While EQUAL, turn off all codes (infinite loop on the +code). + + + + +------------------------------------ +// Type 3 : If lower... (signed) // (can be called "30", "31" and "32") +------------------------------------ + +Signed means : +For Bytes : values go from -128 to +127. +For Halfword : values go from -32768/+32767. +For Words : values go from -2147483648 to 2147483647. +For exemple, for the Byte comparison, 7F (127) will be > to FFFFFFFF (-1). +You HAVE to enter a 32bits signed number as value, even if you just want to +make an halfword +comparison. That's because 0000FFFF = 65535, and FFFFFFFF = -1). +You could choose any value (for exemple, +65536 for halfword code, but the +result will be always True +(or always False if you choose -65537...). + +3.y.x +----- + +18XXXXXX YYYYYYYY + +* WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * +WARNING * WARNING * + +If you used a "byte" size, this Type 3 code will actually be a "If lower... +(UNSIGNED)" ! +That means, no signed comparison for byte values !!! (AR bug?) + +* WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * +WARNING * WARNING * + +Subtype 0 [18] : If lower, execute next line (else skip next line). +Subtype 1 [58] : If lower, execute next 2 lines (else skip next 2 lines). +Sybtype 2 [98] : If lower, execute all the codes below this one in the same +row (else execute + none of the codes below). +Subtype 3 [D8] : While higher, turn off all codes (infinite loop on the +code). + + + +Note 1 : For 8 and 16 bits codes, you *could* fill the unused numbers in the +Value to change + the encrypted code, and "sign" them (unverified). + + + +------------------------------------ +// Type 4 : If higher... (signed) // (can be called "40", "41" and "42") +------------------------------------ + +Signed means : +For Bytes : values go from -128 to +127. +For Halfword : values go from -32768/+32767. +For Words : values go from -2147483648 to 2147483647. +For exemple, for the Byte comparison, 7F (127) will be > to FFFFFFFF (-1). +You HAVE to enter a 32bits signed number as value, even if you just want to +make an halfword +comparison. That's because 0000FFFF = 65535, and FFFFFFFF = -1). +You could choose any value (for exemple, +65536 for halfword code, but the +result will be always True +(or always False if you choose -65537...). + + +4.y.x +----- + +20XXXXXX YYYYYYYY + + +* WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * +WARNING * WARNING * + +If you used a "byte" size, this Type 4 code will actually be a "If lower... +(UNSIGNED)" ! +That means, no signed comparison for byte values !!! (AR bug?) + +* WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * +WARNING * WARNING * + +Subtype 0 [20] : If higher, execute next line (else skip next line). +Subtype 1 [60] : If higher, execute next 2 lines (else skip next 2 lines). +Sybtype 2 [A0] : If higher, execute all the codes below this one in the same +row (else execute + none of the codes below). +Subtype 3 [E0] : While lower, turn off all codes (infinite loop on the +code). + + +Note 1 : For 8 and 16 bits codes, you *could* fill the unused numbers in the +Value to change + the encrypted code, and "sign" them (unverified). + + + +------------------------------------- +// Type 5 : If lower... (unsigned) // (can be called "50", "51" and "52") +------------------------------------- + +Unsigned means : +For Bytes : values go from 0 to +255. +For Halfword : values go from 0 to +65535. +For Words : values go from 0 to 4294967295. +For exemple, for the Byte comparison, 7F (127) will be < to FF (255). + +5.y.x +----- + +28XXXXXX YYYYYYYY + + +Subtype 0 [28] : If lower, execute next line (else skip next line). +Subtype 1 [68] : If lower, execute next 2 lines (else skip next 2 lines). +Sybtype 2 [A8] : If lower, execute all the codes below this one in the same +row (else execute + none of the codes below). +Subtype 3 [E8] : While higher, turn off all codes (infinite loop on the +code). + + + +-------------------------------------- +// Type 6 : If higher... (unsigned) // (can be called "60", "61" and "62") +-------------------------------------- + +Unsigned means : +For Bytes : values go from 0 to +255. +For Halfword : values go from 0 to +65535. +For Words : values go from 0 to 4294967295. +For exemple, for the Byte comparison, 7F (127) will be < to FF (255). + + +6.y.x +----- + +30XXXXXX YYYYYYYY + + +Subtype 0 [30] : If higher, execute next line (else skip next line). +Subtype 1 [70] : If higher, execute next 2 lines (else skip next 2 lines). +Sybtype 2 [B0] : If higher, execute all the codes below this one in the same +row (else execute + none of the codes below). +Subtype 3 [F0] : While lower, turn off all codes (infinite loop on the +code). + + + + + +------------------------ +// Type 7 : If AND... // (can be called "70", "71" and "72") +------------------------ + +(if the result of ANDing the IN GAME and IN CODE values is <>0) + +7.y.x +----- + +38XXXXXX YYYYYYYY + + +Subtype 0 [38] : If AND, execute next line (else skip next line). +Subtype 1 [78] : If AND, execute next 2 lines (else skip next 2 lines). +Sybtype 2 [B8] : If AND, execute all the codes below this one in the same +row (else execute + none of the codes below). +Subtype 3 [F8] : While NOT AND, turn off all codes (infinite loop on the +code). + + + + + + + + * THE END * + diff --git a/docs/DSP/AX.c b/docs/DSP/AX.c new file mode 100644 index 0000000000..87a30e46aa --- /dev/null +++ b/docs/DSP/AX.c @@ -0,0 +1,213 @@ +// +// Pseudo C +// + +// +// DSP: +// + +// Memory USAGE + + + +0x0B80 to 0x0C40 CurrentPB + +0x0B87 + +0x0E15 SrcSelectFunction // perhaps CMD0 setups some kind of jmp table at this addresses +0x0E16 CoefFunction +0x0E14 MixCtrlFunction + +0x0e17 TmpBuffer exceptions +0x0e18 TmpBuffer exceptions +0x0e19 TmpBuffer exceptions + +// instrcution memory +0x0B31 to 0x0B33 some kind of JMP-Table to handle srcSelect ??? +0x0B34 to 0x0B36 some kind of JMP-Table to handle coefSelect ??? +0x0B11 to 0x0B1F some kind of JMP-Table to handle mixerCtrl ??? + +void CMD2() +{ +// 0x1BC + int_addrPB = (*r00 << 16) | *(r00+1) + DMA_From_Memory(0x0B80, _addrPB, 0xC0); // read first PB to 0x0B80 + +// 0x1C7 + *0x0E08 = 0x0000 + *0x0E09 = 0x0140 + *0x0E0A = 0x0280 + *0x0E0B = 0x0400 + *0x0E0C = 0x0540 + *0x0E0D = 0x0680 + *0x0E0E = 0x07C0 + *0x0E0F = 0x0900 + *0x0E10 = 0x0A40 + +// 0x1E4 + WaitForDMATransfer() + +// 0x1E6 + Addr = (*0x0BA7 << 16) | *0x0BA8 + DMA_From_Memory(0x03C0, Addr, 0x80); // Copy Update Data to 0x03C0 (AXPBUPDATE dataHi, dataLo) + +// 0x1F4 + R03 = (*0x0B84) + 0x0B31 // AXPB->srcSelect + 0x0B31 ??? some kind of flag handling ??? SRCSEL can be 0x0 to 0x2 + AC0.M = *R03 + *0x0E15 = *AC0.M + +// 0x1FD + R03 = (*0x0B85) + 0x0B34 // AXPB->coefSelect + 0x0B34 ??? some kind of flag handling ??? COEF can be 0x0 to 0x2 + AC0.M = *R03 + *0x0E16 = *AC0.M + +// 0x206 + R03 = (*0x0B86) + 0x0B11 // AXPB->mixerCtrl + 0x0B36 ??? some kind of flag handling ??? MIXCTRL can be 0x0 to 0xE + AC0.M = *R03 + *0x0E14 = *AC0.M + +// 0x20F + if (*0x0B9B == 0) // AXPBITD->flag (on or off for this voice) + { + // jmp to 0x23a + *0x0E42 = 0x0CE0 + *0x0E40 = 0x0CE0 + *0x0E41 = 0x0CE0 + *0x0E43 = 0x0CE0 + + WaitForDMATransfer() + } + else + { + // code at 0x216 + *0x0E40 = *0x0B9E + 0x0CC0 // AXPBITD->shiftL + *0x0E41 = *0x0B9F + 0x0CC0 // AXPBITD->shiftR + *0x0E42 = 0xCE0 + *0x0E43 = 0xCE0 + + WaitForDMATransfer() + + // 0x22a + Addr = (*0x0B9C << 16) | *0x0B9D + DMA_From_Memory(0x0CC0, Addr, 0x40); // (AXPBITD->bufferHi << 16 | AXPBITD->bufferLo) -> 0xCC0 + WaitForDMATransfer() + } + +} + +void CMD0() +{ + +} + + +void CMD3() +{ + + 0x0E07 = R00 + R00 = 0x0BA2 // AXPBUPDATE->updNum + R01 = 0x03C0 + *0x0E04 = 0x05 + + AC1 = 0 + AC0 = 0 + AX0.H = *R00++ // AXPBUPDATE->updNum[0] + AC1.M = 0x0B80 + +// 0x256 + for (i=0; istate + + if (AC0.M == 1) + { + // JMP 0x267 (AX_PB_STATE_RUN) + *0x0E1C = *0x0E42 + + CALLR *0x0E15 // Load Sample (SrcSelectFunction) + + // 0x270 + AC0.M = *0xBB3 // AXPBVE->currentDelta (.15 volume at start of frame) + AC1.M = *0xBB2 // AXPBVE->currentVolume + + // 0x278 + AX0.L = AC1.M + AC1.M = AC1.M + AC0.M + AC0.M = AC0.M << 1 + + SET15 // ???? + + AX1.H = AC0.M + AC0.M = AX0.L + + AX0.L = 0x8000 + R00 = 0x0E44 + +// 0x27f + // scale volume table + . + . + . +/* for (int i=0; i<32; i++) + { + *R00++ = AC0.M; + prod = AX0.L * AX1.H + + *R00++ = AC1.M; + AC0 = AC0 + prod + prod = AX0.L * AX1.H + + *R00++ = AC0.M; + AC1 = AC1 + prod + prod = AX0.L * AX1.H + }*/ + +// 0x29f + *0xBB2 = CurrentVolume + + +// 0x2a1 + // mutiply volume with sample + . + . + . + + +// 0x2ea + // Call mixer + +// 0x02f0 + + + + } + else + { + // JMP 0x332 + . + . + . + . + } + +} + +// =============================================================== +void Func_0x065D() +{ + + +} \ No newline at end of file diff --git a/docs/DSP/Crazy Taxi.txt b/docs/DSP/Crazy Taxi.txt new file mode 100644 index 0000000000..2db9cb7284 --- /dev/null +++ b/docs/DSP/Crazy Taxi.txt @@ -0,0 +1,2703 @@ +// documented UCode of Crazy Taxi +// +// + +//////////////////////////////////////////////////////////// +// MemMap +// + + +0x0000 // RightBuffer +0x0140 // LeftBuffer +0x0280 +0x0400 // Opcode_14() interleaves the buffer to this address +0x0540 +0x0680 +0x07C0 +0x0900 +0x0A40 +0x0B80 to 0x0C40 // CurrentPB + + +// addresses to buffers +0x0E08 // BufferLeft +0x0E09 // BufferRight +0x0E0A // +0x0E0B +0x0E0C +0x0E0D +0x0E0E +0x0E0F +0x0E10 + + +// callbacks +0x0E15 SrcSelectFunction // perhaps CMD0 setups some kind of jmp table at this addresses +0x0E16 CoefFunction +0x0E14 MixCtrlFunction + +0x0e17 TmpBuffer exceptions +0x0e18 TmpBuffer exceptions +0x0e19 TmpBuffer exceptions + + +0x0e1c TmpBuffer for Opcode3() + + +0x0e40 pb->PBInitialTimeDelay->offsetLeft +0x0e41 pb->PBInitialTimeDelay->offsetRight + +0x0e42 // initialized to 0x0ce0 all the time; something for the Decoder Functions + + + +//////////////////////////////////////////////////////////// +// Code +// + + + +0000 0000 NOP +0001 0000 NOP +0002 029f 0c10 JMP 0x0c10 +0004 029f 0c1f JMP 0x0c1f +0006 029f 0c3b JMP 0x0c3b +0008 029f 0c4a JMP 0x0c4a +000a 029f 0c50 JMP 0x0c50 +000c 029f 0c82 JMP 0x0c82 +000e 029f 0c88 JMP 0x0c88 + + +Init-Code() + +0010 1302 SBSET #0x02 +0011 1303 SBSET #0x03 +0012 1204 SBCLR #0x04 +0013 1305 SBSET #0x05 +0014 1306 SBSET #0x06 +0015 8e00 S40 +0016 8c00 CLR15 +0017 8b00 M0 +0018 0092 00ff LRI $18, #0x00ff +001a 8100 CLR $30 +001b 8900 CLR $31 +001c 009e 0e80 LRI $30, #0x0e80 +001e 00fe 0e1b SR @0x0e1b, $30 +0020 8100 CLR $30 +0021 00fe 0e31 SR @0x0e31, $30 +0023 16fc dcd1 SI @DMBH, #0xdcd1 +0025 16fd 0000 SI @DMBL, #0x0000 +0027 16fb 0001 SI @DIRQ, #0x0001 // write mail: DSP_TASK_STATE_RUN(0xDCD10000) and calls initCB of the task + +// wait for mail +0029 26fc LRS $30, @DMBH +002a 02a0 8000 ANDCF $30, #0x8000 +002c 029c 0029 JZR 0x0029 + +002e 029f 0045 JMP 0x0045 + + + +0030 1302 SBSET #0x02 +0031 1303 SBSET #0x03 +0032 1204 SBCLR #0x04 +0033 1305 SBSET #0x05 +0034 1306 SBSET #0x06 +0035 8e00 S40 +0036 8c00 CLR15 +0037 8b00 M0 +0038 0092 00ff LRI $18, #0x00ff +003a 16fc dcd1 SI @DMBH, #0xdcd1 +003c 16fd 0001 SI @DMBL, #0x0001 +003e 16fb 0001 SI @DIRQ, #0x0001 // write mail: DSP_TASK_STATE_RUN(0xDCD10001) and calls resCB of the task + + +0040 26fc LRS $30, @DMBH +0041 02a0 8000 ANDCF $30, #0x8000 +0043 029c 0040 JZR 0x0040 + +------------------------------------------------------------ +Main() + +0045 8e00 S40 +0046 8100 CLR $30 +0047 8900 CLR $31 +0048 009f babe LRI $31, #0xbabe + + +// wait for dma timewasting :D +004a 26fe LRS $30, @CMBH +004b 02c0 8000 ANDF $30, #0x8000 +004d 029c 004a JZR 0x004a + + + +004f 8200 CMP +0050 0294 004a JNE 0x004a +0052 23ff LRS $27, @CMBL +0053 8100 CLR $30 +0054 26fe LRS $30, @CMBH +0055 02c0 8000 ANDF $30, #0x8000 +0057 029c 0054 JZR 0x0054 +0059 27ff LRS $31, @CMBL +005a 0240 7fff ANDI $32, #0x7fff +005c 2ece SRS @DSMAH, $30 +005d 2fcf SRS @DSMAL, $31 +005e 16cd 0c00 SI @DSPA, #0x0c00 +0060 8100 CLR $30 +0061 2ec9 SRS @DSCR, $30 +0062 1ffb MRR $31, $27 +0063 2fcb SRS @DSBL, $31 +0064 02bf 055c CALL 0x055c // Wait for DMA control reg +0066 0080 0c00 LRI $0, #0x0c00 + + +0068 8e00 S40 +0069 8100 CLR $30 +006a 8970 CLR.L $31 : $30, @$0 +006b b100 TST $30 +006c 0291 007e JX1 0x007e + + +// check if the code it out of Opcode is > 0x12 if so send a 0xBAAD and HALT +006e 0a12 LRIS $26, #0x12 +006f c100 CMPAXH $30, $26 +0070 0292 007e JX2 0x007e + +0072 009f 0aff LRI $31, #0x0aff // load jump table base address +0074 4c00 ADD $30, $31 +0075 1c7e MRR $3, $30 +0076 0213 ILRR $30, @$3 +0077 1c7e MRR $3, $30 +0078 176f JMPR $3 // jump to the opcode + + +// HALT - but this one seems to be unreachable +0079 16fc fbad SI @DMBH, #0xfbad +007b 16fd 8080 SI @DMBL, #0x8080 +007d 0021 HALT + +// we got a wrong opcode - HALT +007e 16fc baad SI @DMBH, #0xbaad +0080 2efd SRS @DMBL, $30 +0081 0021 HALT + + +//////// +// Opcode_00() + +0082 8100 CLR $30 +0083 8970 CLR.L $31 : $30, @$0 +0084 8e78 S40.L : $31, @$0 +0085 2ece SRS @DSMAH, $30 +0086 2fcf SRS @DSMAL, $31 +0087 009e 0e44 LRI $30, #0x0e44 +0089 2ecd SRS @DSPA, $30 +008a 0e00 LRIS $30, #0x00 +008b 2ec9 SRS @DSCR, $30 +008c 009e 0040 LRI $30, #0x0040 +008e 2ecb SRS @DSBL, $30 +008f 0081 0e44 LRI $1, #0x0e44 +0091 0082 0000 LRI $2, #0x0000 +0093 009b 009f LRI $27, #0x009f +0095 009a 0140 LRI $26, #0x0140 +0097 8100 CLR $30 +0098 8900 CLR $31 +0099 8f00 S16 +009a 02bf 055c CALL 0x055c // Wait for DMA control reg +009c 193e LRRI $30, @$1 +009d 193c LRRI $28, @$1 +009e b100 TST $30 +009f 193f LRRI $31, @$1 +00a0 0294 00a6 JNE 0x00a6 +00a2 005a LOOP $26 +00a3 1b5e SRRI @$2, $30 +00a4 029f 00ae JMP 0x00ae +00a6 9900 ASR16 $31 +00a7 1b5e SRRI @$2, $30 +00a8 1b5c SRRI @$2, $28 +00a9 007b 00ad BLOOP $27, 0x00ad +00ab 4c00 ADD $30, $31 +00ac 1b5e SRRI @$2, $30 +00ad 1b5c SRRI @$2, $28 +00ae 193e LRRI $30, @$1 +00af 193c LRRI $28, @$1 +00b0 b100 TST $30 +00b1 193f LRRI $31, @$1 +00b2 0294 00b8 JNE 0x00b8 +00b4 005a LOOP $26 +00b5 1b5e SRRI @$2, $30 +00b6 029f 00c0 JMP 0x00c0 +00b8 9900 ASR16 $31 +00b9 1b5e SRRI @$2, $30 +00ba 1b5c SRRI @$2, $28 +00bb 007b 00bf BLOOP $27, 0x00bf +00bd 4c00 ADD $30, $31 +00be 1b5e SRRI @$2, $30 +00bf 1b5c SRRI @$2, $28 +00c0 193e LRRI $30, @$1 +00c1 193c LRRI $28, @$1 +00c2 b100 TST $30 +00c3 193f LRRI $31, @$1 +00c4 0294 00ca JNE 0x00ca +00c6 005a LOOP $26 +00c7 1b5e SRRI @$2, $30 +00c8 029f 00d2 JMP 0x00d2 +00ca 9900 ASR16 $31 +00cb 1b5e SRRI @$2, $30 +00cc 1b5c SRRI @$2, $28 +00cd 007b 00d1 BLOOP $27, 0x00d1 +00cf 4c00 ADD $30, $31 +00d0 1b5e SRRI @$2, $30 +00d1 1b5c SRRI @$2, $28 +00d2 0082 0400 LRI $2, #0x0400 +00d4 193e LRRI $30, @$1 +00d5 193c LRRI $28, @$1 +00d6 b179 TST.L $30 : $31, @$1 +00d7 0294 00dd JNE 0x00dd +00d9 005a LOOP $26 +00da 1b5e SRRI @$2, $30 +00db 029f 00e5 JMP 0x00e5 +00dd 9900 ASR16 $31 +00de 1b5e SRRI @$2, $30 +00df 1b5c SRRI @$2, $28 +00e0 007b 00e4 BLOOP $27, 0x00e4 +00e2 4c00 ADD $30, $31 +00e3 1b5e SRRI @$2, $30 +00e4 1b5c SRRI @$2, $28 +00e5 193e LRRI $30, @$1 +00e6 193c LRRI $28, @$1 +00e7 b179 TST.L $30 : $31, @$1 +00e8 0294 00ee JNE 0x00ee +00ea 005a LOOP $26 +00eb 1b5e SRRI @$2, $30 +00ec 029f 00f6 JMP 0x00f6 +00ee 9900 ASR16 $31 +00ef 1b5e SRRI @$2, $30 +00f0 1b5c SRRI @$2, $28 +00f1 007b 00f5 BLOOP $27, 0x00f5 +00f3 4c00 ADD $30, $31 +00f4 1b5e SRRI @$2, $30 +00f5 1b5c SRRI @$2, $28 +00f6 193e LRRI $30, @$1 +00f7 193c LRRI $28, @$1 +00f8 b179 TST.L $30 : $31, @$1 +00f9 0294 00ff JNE 0x00ff +00fb 005a LOOP $26 +00fc 1b5e SRRI @$2, $30 +00fd 029f 0107 JMP 0x0107 +00ff 9900 ASR16 $31 +0100 1b5e SRRI @$2, $30 +0101 1b5c SRRI @$2, $28 +0102 007b 0106 BLOOP $27, 0x0106 +0104 4c00 ADD $30, $31 +0105 1b5e SRRI @$2, $30 +0106 1b5c SRRI @$2, $28 +0107 0082 07c0 LRI $2, #0x07c0 +0109 193e LRRI $30, @$1 +010a 193c LRRI $28, @$1 +010b b179 TST.L $30 : $31, @$1 +010c 0294 0112 JNE 0x0112 +010e 005a LOOP $26 +010f 1b5e SRRI @$2, $30 +0110 029f 011a JMP 0x011a +0112 9900 ASR16 $31 +0113 1b5e SRRI @$2, $30 +0114 1b5c SRRI @$2, $28 +0115 007b 0119 BLOOP $27, 0x0119 +0117 4c00 ADD $30, $31 +0118 1b5e SRRI @$2, $30 +0119 1b5c SRRI @$2, $28 +011a 193e LRRI $30, @$1 +011b 193c LRRI $28, @$1 +011c b179 TST.L $30 : $31, @$1 +011d 0294 0123 JNE 0x0123 +011f 005a LOOP $26 +0120 1b5e SRRI @$2, $30 +0121 029f 012b JMP 0x012b +0123 9900 ASR16 $31 +0124 1b5e SRRI @$2, $30 +0125 1b5c SRRI @$2, $28 +0126 007b 012a BLOOP $27, 0x012a +0128 4c00 ADD $30, $31 +0129 1b5e SRRI @$2, $30 +012a 1b5c SRRI @$2, $28 +012b 193e LRRI $30, @$1 +012c 193c LRRI $28, @$1 +012d b179 TST.L $30 : $31, @$1 +012e 0294 0134 JNE 0x0134 +0130 005a LOOP $26 +0131 1b5e SRRI @$2, $30 +0132 029f 013c JMP 0x013c +0134 9900 ASR16 $31 +0135 1b5e SRRI @$2, $30 +0136 1b5c SRRI @$2, $28 +0137 007b 013b BLOOP $27, 0x013b +0139 4c00 ADD $30, $31 +013a 1b5e SRRI @$2, $30 +013b 1b5c SRRI @$2, $28 +013c 029f 0068 JMP 0x0068 // Return to message loop. + + +// Opcode_01() +013e 0085 ffff LRI $5, #0xffff +0140 8150 CLR.L $30 : $26, @$0 +0141 8940 CLR.L $31 : $24, @$0 +0142 8e48 S40.L : $25, @$0 +0143 00fa 0e17 SR @0x0e17, $26 +0145 00f8 0e18 SR @0x0e18, $24 +0147 0081 0000 LRI $1, #0x0000 +0149 02bf 04f1 CALL 0x04f1 +014b 00da 0e17 LR $26, @0x0e17 +014d 00d8 0e18 LR $24, @0x0e18 +014f 8948 CLR.L $31 : $25, @$0 +0150 0081 0400 LRI $1, #0x0400 +0152 02bf 04f1 CALL 0x04f1 +0154 00da 0e17 LR $26, @0x0e17 +0156 00d8 0e18 LR $24, @0x0e18 +0158 8948 CLR.L $31 : $25, @$0 +0159 0081 07c0 LRI $1, #0x07c0 +015b 02bf 04f1 CALL 0x04f1 +015d 029f 0068 JMP 0x0068 // Return to message loop. + + +// Opcode_09() +015f 0086 07c0 LRI $6, #0x07c0 +0161 02bf 0484 CALL 0x0484 +0163 029f 0068 JMP 0x0068 // Return to message loop. + +// DMA something back to RAM +// Opcode_06() +0165 8100 CLR $30 +0166 8e00 S40 +0167 191e LRRI $30, @$0 +0168 191c LRRI $28, @$0 +0169 2ece SRS @DSMAH, $30 +016a 2ccf SRS @DSMAL, $28 +016b 16cd 0000 SI @DSPA, #0x0000 +016d 16c9 0001 SI @DSCR, #0x0001 +016f 16cb 0780 SI @DSBL, #0x0780 +0171 02bf 055c CALL 0x055c // Wait for DMA control reg +0173 029f 0068 JMP 0x0068 // Return to message loop. + + +// Opcode_17() +0175 8100 CLR $30 +0176 8970 CLR.L $31 : $30, @$0 +0177 8e60 S40.L : $28, @$0 +0178 2ece SRS @DSMAH, $30 +0179 2ccf SRS @DSMAL, $28 +017a 16cd 0e44 SI @DSPA, #0x0e44 +017c 16c9 0000 SI @DSCR, #0x0000 +017e 8900 CLR $31 +017f 0d20 LRIS $29, #0x20 +0180 2dcb SRS @DSBL, $29 +0181 4c00 ADD $30, $31 +0182 1c80 MRR $4, $0 +0183 0080 0280 LRI $0, #0x0280 +0185 0081 0000 LRI $1, #0x0000 +0187 0082 0140 LRI $2, #0x0140 +0189 0083 0e44 LRI $3, #0x0e44 +018b 0a00 LRIS $26, #0x00 +018c 27c9 LRS $31, @DSCR +018d 03a0 0004 ANDCF $31, #0x0004 +018f 029c 018c JZR 0x018c // wait for dma loop +0191 2ece SRS @DSMAH, $30 +0192 2ccf SRS @DSMAL, $28 +0193 16cd 0e54 SI @DSPA, #0x0e54 +0195 16c9 0000 SI @DSCR, #0x0000 +0197 16cb 0260 SI @DSBL, #0x0260 +0199 009f 00a0 LRI $31, #0x00a0 +019b 8f00 S16 +019c 007f 01a5 BLOOP $31, 0x01a5 +019e 197e LRRI $30, @$3 +019f 1b1a SRRI @$0, $26 +01a0 197c LRRI $28, @$3 +01a1 1b1a SRRI @$0, $26 +01a2 1b5e SRRI @$2, $30 +01a3 7c22 NEG.S $30 : @$2, $28 +01a4 1b3e SRRI @$1, $30 +01a5 1b3c SRRI @$1, $28 +01a6 1c04 MRR $0, $4 +01a7 029f 0068 JMP 0x0068 // Return to message loop. + + +// Opcode_13() +01a9 8e70 S40.L : $30, @$0 +01aa 8960 CLR.L $31 : $28, @$0 +01ab 191f LRRI $31, @$0 +01ac 2ece SRS @DSMAH, $30 +01ad 2ccf SRS @DSMAL, $28 +01ae 16cd 0c00 SI @DSPA, #0x0c00 +01b0 16c9 0000 SI @DSCR, #0x0000 +01b2 0503 ADDIS $33, #0x03 +01b3 0340 fff0 ANDI $33, #0xfff0 +01b5 2fcb SRS @DSBL, $31 +01b6 02bf 055c CALL 0x055c // Wait for DMA control reg +01b8 0080 0c00 LRI $0, #0x0c00 +01ba 029f 0068 JMP 0x0068 // Return to message loop. + + +// Opcode_02() +01bc 8100 CLR $30 +01bd 8970 CLR.L $31 : $30, @$0 +01be 8e78 S40.L : $31, @$0 +01bf 2ece SRS @DSMAH, $30 +01c0 2fcf SRS @DSMAL, $31 +01c1 16cd 0b80 SI @DSPA, #0x0b80 +01c3 16c9 0000 SI @DSCR, #0x0000 +01c5 16cb 00c0 SI @DSBL, #0x00c0 +01c7 0082 0e08 LRI $2, #0x0e08 +01c9 009f 0000 LRI $31, #0x0000 +01cb 1b5f SRRI @$2, $31 +01cc 009f 0140 LRI $31, #0x0140 +01ce 1b5f SRRI @$2, $31 +01cf 009f 0280 LRI $31, #0x0280 +01d1 1b5f SRRI @$2, $31 +01d2 009f 0400 LRI $31, #0x0400 +01d4 1b5f SRRI @$2, $31 +01d5 009f 0540 LRI $31, #0x0540 +01d7 1b5f SRRI @$2, $31 +01d8 009f 0680 LRI $31, #0x0680 +01da 1b5f SRRI @$2, $31 +01db 009f 07c0 LRI $31, #0x07c0 +01dd 1b5f SRRI @$2, $31 +01de 009f 0900 LRI $31, #0x0900 +01e0 1b5f SRRI @$2, $31 +01e1 009f 0a40 LRI $31, #0x0a40 +01e3 1b5f SRRI @$2, $31 +01e4 02bf 055c CALL 0x055c // Wait for DMA control reg +01e6 00de 0ba7 LR $30, @0x0ba7 // current PB PBInitialTimeDelay[o] +01e8 00df 0ba8 LR $31, @0x0ba8 // current PB PBInitialTimeDelay[1] +01ea 2ece SRS @DSMAH, $30 +01eb 2fcf SRS @DSMAL, $31 +01ec 16cd 03c0 SI @DSPA, #0x03c0 +01ee 16c9 0000 SI @DSCR, #0x0000 +01f0 16cb 0080 SI @DSBL, #0x0080 +01f2 8100 CLR $30 +01f3 8900 CLR $31 +01f4 00de 0b84 LR $30, @0x0b84 // current PB src_type +01f6 009f 0b31 LRI $31, #0x0b31 // src type jmp table base addr +01f8 4c00 ADD $30, $31 +01f9 1c7e MRR $3, $30 +01fa 0213 ILRR $30, @$3 +01fb 00fe 0e15 SR @0x0e15, $30 +01fd 00de 0b85 LR $30, @0x0b85 // unknown +01ff 009f 0b34 LRI $31, #0x0b34 +0201 4c00 ADD $30, $31 +0202 1c7e MRR $3, $30 +0203 0213 ILRR $30, @$3 +0204 00fe 0e16 SR @0x0e16, $30 +0206 00de 0b86 LR $30, @0x0b86 // current PB mixer_control +0208 009f 0b11 LRI $31, #0x0b11 // mixer control jmp table base addr +020a 4c00 ADD $30, $31 +020b 1c7e MRR $3, $30 +020c 0213 ILRR $30, @$3 +020d 00fe 0e14 SR @0x0e14, $30 +020f 8100 CLR $30 +0210 00de 0b9b LR $30, @0x0b9b +0212 b100 TST $30 +0213 0295 023a JEQ 0x023a +0215 8900 CLR $31 +0216 00df 0b9e LR $31, @0x0b9e // pb->PBInitialTimeDelay->offsetLeft +0218 0300 0cc0 ADDI $33, #0x0cc0 +021a 00ff 0e40 SR @0x0e40, $31 +021c 00df 0b9f LR $31, @0x0b9f +021e 0300 0cc0 ADDI $33, #0x0cc0 +0220 00ff 0e41 SR @0x0e41, $31 +0222 009f 0ce0 LRI $31, #0x0ce0 +0224 00ff 0e42 SR @0x0e42, $31 +0226 00ff 0e43 SR @0x0e43, $31 +0228 02bf 055c CALL 0x055c // Wait for DMA control reg +022a 00de 0b9c LR $30, @0x0b9c +022c 2ece SRS @DSMAH, $30 +022d 00de 0b9d LR $30, @0x0b9d +022f 2ecf SRS @DSMAL, $30 +0230 16cd 0cc0 SI @DSPA, #0x0cc0 +0232 16c9 0000 SI @DSCR, #0x0000 +0234 16cb 0040 SI @DSBL, #0x0040 +0236 02bf 055c CALL 0x055c // Wait for DMA control reg +0238 029f 0068 JMP 0x0068 // Return to message loop. // return out of the function +023a 009f 0ce0 LRI $31, #0x0ce0 +023c 00ff 0e42 SR @0x0e42, $31 +023e 00ff 0e40 SR @0x0e40, $31 +0240 00ff 0e41 SR @0x0e41, $31 +0242 00ff 0e43 SR @0x0e43, $31 +0244 02bf 055c CALL 0x055c // Wait for DMA control reg +0246 029f 0068 JMP 0x0068 // Return to message loop. + + +// Opcode_03() +0248 8e00 S40 +0249 00e0 0e07 SR @0x0e07, $0 +024b 0080 0ba2 LRI $0, #0x0ba2 +024d 0081 03c0 LRI $1, #0x03c0 +024f 0e05 LRIS $30, #0x05 +0250 00fe 0e04 SR @0x0e04, $30 +0252 8900 CLR $31 +0253 8150 CLR.L $30 : $26, @$0 +0254 009f 0b80 LRI $31, #0x0b80 +0256 007a 025b BLOOP $26, 0x025b +0258 193e LRRI $30, @$1 +0259 4c49 ADD.L $30, $31 : $25, @$1 +025a 1c5e MRR $2, $30 +025b 1a59 SRR @$2, $25 +025c 0083 0e05 LRI $3, #0x0e05 +025e 1b61 SRRI @$3, $1 +025f 1b60 SRRI @$3, $0 +0260 00de 0b87 LR $30, @0x0b87 // is pb->running? +0262 0601 CMPIS $32, #0x01 +0263 0295 0267 JEQ 0x0267 +0265 029f 0332 JMP 0x0332 +0267 00de 0e42 LR $30, @0x0e42 // we got here - yes, it's running +0269 00fe 0e1c SR @0x0e1c, $30 +026b 00c3 0e15 LR $3, @0x0e15 +026d 177f CALLR $3 // Call the Src Decoder + + +// Volume Envelope +026e 8e00 S40 +026f 8a00 M2 +0270 8100 CLR $30 +0271 8900 CLR $31 +0272 00de 0bb3 LR $30, @0x0bb3 // PBVolumeEnvelope->cur_volume_delta +0274 00df 0bb2 LR $31, @0x0bb2 // PBVolumeEnvelope->cur_volume +0276 1f1f MRR $24, $31 +0277 4d00 ADD $31, $30 +0278 1481 ASL $32, #0x01 +0279 8d1e SET15.MV : $27, $30 +027a 1fd8 MRR $30, $24 +027b 0098 8000 LRI $24, #0x8000 +027d 0080 0e44 LRI $0, #0x0e44 +027f a830 MULX.S $24, $27 : @$0, $30 +0280 ac38 MULXAC.S $24, $27, $30 : @$0, $31 +0281 ad30 MULXAC.S $24, $27, $31 : @$0, $30 +0282 ac38 MULXAC.S $24, $27, $30 : @$0, $31 +0283 ad30 MULXAC.S $24, $27, $31 : @$0, $30 +0284 ac38 MULXAC.S $24, $27, $30 : @$0, $31 +0285 ad30 MULXAC.S $24, $27, $31 : @$0, $30 +0286 ac38 MULXAC.S $24, $27, $30 : @$0, $31 +0287 ad30 MULXAC.S $24, $27, $31 : @$0, $30 +0288 ac38 MULXAC.S $24, $27, $30 : @$0, $31 +0289 ad30 MULXAC.S $24, $27, $31 : @$0, $30 +028a ac38 MULXAC.S $24, $27, $30 : @$0, $31 +028b ad30 MULXAC.S $24, $27, $31 : @$0, $30 +028c ac38 MULXAC.S $24, $27, $30 : @$0, $31 +028d ad30 MULXAC.S $24, $27, $31 : @$0, $30 +028e ac38 MULXAC.S $24, $27, $30 : @$0, $31 +028f ad30 MULXAC.S $24, $27, $31 : @$0, $30 +0290 ac38 MULXAC.S $24, $27, $30 : @$0, $31 +0291 ad30 MULXAC.S $24, $27, $31 : @$0, $30 +0292 ac38 MULXAC.S $24, $27, $30 : @$0, $31 +0293 ad30 MULXAC.S $24, $27, $31 : @$0, $30 +0294 ac38 MULXAC.S $24, $27, $30 : @$0, $31 +0295 ad30 MULXAC.S $24, $27, $31 : @$0, $30 +0296 ac38 MULXAC.S $24, $27, $30 : @$0, $31 +0297 ad30 MULXAC.S $24, $27, $31 : @$0, $30 +0298 ac38 MULXAC.S $24, $27, $30 : @$0, $31 +0299 ad30 MULXAC.S $24, $27, $31 : @$0, $30 +029a ac38 MULXAC.S $24, $27, $30 : @$0, $31 +029b ad30 MULXAC.S $24, $27, $31 : @$0, $30 +029c ac38 MULXAC.S $24, $27, $30 : @$0, $31 +029d ad30 MULXAC.S $24, $27, $31 : @$0, $30 +029e ac38 MULXAC.S $24, $27, $30 : @$0, $31 +029f 00fe 0bb2 SR @0x0bb2, $30 // write back to PBVolumeEnvelope->cur_volume + +// Initial Time Delay + (IIR Filter?) +02a1 8f00 S16 +02a2 0080 0e44 LRI $0, #0x0e44 +02a4 00c1 0e43 LR $1, @0x0e43 +02a6 1c61 MRR $3, $1 +02a7 193a LRRI $26, @$1 +02a8 1918 LRRI $24, @$0 +02a9 9059 MUL.L $24, $26 : $27, @$1 +02aa 1919 LRRI $25, @$0 +02ab 9e51 MULMV.L $25, $27, $30 : $26, @$1 +02ac 8080 NX.LS : $24, $30 +02ad 9759 MULMV.L $24, $26, $31 : $27, @$1 +02ae 8091 NX.LS : $25, $31 +02af 9e51 MULMV.L $25, $27, $30 : $26, @$1 +02b0 8080 NX.LS : $24, $30 +02b1 9759 MULMV.L $24, $26, $31 : $27, @$1 +02b2 8091 NX.LS : $25, $31 +02b3 9e51 MULMV.L $25, $27, $30 : $26, @$1 +02b4 8080 NX.LS : $24, $30 +02b5 9759 MULMV.L $24, $26, $31 : $27, @$1 +02b6 8091 NX.LS : $25, $31 +02b7 9e51 MULMV.L $25, $27, $30 : $26, @$1 +02b8 8080 NX.LS : $24, $30 +02b9 9759 MULMV.L $24, $26, $31 : $27, @$1 +02ba 8091 NX.LS : $25, $31 +02bb 9e51 MULMV.L $25, $27, $30 : $26, @$1 +02bc 8080 NX.LS : $24, $30 +02bd 9759 MULMV.L $24, $26, $31 : $27, @$1 +02be 8091 NX.LS : $25, $31 +02bf 9e51 MULMV.L $25, $27, $30 : $26, @$1 +02c0 8080 NX.LS : $24, $30 +02c1 9759 MULMV.L $24, $26, $31 : $27, @$1 +02c2 8091 NX.LS : $25, $31 +02c3 9e51 MULMV.L $25, $27, $30 : $26, @$1 +02c4 8080 NX.LS : $24, $30 +02c5 9759 MULMV.L $24, $26, $31 : $27, @$1 +02c6 8091 NX.LS : $25, $31 +02c7 9e51 MULMV.L $25, $27, $30 : $26, @$1 +02c8 8080 NX.LS : $24, $30 +02c9 9759 MULMV.L $24, $26, $31 : $27, @$1 +02ca 8091 NX.LS : $25, $31 +02cb 9e51 MULMV.L $25, $27, $30 : $26, @$1 +02cc 8080 NX.LS : $24, $30 +02cd 9759 MULMV.L $24, $26, $31 : $27, @$1 +02ce 8091 NX.LS : $25, $31 +02cf 9e51 MULMV.L $25, $27, $30 : $26, @$1 +02d0 8080 NX.LS : $24, $30 +02d1 9759 MULMV.L $24, $26, $31 : $27, @$1 +02d2 8091 NX.LS : $25, $31 +02d3 9e51 MULMV.L $25, $27, $30 : $26, @$1 +02d4 8080 NX.LS : $24, $30 +02d5 9759 MULMV.L $24, $26, $31 : $27, @$1 +02d6 8091 NX.LS : $25, $31 +02d7 9e51 MULMV.L $25, $27, $30 : $26, @$1 +02d8 8080 NX.LS : $24, $30 +02d9 9759 MULMV.L $24, $26, $31 : $27, @$1 +02da 8091 NX.LS : $25, $31 +02db 9e51 MULMV.L $25, $27, $30 : $26, @$1 +02dc 8080 NX.LS : $24, $30 +02dd 9759 MULMV.L $24, $26, $31 : $27, @$1 +02de 8091 NX.LS : $25, $31 +02df 9e51 MULMV.L $25, $27, $30 : $26, @$1 +02e0 8080 NX.LS : $24, $30 +02e1 9759 MULMV.L $24, $26, $31 : $27, @$1 +02e2 8091 NX.LS : $25, $31 +02e3 9e51 MULMV.L $25, $27, $30 : $26, @$1 +02e4 8080 NX.LS : $24, $30 +02e5 9759 MULMV.L $24, $26, $31 : $27, @$1 +02e6 8091 NX.LS : $25, $31 +02e7 9e00 MULMV $25, $27, $30 +02e8 6f33 MOVP.S $31 : @$3, $30 +02e9 1b7f SRRI @$3, $31 +02ea 00c3 0e14 LR $3, @0x0e14 // call the mixer +02ec 8f00 S16 +02ed 8d00 SET15 +02ee 8a00 M2 +02ef 177f CALLR $3 +02f0 8100 CLR $30 +02f1 00de 0b9b LR $30, @0x0b9b // check (PBInitialTimeDelay->firstStart == 0) +02f3 b100 TST $30 +02f4 0295 032a JEQ 0x032a + + +02f6 00de 0e42 LR $30, @0x0e42 +02f8 00fe 0e43 SR @0x0e43, $30 +02fa 8100 CLR $30 +02fb 8900 CLR $31 +02fc 00de 0b9e LR $30, @0x0b9e +02fe 00df 0ba0 LR $31, @0x0ba0 +0300 8200 CMP +0301 0293 0306 JX3 0x0306 +0303 7800 DECM $30 +0304 029f 0309 JMP 0x0309 +0306 0295 0309 JEQ 0x0309 +0308 7400 INCM $30 +0309 00fe 0b9e SR @0x0b9e, $30 +030b 00df 0e43 LR $31, @0x0e43 +030d 05e0 ADDIS $33, #0xe0 +030e 4c00 ADD $30, $31 +030f 00fe 0e40 SR @0x0e40, $30 +0311 8100 CLR $30 +0312 8900 CLR $31 +0313 00de 0b9f LR $30, @0x0b9f +0315 00df 0ba1 LR $31, @0x0ba1 +0317 8200 CMP +0318 0293 031d JX3 0x031d +031a 7800 DECM $30 +031b 029f 0320 JMP 0x0320 +031d 0295 0320 JEQ 0x0320 +031f 7400 INCM $30 +0320 00fe 0b9f SR @0x0b9f, $30 +0322 00df 0e43 LR $31, @0x0e43 +0324 05e0 ADDIS $33, #0xe0 +0325 4c00 ADD $30, $31 +0326 00fe 0e41 SR @0x0e41, $30 +0328 029f 0332 JMP 0x0332 + +032a 00de 0e42 LR $30, @0x0e42 +032c 00fe 0e40 SR @0x0e40, $30 +032e 00fe 0e41 SR @0x0e41, $30 +0330 00fe 0e43 SR @0x0e43, $30 +0332 8100 CLR $30 // Jumps here when a PB isn't ->running. +0333 8e00 S40 +0334 8400 CLRP +0335 8900 CLR $31 +0336 1efe MRR $23, $30 +0337 0e40 LRIS $30, #0x40 +0338 1ebe MRR $21, $30 +0339 0083 0e08 LRI $3, #0x0e08 +033b 1c03 MRR $0, $3 +033c 1ff5 MRR $31, $21 +033d 191a LRRI $26, @$0 + + +033e f858 ADDPAXZ.L $30, $26 : $27, @$0 +033f fba0 ADDPAXZ.LS $31, $27 : $26, $30 +0340 f8b1 ADDPAXZ.LS $30, $26 : $27, $31 +0341 fba0 ADDPAXZ.LS $31, $27 : $26, $30 +0342 f8b1 ADDPAXZ.LS $30, $26 : $27, $31 +0343 fba0 ADDPAXZ.LS $31, $27 : $26, $30 +0344 f8b1 ADDPAXZ.LS $30, $26 : $27, $31 +0345 fba0 ADDPAXZ.LS $31, $27 : $26, $30 +0346 f83b ADDPAXZ.S $30, $26 : @$3, $31 + + + + +0347 1b7e SRRI @$3, $30 +0348 0083 0e04 LRI $3, #0x0e04 +034a 8100 CLR $30 +034b 8973 CLR.L $31 : $30, @$3 +034c 1961 LRRI $1, @$3 +034d 1960 LRRI $0, @$3 +034e 7800 DECM $30 +034f 00fe 0e04 SR @0x0e04, $30 +0351 0294 0253 JNE 0x0253 +0353 8e00 S40 +0354 8100 CLR $30 +0355 00de 0b9b LR $30, @0x0b9b // check (PBInitialTimeDelay->firstStart == 0) or write back to MEM?! +0357 b100 TST $30 +0358 0295 036a JEQ 0x036a + + +035a 00de 0b9c LR $30, @0x0b9c +035c 00dc 0b9d LR $28, @0x0b9d +035e 2ece SRS @DSMAH, $30 +035f 2ccf SRS @DSMAL, $28 +0360 8100 CLR $30 +0361 00de 0e1c LR $30, @0x0e1c +0363 2ecd SRS @DSPA, $30 +0364 16c9 0001 SI @DSCR, #0x0001 +0366 16cb 0040 SI @DSBL, #0x0040 +0368 02bf 055c CALL 0x055c // Wait for DMA control reg + + +// write back the PB +036a 8100 CLR $30 +036b 8900 CLR $31 +036c 00de 0b82 LR $30, @0x0b82 +036e 00df 0b83 LR $31, @0x0b83 +0370 2ece SRS @DSMAH, $30 +0371 2fcf SRS @DSMAL, $31 +0372 16cd 0b80 SI @DSPA, #0x0b80 +0374 16c9 0001 SI @DSCR, #0x0001 +0376 16cb 00c0 SI @DSBL, #0x00c0 +0378 02bf 055c CALL 0x055c // Wait for DMA control reg +037a 8100 CLR $30 + +// check if there is a another PB linked, if yes copy and setup this one (like Opcode2()) +037b 00de 0b80 LR $30, @0x0b80 +037d 00dc 0b81 LR $28, @0x0b81 +037f b100 TST $30 +0380 0294 0386 JNE 0x0386 +0382 00c0 0e07 LR $0, @0x0e07 +0384 029f 0068 JMP 0x0068 // Return to message loop. --> return to next opcode + +// copy the next PB to memory +0386 2ece SRS @DSMAH, $30 +0387 2ccf SRS @DSMAL, $28 +0388 16cd 0b80 SI @DSPA, #0x0b80 // b80 - paramblock +038a 16c9 0000 SI @DSCR, #0x0000 +038c 16cb 00c0 SI @DSBL, #0x00c0 +038e 0082 0e08 LRI $2, #0x0e08 +0390 009f 0000 LRI $31, #0x0000 +0392 1b5f SRRI @$2, $31 +0393 009f 0140 LRI $31, #0x0140 +0395 1b5f SRRI @$2, $31 +0396 009f 0280 LRI $31, #0x0280 +0398 1b5f SRRI @$2, $31 +0399 009f 0400 LRI $31, #0x0400 +039b 1b5f SRRI @$2, $31 +039c 009f 0540 LRI $31, #0x0540 +039e 1b5f SRRI @$2, $31 +039f 009f 0680 LRI $31, #0x0680 +03a1 1b5f SRRI @$2, $31 +03a2 009f 07c0 LRI $31, #0x07c0 +03a4 1b5f SRRI @$2, $31 +03a5 009f 0900 LRI $31, #0x0900 +03a7 1b5f SRRI @$2, $31 +03a8 009f 0a40 LRI $31, #0x0a40 +03aa 1b5f SRRI @$2, $31 +03ab 02bf 055c CALL 0x055c // Wait for DMA control reg +03ad 00de 0ba7 LR $30, @0x0ba7 +03af 00df 0ba8 LR $31, @0x0ba8 +03b1 2ece SRS @DSMAH, $30 +03b2 2fcf SRS @DSMAL, $31 +03b3 16cd 03c0 SI @DSPA, #0x03c0 +03b5 16c9 0000 SI @DSCR, #0x0000 +03b7 16cb 0080 SI @DSBL, #0x0080 // Don't know w.at this dma xfer is + + + + + +03b9 8100 CLR $30 +03ba 8900 CLR $31 +03bb 00de 0b84 LR $30, @0x0b84 +03bd 009f 0b31 LRI $31, #0x0b31 +03bf 4c00 ADD $30, $31 +03c0 1c7e MRR $3, $30 +03c1 0213 ILRR $30, @$3 +03c2 00fe 0e15 SR @0x0e15, $30 +03c4 00de 0b85 LR $30, @0x0b85 +03c6 009f 0b34 LRI $31, #0x0b34 +03c8 4c00 ADD $30, $31 +03c9 1c7e MRR $3, $30 +03ca 0213 ILRR $30, @$3 +03cb 00fe 0e16 SR @0x0e16, $30 +03cd 00de 0b86 LR $30, @0x0b86 +03cf 009f 0b11 LRI $31, #0x0b11 // mixer control jmp table base addr +03d1 4c00 ADD $30, $31 +03d2 1c7e MRR $3, $30 +03d3 0213 ILRR $30, @$3 +03d4 00fe 0e14 SR @0x0e14, $30 +03d6 8100 CLR $30 +03d7 00de 0b9b LR $30, @0x0b9b +03d9 b100 TST $30 +03da 0295 0403 JEQ 0x0403 +03dc 8900 CLR $31 +03dd 00df 0b9e LR $31, @0x0b9e +03df 0300 0cc0 ADDI $33, #0x0cc0 +03e1 00ff 0e40 SR @0x0e40, $31 +03e3 00df 0b9f LR $31, @0x0b9f +03e5 0300 0cc0 ADDI $33, #0x0cc0 +03e7 00ff 0e41 SR @0x0e41, $31 +03e9 009f 0ce0 LRI $31, #0x0ce0 +03eb 00ff 0e42 SR @0x0e42, $31 +03ed 00ff 0e43 SR @0x0e43, $31 +03ef 02bf 055c CALL 0x055c // Wait for DMA control reg +03f1 00de 0b9c LR $30, @0x0b9c +03f3 2ece SRS @DSMAH, $30 +03f4 00de 0b9d LR $30, @0x0b9d +03f6 2ecf SRS @DSMAL, $30 +03f7 16cd 0cc0 SI @DSPA, #0x0cc0 +03f9 16c9 0000 SI @DSCR, #0x0000 +03fb 16cb 0040 SI @DSBL, #0x0040 +03fd 02bf 055c CALL 0x055c // Wait for DMA control reg // wait for DMA +03ff 00c0 0e07 LR $0, @0x0e07 +0401 029f 0248 JMP 0x0248 // Opcode3() - "self calling" +0403 009f 0ce0 LRI $31, #0x0ce0 // <<< branch from 03da +0405 00ff 0e42 SR @0x0e42, $31 +0407 00ff 0e40 SR @0x0e40, $31 +0409 00ff 0e41 SR @0x0e41, $31 +040b 00ff 0e43 SR @0x0e43, $31 +040d 02bf 055c CALL 0x055c // Wait for DMA control reg +040f 00c0 0e07 LR $0, @0x0e07 +0411 029f 0248 JMP 0x0248 // Opcode3() - "self calling" + + +// Opcode_04() - do a DMA transfer +0413 8e00 S40 +0414 0086 0400 LRI $6, #0x0400 +0416 8100 CLR $30 +0417 8970 CLR.L $31 : $30, @$0 +0418 191c LRRI $28, @$0 +0419 2ece SRS @DSMAH, $30 +041a 2ccf SRS @DSMAL, $28 +041b 1fc6 MRR $30, $6 +041c 2ecd SRS @DSPA, $30 +041d 16c9 0001 SI @DSCR, #0x0001 +041f 16cb 0780 SI @DSBL, #0x0780 +0421 02bf 055c CALL 0x055c // Wait for DMA control reg +0423 02bf 0484 CALL 0x0484 +0425 029f 0068 JMP 0x0068 // Return to message loop. + +// DMA soemthing back to RAM +// Opcode_05() - do another DMA transfer +0427 8e00 S40 +0428 0086 07c0 LRI $6, #0x07c0 +042a 8100 CLR $30 +042b 8970 CLR.L $31 : $30, @$0 +042c 191c LRRI $28, @$0 +042d 2ece SRS @DSMAH, $30 +042e 2ccf SRS @DSMAL, $28 +042f 1fc6 MRR $30, $6 +0430 2ecd SRS @DSPA, $30 +0431 16c9 0001 SI @DSCR, #0x0001 +0433 16cb 0780 SI @DSBL, #0x0780 +0435 02bf 055c CALL 0x055c // Wait for DMA control reg +0437 02bf 0484 CALL 0x0484 +0439 029f 0068 JMP 0x0068 // Return to message loop. + +///////////////////////////////////// +// DMA the sound buffer back to RAM +// Opcode_14() +// called by CT +// +043b 8c00 CLR15 +043c 8a00 M2 + +// send the 0x280 to 0x500 to CPU RAM + 043d 8100 CLR $30 + 043e 8970 CLR.L $31 : $30, @$0 + 043f 191f LRRI $31, @$0 + 0440 2ece SRS @DSMAH, $30 + 0441 2fcf SRS @DSMAL, $31 + 0442 16cd 0280 SI @DSPA, #0x0280 + 0444 16c9 0001 SI @DSCR, #0x0001 + 0446 16cb 0280 SI @DSBL, #0x0280 + 0448 8f50 S16.L : $26, @$0 + 0449 8140 CLR.L $30 : $24, @$0 + 044a 0081 0400 LRI $1, #0x0400 + 044c 0083 0000 LRI $3, #0x0000 + 044e 0082 0140 LRI $2, #0x0140 + 0450 0099 0080 LRI $25, #0x0080 + 0452 02bf 055c CALL 0x055c // Wait for DMA control reg + +// interleave loop and DMA the buffer to CPU... call innerloop 5 times (5 * 32Byte) + 0454 1105 046c BLOOPI #0x05, 0x046c + 0456 1f61 MRR $27, $1 + + // interleave 32 shorts (from left and right buffer) + 0457 1120 045e BLOOPI #0x20, 0x045e + 0459 8972 CLR.L $31 : $30, @$2 + 045a 195c LRRI $28, @$2 + 045b f07b LSL16.L $30 : $31, @$3 + 045c 197d LRRI $29, @$3 + 045d f131 LSL16.S $31 : @$1, $30 + 045e 8139 CLR.S $30 : @$1, $31 + // end: innerloop + + 045f 8900 CLR $31 + 0460 6800 MOVAX $30, $24 + 0461 2ece SRS @DSMAH, $30 + 0462 2ccf SRS @DSMAL, $28 + 0463 1ffb MRR $31, $27 + 0464 2fcd SRS @DSPA, $31 + 0465 0f01 LRIS $31, #0x01 + 0466 2fc9 SRS @DSCR, $31 + 0467 1ff9 MRR $31, $25 // $25 is const 0x80 + 0468 2fcb SRS @DSBL, $31 + 0469 7200 ADDAXL $30, $25 + 046a 1f5e MRR $26, $30 + 046b 1f1c MRR $24, $28 + 046c 8100 CLR $30 +// end: outerloop (strange because shouldnt we wait to the DMA transfer all the time??) + +046d 26c9 LRS $30, @DSCR +046e 02a0 0004 ANDCF $30, #0x0004 +0470 029c 046d JZR 0x046d // wait for DMA loop + +0472 029f 0068 JMP 0x0068 // Return to message loop. + +// Opcode_11() - not implemented +0474 029f 0068 JMP 0x0068 // Return to message loop. + +// Opcode_12() - not implemented +0476 029f 0068 JMP 0x0068 // Return to message loop. + +// Opcode_10() - not implemented +0478 029f 0068 JMP 0x0068 // Return to message loop. + + +// Opcode_15() // end AX List command (write the 0xDCD10002 that we .ave executed the s.it) +047a 16fc dcd1 SI @DMBH, #0xdcd1 +047c 16fd 0002 SI @DMBL, #0x0002 +047e 16fb 0001 SI @DIRQ, #0x0001 +0480 029f 0c91 JMP 0x0c91 + + + +// looks like unused code +0482 029f 0045 JMP 0x0045 + + +// no idea... it usesd for several opcodes +// Opcode_04(), Opcode_05() and Opcode_09() calls it +// per.aps some kind of filter?? +0484 8e00 S40 +0485 191f LRRI $31, @$0 +0486 191d LRRI $29, @$0 +0487 1f5f MRR $26, $31 +0488 1f1d MRR $24, $29 +0489 2fce SRS @DSMAH, $31 +048a 2dcf SRS @DSMAL, $29 +048b 8900 CLR $31 +048c 1fa6 MRR $29, $6 +048d 2dcd SRS @DSPA, $29 +048e 0e00 LRIS $30, #0x00 +048f 2ec9 SRS @DSCR, $30 +0490 8100 CLR $30 +0491 009c 00c0 LRI $28, #0x00c0 +0493 2ccb SRS @DSBL, $28 +0494 1ca0 MRR $5, $0 +0495 0081 0e44 LRI $1, #0x0e44 +0497 4800 ADDAX $30, $24 +0498 1b3e SRRI @$1, $30 +0499 1b3c SRRI @$1, $28 +049a 0b00 LRIS $27, #0x00 +049b 0099 0060 LRI $25, #0x0060 +049d 4b00 ADDAX $31, $25 +049e 1b3d SRRI @$1, $29 +049f 0081 0e44 LRI $1, #0x0e44 +04a1 1c06 MRR $0, $6 +04a2 0083 0000 LRI $3, #0x0000 +04a4 1c43 MRR $2, $3 +04a5 27c9 LRS $31, @DSCR +04a6 03a0 0004 ANDCF $31, #0x0004 +04a8 029c 04a5 JZR 0x04a5 // wait for DMA loop +04aa 1109 04da BLOOPI #0x09, 0x04da +04ac 8e00 S40 +04ad 193a LRRI $26, @$1 +04ae 1938 LRRI $24, @$1 +04af 6900 MOVAX $31, $24 +04b0 2fce SRS @DSMAH, $31 +04b1 2dcf SRS @DSMAL, $29 +04b2 8900 CLR $31 +04b3 193d LRRI $29, @$1 +04b4 2dcd SRS @DSPA, $29 +04b5 16c9 0000 SI @DSCR, #0x0000 +04b7 8100 CLR $30 +04b8 009c 00c0 LRI $28, #0x00c0 +04ba 2ccb SRS @DSBL, $28 +04bb 0081 0e44 LRI $1, #0x0e44 +04bd 4800 ADDAX $30, $24 +04be 1b3e SRRI @$1, $30 +04bf 1b3c SRRI @$1, $28 +04c0 0b00 LRIS $27, #0x00 +04c1 0960 LRIS $25, #0x60 +04c2 4b00 ADDAX $31, $25 +04c3 1b3d SRRI @$1, $29 +04c4 0081 0e44 LRI $1, #0x0e44 +04c6 8f00 S16 +04c7 80f0 NX.LDX : $25, $27, @$1 +04c8 80c0 NX.LDX : $24, $26, @$0 +04c9 6a00 MOVAX $30, $25 +04ca 4800 ADDAX $30, $24 +04cb 1117 04d4 BLOOPI #0x17, 0x04d4 +04cd 80f0 NX.LDX : $25, $27, @$1 +04ce 80c0 NX.LDX : $24, $26, @$0 +04cf 6b32 MOVAX.S $31, $25 : @$2, $30 +04d0 4922 ADDAX.S $31, $24 : @$2, $28 +04d1 80f0 NX.LDX : $25, $27, @$1 +04d2 80c0 NX.LDX : $24, $26, @$0 +04d3 6a3a MOVAX.S $30, $25 : @$2, $31 +04d4 482a ADDAX.S $30, $24 : @$2, $29 +04d5 80f0 NX.LDX : $25, $27, @$1 +04d6 80c0 NX.LDX : $24, $26, @$0 +04d7 6b32 MOVAX.S $31, $25 : @$2, $30 +04d8 4922 ADDAX.S $31, $24 : @$2, $28 +04d9 1b5f SRRI @$2, $31 +04da 1b5d SRRI @$2, $29 +04db 80f0 NX.LDX : $25, $27, @$1 +04dc 80c0 NX.LDX : $24, $26, @$0 +04dd 6a00 MOVAX $30, $25 +04de 4800 ADDAX $30, $24 +04df 1117 04e8 BLOOPI #0x17, 0x04e8 +04e1 80f0 NX.LDX : $25, $27, @$1 +04e2 80c0 NX.LDX : $24, $26, @$0 +04e3 6b32 MOVAX.S $31, $25 : @$2, $30 +04e4 4922 ADDAX.S $31, $24 : @$2, $28 +04e5 80f0 NX.LDX : $25, $27, @$1 +04e6 80c0 NX.LDX : $24, $26, @$0 +04e7 6a3a MOVAX.S $30, $25 : @$2, $31 +04e8 482a ADDAX.S $30, $24 : @$2, $29 +04e9 80f0 NX.LDX : $25, $27, @$1 +04ea 80c0 NX.LDX : $24, $26, @$0 +04eb 6b32 MOVAX.S $31, $25 : @$2, $30 +04ec 4922 ADDAX.S $31, $24 : @$2, $28 +04ed 1b5f SRRI @$2, $31 +04ee 1b5d SRRI @$2, $29 +04ef 1c05 MRR $0, $5 +04f0 02df RET + +// Called by opcode1 +04f1 8e00 S40 +04f2 009b 0e44 LRI $27, #0x0e44 +04f4 009d 00c0 LRI $29, #0x00c0 +04f6 02bf 0541 CALL 0x0541 // Do DMA +04f8 4900 ADDAX $31, $24 +04f9 00ff 0e1d SR @0x0e1d, $31 +04fb 00fd 0e1e SR @0x0e1e, $29 +04fd 8900 CLR $31 +04fe 02bf 055c CALL 0x055c // Wait for DMA control reg +0500 1104 052c BLOOPI #0x04, 0x052c +0502 00da 0e1d LR $26, @0x0e1d +0504 00d8 0e1e LR $24, @0x0e1e +0506 009b 0ea4 LRI $27, #0x0ea4 +0508 009d 00c0 LRI $29, #0x00c0 +050a 02bf 0541 CALL 0x0541 // Do DMA +050c 4900 ADDAX $31, $24 +050d 00ff 0e1d SR @0x0e1d, $31 +050f 00fd 0e1e SR @0x0e1e, $29 +0511 0083 0e44 LRI $3, #0x0e44 +0513 02bf 054c CALL 0x054c +0515 8900 CLR $31 +0516 00da 0e1d LR $26, @0x0e1d +0518 00d8 0e1e LR $24, @0x0e1e +051a 009b 0e44 LRI $27, #0x0e44 +051c 009d 00c0 LRI $29, #0x00c0 +051e 02bf 0541 CALL 0x0541 // Do DMA +0520 4900 ADDAX $31, $24 +0521 00ff 0e1d SR @0x0e1d, $31 +0523 00fd 0e1e SR @0x0e1e, $29 +0525 0083 0ea4 LRI $3, #0x0ea4 +0527 02bf 054c CALL 0x054c +0529 0000 NOP +052a 0000 NOP +052b 8e00 S40 +052c 8900 CLR $31 +052d 00da 0e1d LR $26, @0x0e1d +052f 00d8 0e1e LR $24, @0x0e1e +0531 009b 0ea4 LRI $27, #0x0ea4 +0533 009d 00c0 LRI $29, #0x00c0 +0535 02bf 0541 CALL 0x0541 // Do DMA +0537 4900 ADDAX $31, $24 +0538 0083 0e44 LRI $3, #0x0e44 +053a 02bf 054c CALL 0x054c +053c 0083 0ea4 LRI $3, #0x0ea4 +053e 02bf 054c CALL 0x054c +0540 02df RET + + + +// some code to DMA stuff... +0541 8e00 S40 +0542 00fa ffce SR @DSMAH, $26 +0544 00f8 ffcf SR @DSMAL, $24 +0546 00fb ffcd SR @DSPA, $27 +0548 16c9 0000 SI @DSCR, #0x0000 +054a 2dcb SRS @DSBL, $29 +054b 02df RET + + +// function / some kind of loop to modify a sample? +054c 8f00 S16 +054d 8d00 SET15 +054e 8a00 M2 +054f 197a LRRI $26, @$3 +0550 1978 LRRI $24, @$3 +0551 a000 MULX $24, $25 +0552 b600 MULXMV $26, $25, $30 +0553 1130 055a BLOOPI #0x30, 0x055a +0555 9179 ASR16.L $30 : $31, @$1 +0556 4e6d ADDP.LN $30 : $29, @$1 +0557 197a LRRI $26, @$3 +0558 4d43 ADD.L $31, $30 : $24, @$3 +0559 a039 MULX.S $24, $25 : @$1, $31 +055a b629 MULXMV.S $26, $25, $30 : @$1, $29 +055b 02df RET + +// waits for DMA control reg +055c 26c9 LRS $30, @DSCR +055d 02a0 0004 ANDCF $30, #0x0004 +055f 029c 055c JZR 0x055c +0561 02df RET + +// waits for empty CPU mailbox +0562 26fe LRS $30, @CMBH +0563 02c0 8000 ANDF $30, #0x8000 +0565 029c 0562 JZR 0x0562 +0567 02df RET + +// waits for empty DSP mailbox +0568 26fc LRS $30, @DMBH +0569 02a0 8000 ANDCF $30, #0x8000 +056b 029c 0568 JZR 0x0568 +056d 02df RET + +// same function two times... strange ^^ +// waits for empty DSP mailbox +056e 26fc LRS $30, @DMBH +056f 02a0 8000 ANDCF $30, #0x8000 +0571 029c 056e JZR 0x056e +0573 02df RET + + +// Opcode_07() +0574 8100 CLR $30 +0575 8970 CLR.L $31 : $30, @$0 +0576 8e60 S40.L : $28, @$0 +0577 2ece SRS @DSMAH, $30 +0578 2ccf SRS @DSMAL, $28 +0579 16cd 0e44 SI @DSPA, #0x0e44 +057b 16c9 0000 SI @DSCR, #0x0000 +057d 8900 CLR $31 +057e 0d20 LRIS $29, #0x20 +057f 2dcb SRS @DSBL, $29 +0580 4c00 ADD $30, $31 +0581 1c80 MRR $4, $0 +0582 0080 0280 LRI $0, #0x0280 +0584 0081 0000 LRI $1, #0x0000 +0586 0082 0140 LRI $2, #0x0140 +0588 0083 0e44 LRI $3, #0x0e44 +058a 0a00 LRIS $26, #0x00 +058b 27c9 LRS $31, @DSCR +058c 03a0 0004 ANDCF $31, #0x0004 +058e 029c 058b JZR 0x058b // wait for DMA loop +0590 2ece SRS @DSMAH, $30 +0591 2ccf SRS @DSMAL, $28 +0592 16cd 0e54 SI @DSPA, #0x0e54 +0594 16c9 0000 SI @DSCR, #0x0000 +0596 16cb 0260 SI @DSBL, #0x0260 +0598 009f 00a0 LRI $31, #0x00a0 +059a 8f00 S16 + +059b 007f 05a4 BLOOP $31, 0x05a4 +059d 197e LRRI $30, @$3 +059e 1b1a SRRI @$0, $26 +059f 197c LRRI $28, @$3 +05a0 1b1a SRRI @$0, $26 +05a1 1b5e SRRI @$2, $30 +05a2 1b5c SRRI @$2, $28 +05a3 1b3e SRRI @$1, $30 +05a4 1b3c SRRI @$1, $28 + +05a5 1c04 MRR $0, $4 +05a6 029f 0068 JMP 0x0068 // Return to message loop. + + +// Decoder_ADPCM() +05a8 0082 0bb8 LRI $2, #0x0bb8 +05aa 195e LRRI $30, @$2 +05ab 2ed1 SRS @SampleFormat, $30 +05ac 195e LRRI $30, @$2 +05ad 2ed4 SRS @ACSAH, $30 +05ae 195e LRRI $30, @$2 +05af 2ed5 SRS @ACSAL, $30 +05b0 195e LRRI $30, @$2 +05b1 2ed6 SRS @ACEAH, $30 +05b2 195e LRRI $30, @$2 +05b3 2ed7 SRS @ACEAL, $30 +05b4 195e LRRI $30, @$2 +05b5 2ed8 SRS @ACCAH, $30 +05b6 195e LRRI $30, @$2 +05b7 2ed9 SRS @ACCAL, $30 +05b8 195e LRRI $30, @$2 +05b9 2ea0 SRS @COEF_A1_0, $30 +05ba 195e LRRI $30, @$2 +05bb 2ea1 SRS @COEF_A2_0, $30 +05bc 195e LRRI $30, @$2 +05bd 2ea2 SRS @COEF_A1_1, $30 +05be 195e LRRI $30, @$2 +05bf 2ea3 SRS @COEF_A2_1, $30 +05c0 195e LRRI $30, @$2 +05c1 2ea4 SRS @COEF_A1_2, $30 +05c2 195e LRRI $30, @$2 +05c3 2ea5 SRS @COEF_A2_2, $30 +05c4 195e LRRI $30, @$2 +05c5 2ea6 SRS @COEF_A1_3, $30 +05c6 195e LRRI $30, @$2 +05c7 2ea7 SRS @COEF_A2_3, $30 +05c8 195e LRRI $30, @$2 +05c9 2ea8 SRS @COEF_A1_4, $30 +05ca 195e LRRI $30, @$2 +05cb 2ea9 SRS @COEF_A2_4, $30 +05cc 195e LRRI $30, @$2 +05cd 2eaa SRS @COEF_A1_5, $30 +05ce 195e LRRI $30, @$2 +05cf 2eab SRS @COEF_A2_5, $30 +05d0 195e LRRI $30, @$2 +05d1 2eac SRS @COEF_A1_6, $30 +05d2 195e LRRI $30, @$2 +05d3 2ead SRS @COEF_A2_6, $30 +05d4 195e LRRI $30, @$2 +05d5 2eae SRS @COEF_A1_7, $30 +05d6 195e LRRI $30, @$2 +05d7 2eaf SRS @COEF_A2_7, $30 +05d8 195e LRRI $30, @$2 +05d9 2ede SRS @GAIN, $30 +05da 195e LRRI $30, @$2 +05db 2eda SRS @pred_scale, $30 +05dc 195e LRRI $30, @$2 +05dd 2edb SRS @yn1, $30 +05de 195e LRRI $30, @$2 +05df 2edc SRS @yn2, $30 +05e0 8c00 CLR15 +05e1 8a00 M2 +05e2 8e00 S40 +05e3 00d8 0e16 LR $24, @0x0e16 // get COEF Table +05e5 195b LRRI $27, @$2 +05e6 1959 LRRI $25, @$2 +05e7 8100 CLR $30 +05e8 195c LRRI $28, @$2 +05e9 0080 0e44 LRI $0, #0x0e44 +05eb 195f LRRI $31, @$2 +05ec 1b1f SRRI @$0, $31 +05ed 195f LRRI $31, @$2 +05ee 1b1f SRRI @$0, $31 +05ef 195f LRRI $31, @$2 +05f0 1b1f SRRI @$0, $31 +05f1 185f LRR $31, @$2 +05f2 1b1f SRRI @$0, $31 +05f3 6b00 MOVAX $31, $25 +05f4 1505 LSL $33, #0x05 +05f5 4d00 ADD $31, $30 +05f6 157e LSR $33, #0x3e +05f7 1c9f MRR $4, $31 +05f8 1cbd MRR $5, $29 +05f9 05e0 ADDIS $33, #0xe0 +05fa 9900 ASR16 $31 +05fb 7d00 NEG $31 +05fc 1cdd MRR $6, $29 +05fd 8900 CLR $31 +05fe 1fa5 MRR $29, $5 +05ff 1502 LSL $33, #0x02 +0600 1cbf MRR $5, $31 +0601 009a 01fc LRI $26, #0x01fc +0603 009e 0e44 LRI $30, #0x0e44 +0605 0081 ffdd LRI $1, #0xffdd +0607 0083 0d80 LRI $3, #0x0d80 +0609 0064 061a BLOOP $4, 0x061a +060b 1827 LRR $7, @$1 +060c 1b07 SRRI @$0, $7 +060d 4a00 ADDAX $30, $25 +060e 1ffc MRR $31, $28 +060f 1827 LRR $7, @$1 +0610 1b07 SRRI @$0, $7 +0611 1579 LSR $33, #0x39 +0612 3500 ANDR $31, $26 +0613 1827 LRR $7, @$1 +0614 1b07 SRRI @$0, $7 +0615 4100 ADDR $31, $24 +0616 1b7e SRRI @$3, $30 +0617 1827 LRR $7, @$1 +0618 1b07 SRRI @$0, $7 +0619 1b7f SRRI @$3, $31 +061a 0000 NOP // bloop 0609 +061b 0065 0620 BLOOP $5, 0x0620 +061d 1827 LRR $7, @$1 +061e 1b07 SRRI @$0, $7 +061f 0000 NOP +0620 0000 NOP // bloop 061b +0621 0007 DAR $3 +0622 187f LRR $31, @$3 +0623 0066 0629 BLOOP $6, 0x0629 +0625 4a3b ADDAX.S $30, $25 : @$3, $31 +0626 1ffc MRR $31, $28 +0627 1579 LSR $33, #0x39 +0628 3533 ANDR.S $31, $26 : @$3, $30 +0629 4100 ADDR $31, $24 // bloop 0623 +062a 1b7f SRRI @$3, $31 +062b 0004 DAR $0 +062c 189f LRRD $31, @$0 +062d 1adf SRRD @$2, $31 +062e 189f LRRD $31, @$0 +062f 1adf SRRD @$2, $31 +0630 189f LRRD $31, @$0 +0631 1adf SRRD @$2, $31 +0632 189f LRRD $31, @$0 +0633 1adf SRRD @$2, $31 +0634 1adc SRRD @$2, $28 +0635 0082 0bd2 LRI $2, #0x0bd2 +0637 27dc LRS $31, @yn2 +0638 1adf SRRD @$2, $31 +0639 27db LRS $31, @yn1 +063a 1adf SRRD @$2, $31 +063b 27da LRS $31, @pred_scale +063c 1adf SRRD @$2, $31 +063d 0082 0bbe LRI $2, #0x0bbe +063f 27d9 LRS $31, @ACCAL +0640 1adf SRRD @$2, $31 +0641 27d8 LRS $31, @ACCAH +0642 1adf SRRD @$2, $31 +0643 8f00 S16 +0644 00c1 0e42 LR $1, @0x0e42 +0646 0082 0d80 LRI $2, #0x0d80 +0648 1940 LRRI $0, @$2 +0649 1943 LRRI $3, @$2 +064a 80f0 NX.LDX : $25, $27, @$1 +064b b8c0 MULX.LDX $26, $27 : $24, $26, @$0 +064c 111f 0654 BLOOPI #0x1f, 0x0654 +064e a6f0 MULXMV.LDX $24, $25, $30 : $25, $27, @$1 +064f bcf0 MULXAC.LDX $26, $27, $30 : $25, $27, @$1 +0650 1940 LRRI $0, @$2 +0651 1943 LRRI $3, @$2 +0652 bcf0 MULXAC.LDX $26, $27, $30 : $25, $27, @$1 +0653 4ec0 ADDP.LDX $30 : $24, $26, @$0 +0654 b831 MULX.S $26, $27 : @$1, $30 +0655 a6f0 MULXMV.LDX $24, $25, $30 : $25, $27, @$1 +0656 bcf0 MULXAC.LDX $26, $27, $30 : $25, $27, @$1 +0657 bc00 MULXAC $26, $27, $30 +0658 4e00 ADDP $30 +0659 1b3e SRRI @$1, $30 +065a 00e1 0e42 SR @0x0e42, $1 +065c 02df RET + +// Decoder_PCM8() +065d 0082 0bb8 LRI $2, #0x0bb8 +065f 195e LRRI $30, @$2 +0660 2ed1 SRS @SampleFormat, $30 +0661 195e LRRI $30, @$2 +0662 2ed4 SRS @ACSAH, $30 +0663 195e LRRI $30, @$2 +0664 2ed5 SRS @ACSAL, $30 +0665 195e LRRI $30, @$2 +0666 2ed6 SRS @ACEAH, $30 +0667 195e LRRI $30, @$2 +0668 2ed7 SRS @ACEAL, $30 +0669 195e LRRI $30, @$2 +066a 2ed8 SRS @ACCAH, $30 +066b 195e LRRI $30, @$2 +066c 2ed9 SRS @ACCAL, $30 +066d 195e LRRI $30, @$2 +066e 2ea0 SRS @COEF_A1_0, $30 +066f 195e LRRI $30, @$2 +0670 2ea1 SRS @COEF_A2_0, $30 +0671 195e LRRI $30, @$2 +0672 2ea2 SRS @COEF_A1_1, $30 +0673 195e LRRI $30, @$2 +0674 2ea3 SRS @COEF_A2_1, $30 +0675 195e LRRI $30, @$2 +0676 2ea4 SRS @COEF_A1_2, $30 +0677 195e LRRI $30, @$2 +0678 2ea5 SRS @COEF_A2_2, $30 +0679 195e LRRI $30, @$2 +067a 2ea6 SRS @COEF_A1_3, $30 +067b 195e LRRI $30, @$2 +067c 2ea7 SRS @COEF_A2_3, $30 +067d 195e LRRI $30, @$2 +067e 2ea8 SRS @COEF_A1_4, $30 +067f 195e LRRI $30, @$2 +0680 2ea9 SRS @COEF_A2_4, $30 +0681 195e LRRI $30, @$2 +0682 2eaa SRS @COEF_A1_5, $30 +0683 195e LRRI $30, @$2 +0684 2eab SRS @COEF_A2_5, $30 +0685 195e LRRI $30, @$2 +0686 2eac SRS @COEF_A1_6, $30 +0687 195e LRRI $30, @$2 +0688 2ead SRS @COEF_A2_6, $30 +0689 195e LRRI $30, @$2 +068a 2eae SRS @COEF_A1_7, $30 +068b 195e LRRI $30, @$2 +068c 2eaf SRS @COEF_A2_7, $30 +068d 195e LRRI $30, @$2 +068e 2ede SRS @GAIN, $30 +068f 195e LRRI $30, @$2 +0690 2eda SRS @pred_scale, $30 +0691 195e LRRI $30, @$2 +0692 2edb SRS @yn1, $30 +0693 195e LRRI $30, @$2 +0694 2edc SRS @yn2, $30 +0695 8c00 CLR15 +0696 8a00 M2 +0697 8e00 S40 +0698 195b LRRI $27, @$2 +0699 1959 LRRI $25, @$2 +069a 8100 CLR $30 +069b 195c LRRI $28, @$2 +069c 0080 0e44 LRI $0, #0x0e44 +069e 195f LRRI $31, @$2 +069f 195f LRRI $31, @$2 +06a0 195f LRRI $31, @$2 +06a1 1b1f SRRI @$0, $31 +06a2 185f LRR $31, @$2 +06a3 1b1f SRRI @$0, $31 +06a4 6b00 MOVAX $31, $25 +06a5 1505 LSL $33, #0x05 +06a6 4d00 ADD $31, $30 +06a7 157e LSR $33, #0x3e +06a8 1c9f MRR $4, $31 +06a9 1cbd MRR $5, $29 +06aa 05e0 ADDIS $33, #0xe0 +06ab 9900 ASR16 $31 +06ac 7d00 NEG $31 +06ad 1cdd MRR $6, $29 +06ae 8900 CLR $31 +06af 1fa5 MRR $29, $5 +06b0 1502 LSL $33, #0x02 +06b1 1cbf MRR $5, $31 +06b2 009a 01fc LRI $26, #0x01fc +06b4 009e 0e45 LRI $30, #0x0e45 +06b6 0081 ffdd LRI $1, #0xffdd +06b8 0083 0d80 LRI $3, #0x0d80 +06ba 0064 06cb BLOOP $4, 0x06cb +06bc 1827 LRR $7, @$1 +06bd 1b07 SRRI @$0, $7 +06be 4a00 ADDAX $30, $25 +06bf 1b7e SRRI @$3, $30 +06c0 1827 LRR $7, @$1 +06c1 1b07 SRRI @$0, $7 +06c2 1b7c SRRI @$3, $28 +06c3 0000 NOP +06c4 1827 LRR $7, @$1 +06c5 1b07 SRRI @$0, $7 +06c6 0000 NOP +06c7 0000 NOP +06c8 1827 LRR $7, @$1 +06c9 1b07 SRRI @$0, $7 +06ca 0000 NOP +06cb 0000 NOP +06cc 0065 06d1 BLOOP $5, 0x06d1 +06ce 1827 LRR $7, @$1 +06cf 1b07 SRRI @$0, $7 +06d0 0000 NOP +06d1 0000 NOP +06d2 0066 06d6 BLOOP $6, 0x06d6 +06d4 4a00 ADDAX $30, $25 +06d5 1b7e SRRI @$3, $30 +06d6 1b7c SRRI @$3, $28 +06d7 0004 DAR $0 +06d8 189f LRRD $31, @$0 +06d9 1adf SRRD @$2, $31 +06da 189f LRRD $31, @$0 +06db 1adf SRRD @$2, $31 +06dc 189f LRRD $31, @$0 +06dd 1adf SRRD @$2, $31 +06de 189f LRRD $31, @$0 +06df 1adf SRRD @$2, $31 +06e0 1adc SRRD @$2, $28 +06e1 0082 0bd2 LRI $2, #0x0bd2 +06e3 27dc LRS $31, @yn2 +06e4 1adf SRRD @$2, $31 +06e5 27db LRS $31, @yn1 +06e6 1adf SRRD @$2, $31 +06e7 27da LRS $31, @pred_scale +06e8 1adf SRRD @$2, $31 +06e9 0082 0bbe LRI $2, #0x0bbe +06eb 27d9 LRS $31, @ACCAL +06ec 1adf SRRD @$2, $31 +06ed 27d8 LRS $31, @ACCAH +06ee 1adf SRRD @$2, $31 +06ef 8d00 SET15 +06f0 8b00 M0 +06f1 8f00 S16 +06f2 00c1 0e42 LR $1, @0x0e42 +06f4 0082 0d80 LRI $2, #0x0d80 +06f6 8100 CLR $30 +06f7 1120 0703 BLOOPI #0x20, 0x0703 +06f9 8900 CLR $31 +06fa 1940 LRRI $0, @$2 +06fb 189e LRRD $30, @$0 +06fc 181b LRR $27, @$0 +06fd 199a LRRN $26, @$0 +06fe 5400 SUBR $30, $26 +06ff 1f5e MRR $26, $30 +0700 1959 LRRI $25, @$2 +0701 b000 MULX $26, $25 +0702 fb00 ADDPAXZ $31, $27 +0703 8139 CLR.S $30 : @$1, $31 +0704 00e1 0e42 SR @0x0e42, $1 +0706 02df RET + +// Decoder_PCM16() +0707 0082 0bb8 LRI $2, #0x0bb8 +0709 195e LRRI $30, @$2 +070a 2ed1 SRS @SampleFormat, $30 +070b 195e LRRI $30, @$2 +070c 2ed4 SRS @ACSAH, $30 +070d 195e LRRI $30, @$2 +070e 2ed5 SRS @ACSAL, $30 +070f 195e LRRI $30, @$2 +0710 2ed6 SRS @ACEAH, $30 +0711 195e LRRI $30, @$2 +0712 2ed7 SRS @ACEAL, $30 +0713 195e LRRI $30, @$2 +0714 2ed8 SRS @ACCAH, $30 +0715 195e LRRI $30, @$2 +0716 2ed9 SRS @ACCAL, $30 +0717 195e LRRI $30, @$2 +0718 2ea0 SRS @COEF_A1_0, $30 +0719 195e LRRI $30, @$2 +071a 2ea1 SRS @COEF_A2_0, $30 +071b 195e LRRI $30, @$2 +071c 2ea2 SRS @COEF_A1_1, $30 +071d 195e LRRI $30, @$2 +071e 2ea3 SRS @COEF_A2_1, $30 +071f 195e LRRI $30, @$2 +0720 2ea4 SRS @COEF_A1_2, $30 +0721 195e LRRI $30, @$2 +0722 2ea5 SRS @COEF_A2_2, $30 +0723 195e LRRI $30, @$2 +0724 2ea6 SRS @COEF_A1_3, $30 +0725 195e LRRI $30, @$2 +0726 2ea7 SRS @COEF_A2_3, $30 +0727 195e LRRI $30, @$2 +0728 2ea8 SRS @COEF_A1_4, $30 +0729 195e LRRI $30, @$2 +072a 2ea9 SRS @COEF_A2_4, $30 +072b 195e LRRI $30, @$2 +072c 2eaa SRS @COEF_A1_5, $30 +072d 195e LRRI $30, @$2 +072e 2eab SRS @COEF_A2_5, $30 +072f 195e LRRI $30, @$2 +0730 2eac SRS @COEF_A1_6, $30 +0731 195e LRRI $30, @$2 +0732 2ead SRS @COEF_A2_6, $30 +0733 195e LRRI $30, @$2 +0734 2eae SRS @COEF_A1_7, $30 +0735 195e LRRI $30, @$2 +0736 2eaf SRS @COEF_A2_7, $30 +0737 195e LRRI $30, @$2 +0738 2ede SRS @GAIN, $30 +0739 195e LRRI $30, @$2 +073a 2eda SRS @pred_scale, $30 +073b 195e LRRI $30, @$2 +073c 2edb SRS @yn1, $30 +073d 195e LRRI $30, @$2 +073e 2edc SRS @yn2, $30 +073f 00c0 0e42 LR $0, @0x0e42 +0741 0081 ffdd LRI $1, #0xffdd +0743 1120 0748 BLOOPI #0x20, 0x0748 +0745 1824 LRR $4, @$1 +0746 1b04 SRRI @$0, $4 +0747 0000 NOP +0748 0000 NOP +0749 00e0 0e42 SR @0x0e42, $0 +074b 0082 0bd9 LRI $2, #0x0bd9 +074d 0004 DAR $0 +074e 189f LRRD $31, @$0 +074f 1adf SRRD @$2, $31 +0750 189f LRRD $31, @$0 +0751 1adf SRRD @$2, $31 +0752 189f LRRD $31, @$0 +0753 1adf SRRD @$2, $31 +0754 189f LRRD $31, @$0 +0755 1adf SRRD @$2, $31 +0756 8900 CLR $31 +0757 1adc SRRD @$2, $28 +0758 27dc LRS $31, @yn2 +0759 00ff 0bd2 SR @0x0bd2, $31 +075b 27db LRS $31, @yn1 +075c 00ff 0bd1 SR @0x0bd1, $31 +075e 27da LRS $31, @pred_scale +075f 00ff 0bd0 SR @0x0bd0, $31 +0761 27d9 LRS $31, @ACCAL +0762 00ff 0bbe SR @0x0bbe, $31 +0764 27d8 LRS $31, @ACCAH +0765 00ff 0bbd SR @0x0bbd, $31 +0767 02df RET + +//////////////////////////////////////////////// +// +// Mixer functions - calls ROM functions +// +//////////////////////////////////////////////// + +// fn0 +// this mixer is used by CrazyTaxi (at least at the beginning) +// per.aps for mono sample?? + +0768 00c0 0e40 LR $0, @0x0e40 // PB->PBInitialTimeDelay->offsetLeft +076a 0081 0b89 LRI $1, #0x0b89 // PB->Mixer... struct offset +076c 00c2 0e08 LR $2, @0x0e08 // Buffer1 (0x0000 all the time - Left Channel) +076e 1c62 MRR $3, $2 // Buffer2 +076f 00c4 0e41 LR $4, @0x0e41 // PB->PBInitialTimeDelay->offsetRight +0771 00c5 0e09 LR $5, @0x0e09 // Buffer3 (0x0140 all the time - Right Channel) +0773 02bf 80e7 CALL 0x80e7 // Call ROM mixer function +0775 00f8 0ba9 SR @0x0ba9, $24 // mixer return value1 +0777 00fb 0bac SR @0x0bac, $27 // mixer return value2 +0779 02df RET + +// fn1 +077a 00c0 0e40 LR $0, @0x0e40 +077c 0081 0b89 LRI $1, #0x0b89 // PB mixer settings // PB mixer settings +077e 00c2 0e08 LR $2, @0x0e08 +0780 1c62 MRR $3, $2 +0781 00c4 0e41 LR $4, @0x0e41 +0783 00c5 0e09 LR $5, @0x0e09 +0785 02bf 80e7 CALL 0x80e7 // Call ROM mixer function +0787 00f8 0ba9 SR @0x0ba9, $24 +0789 00fb 0bac SR @0x0bac, $27 +078b 00c0 0e40 LR $0, @0x0e40 +078d 0081 0b8d LRI $1, #0x0b8d +078f 00c2 0e0b LR $2, @0x0e0b +0791 1c62 MRR $3, $2 +0792 00c4 0e41 LR $4, @0x0e41 +0794 00c5 0e0c LR $5, @0x0e0c +0796 02bf 80e7 CALL 0x80e7 // Call ROM mixer function +0798 00f8 0baa SR @0x0baa, $24 +079a 00fb 0bad SR @0x0bad, $27 +079c 02df RET + +// fn2 +079d 00c0 0e40 LR $0, @0x0e40 +079f 0081 0b89 LRI $1, #0x0b89 // PB mixer settings +07a1 00c2 0e08 LR $2, @0x0e08 +07a3 1c62 MRR $3, $2 +07a4 00c4 0e41 LR $4, @0x0e41 +07a6 00c5 0e09 LR $5, @0x0e09 +07a8 02bf 80e7 CALL 0x80e7 // Call ROM mixer function +07aa 00f8 0ba9 SR @0x0ba9, $24 +07ac 00fb 0bac SR @0x0bac, $27 +07ae 00c0 0e40 LR $0, @0x0e40 +07b0 0081 0b91 LRI $1, #0x0b91 +07b2 00c2 0e0e LR $2, @0x0e0e +07b4 1c62 MRR $3, $2 +07b5 00c4 0e41 LR $4, @0x0e41 +07b7 00c5 0e0f LR $5, @0x0e0f +07b9 02bf 80e7 CALL 0x80e7 // Call ROM mixer function +07bb 00f8 0bab SR @0x0bab, $24 +07bd 00fb 0bae SR @0x0bae, $27 +07bf 02df RET + +// fn3 +07c0 00c0 0e40 LR $0, @0x0e40 +07c2 0081 0b89 LRI $1, #0x0b89 // PB mixer settings // PB mixer settings +07c4 00c2 0e08 LR $2, @0x0e08 +07c6 1c62 MRR $3, $2 +07c7 00c4 0e41 LR $4, @0x0e41 +07c9 00c5 0e09 LR $5, @0x0e09 +07cb 02bf 80e7 CALL 0x80e7 // Call ROM mixer function +07cd 00f8 0ba9 SR @0x0ba9, $24 +07cf 00fb 0bac SR @0x0bac, $27 +07d1 00c0 0e40 LR $0, @0x0e40 +07d3 0081 0b8d LRI $1, #0x0b8d +07d5 00c2 0e0b LR $2, @0x0e0b +07d7 1c62 MRR $3, $2 +07d8 00c4 0e41 LR $4, @0x0e41 +07da 00c5 0e0c LR $5, @0x0e0c +07dc 02bf 80e7 CALL 0x80e7 // Call ROM mixer function +07de 00f8 0baa SR @0x0baa, $24 +07e0 00fb 0bad SR @0x0bad, $27 +07e2 00c0 0e40 LR $0, @0x0e40 +07e4 0081 0b91 LRI $1, #0x0b91 +07e6 00c2 0e0e LR $2, @0x0e0e +07e8 1c62 MRR $3, $2 +07e9 00c4 0e41 LR $4, @0x0e41 +07eb 00c5 0e0f LR $5, @0x0e0f +07ed 02bf 80e7 CALL 0x80e7 // Call ROM mixer function +07ef 00f8 0bab SR @0x0bab, $24 +07f1 00fb 0bae SR @0x0bae, $27 +07f3 02df RET + +// fn4 +07f4 00c0 0e40 LR $0, @0x0e40 +07f6 0081 0b89 LRI $1, #0x0b89 // PB mixer settings +07f8 00c2 0e08 LR $2, @0x0e08 +07fa 1c62 MRR $3, $2 +07fb 00c4 0e41 LR $4, @0x0e41 +07fd 00c5 0e09 LR $5, @0x0e09 +07ff 02bf 80e7 CALL 0x80e7 // Call ROM mixer function +0801 00f8 0ba9 SR @0x0ba9, $24 +0803 00fb 0bac SR @0x0bac, $27 +0805 00c0 0e43 LR $0, @0x0e43 +0807 0081 0b97 LRI $1, #0x0b97 +0809 00c2 0e0a LR $2, @0x0e0a +080b 1c62 MRR $3, $2 +080c 02bf 81f9 CALL 0x81f9 // Call second ROM mixer function +080e 00f8 0baf SR @0x0baf, $24 +0810 02df RET + +// xxxx +0811 00c0 0e40 LR $0, @0x0e40 +0813 0081 0b89 LRI $1, #0x0b89 // PB mixer settings +0815 00c2 0e08 LR $2, @0x0e08 +0817 1c62 MRR $3, $2 +0818 00c4 0e41 LR $4, @0x0e41 +081a 00c5 0e09 LR $5, @0x0e09 +081c 02bf 80e7 CALL 0x80e7 // Call ROM mixer function +081e 00f8 0ba9 SR @0x0ba9, $24 +0820 00fb 0bac SR @0x0bac, $27 +0822 00c0 0e40 LR $0, @0x0e40 +0824 0081 0b8d LRI $1, #0x0b8d +0826 00c2 0e0b LR $2, @0x0e0b +0828 1c62 MRR $3, $2 +0829 00c4 0e41 LR $4, @0x0e41 +082b 00c5 0e0c LR $5, @0x0e0c +082d 02bf 80e7 CALL 0x80e7 // Call ROM mixer function +082f 00f8 0baa SR @0x0baa, $24 +0831 00fb 0bad SR @0x0bad, $27 +0833 00c0 0e43 LR $0, @0x0e43 +0835 0081 0b97 LRI $1, #0x0b97 +0837 00c2 0e0a LR $2, @0x0e0a +0839 1c62 MRR $3, $2 +083a 1c80 MRR $4, $0 +083b 00c5 0e0d LR $5, @0x0e0d +083d 02bf 80e7 CALL 0x80e7 // Call ROM mixer function +083f 00f8 0baf SR @0x0baf, $24 +0841 00fb 0bb0 SR @0x0bb0, $27 +0843 02df RET + + + +0844 00c0 0e40 LR $0, @0x0e40 +0846 0081 0b89 LRI $1, #0x0b89 // PB mixer settings +0848 00c2 0e08 LR $2, @0x0e08 +084a 1c62 MRR $3, $2 +084b 00c4 0e41 LR $4, @0x0e41 +084d 00c5 0e09 LR $5, @0x0e09 +084f 02bf 80e7 CALL 0x80e7 // Call ROM mixer function +0851 00f8 0ba9 SR @0x0ba9, $24 +0853 00fb 0bac SR @0x0bac, $27 +0855 00c0 0e40 LR $0, @0x0e40 +0857 0081 0b91 LRI $1, #0x0b91 +0859 00c2 0e0e LR $2, @0x0e0e +085b 1c62 MRR $3, $2 +085c 00c4 0e41 LR $4, @0x0e41 +085e 00c5 0e0f LR $5, @0x0e0f +0860 02bf 80e7 CALL 0x80e7 // Call ROM mixer function +0862 00f8 0bab SR @0x0bab, $24 +0864 00fb 0bae SR @0x0bae, $27 +0866 00c0 0e43 LR $0, @0x0e43 +0868 0081 0b95 LRI $1, #0x0b95 +086a 00c2 0e10 LR $2, @0x0e10 +086c 1c62 MRR $3, $2 +086d 1c80 MRR $4, $0 +086e 00c5 0e0a LR $5, @0x0e0a +0870 02bf 80e7 CALL 0x80e7 // Call ROM mixer function +0872 00f8 0bb1 SR @0x0bb1, $24 +0874 00fb 0baf SR @0x0baf, $27 +0876 02df RET + + + +0877 00c0 0e40 LR $0, @0x0e40 +0879 0081 0b89 LRI $1, #0x0b89 // PB mixer settings +087b 00c2 0e08 LR $2, @0x0e08 +087d 1c62 MRR $3, $2 +087e 00c4 0e41 LR $4, @0x0e41 +0880 00c5 0e09 LR $5, @0x0e09 +0882 02bf 80e7 CALL 0x80e7 // Call ROM mixer function +0884 00f8 0ba9 SR @0x0ba9, $24 +0886 00fb 0bac SR @0x0bac, $27 +0888 00c0 0e40 LR $0, @0x0e40 +088a 0081 0b8d LRI $1, #0x0b8d +088c 00c2 0e0b LR $2, @0x0e0b +088e 1c62 MRR $3, $2 +088f 00c4 0e41 LR $4, @0x0e41 +0891 00c5 0e0c LR $5, @0x0e0c +0893 02bf 80e7 CALL 0x80e7 // Call ROM mixer function +0895 00f8 0baa SR @0x0baa, $24 +0897 00fb 0bad SR @0x0bad, $27 +0899 00c0 0e40 LR $0, @0x0e40 +089b 0081 0b91 LRI $1, #0x0b91 +089d 00c2 0e0e LR $2, @0x0e0e +089f 1c62 MRR $3, $2 +08a0 00c4 0e41 LR $4, @0x0e41 +08a2 00c5 0e0f LR $5, @0x0e0f +08a4 02bf 80e7 CALL 0x80e7 // Call ROM mixer function +08a6 00f8 0bab SR @0x0bab, $24 +08a8 00fb 0bae SR @0x0bae, $27 +08aa 00c0 0e43 LR $0, @0x0e43 +08ac 0081 0b97 LRI $1, #0x0b97 +08ae 00c2 0e0a LR $2, @0x0e0a +08b0 1c62 MRR $3, $2 +08b1 1c80 MRR $4, $0 +08b2 00c5 0e0d LR $5, @0x0e0d +08b4 02bf 80e7 CALL 0x80e7 // Call ROM mixer function +08b6 00f8 0baf SR @0x0baf, $24 +08b8 00fb 0bb0 SR @0x0bb0, $27 +08ba 00c0 0e43 LR $0, @0x0e43 +08bc 0081 0b95 LRI $1, #0x0b95 +08be 00c2 0e10 LR $2, @0x0e10 +08c0 1c62 MRR $3, $2 +08c1 02bf 81f9 CALL 0x81f9 // Call second ROM mixer function +08c3 00f8 0bb1 SR @0x0bb1, $24 +08c5 02df RET + + + +08c6 00c0 0e40 LR $0, @0x0e40 +08c8 0081 0b89 LRI $1, #0x0b89 // PB mixer settings +08ca 00c2 0e08 LR $2, @0x0e08 +08cc 0083 0e44 LRI $3, #0x0e44 +08ce 00c4 0e41 LR $4, @0x0e41 +08d0 00c5 0e09 LR $5, @0x0e09 +08d2 02bf 8282 CALL 0x8282 // Call third ROM mixer function +08d4 00f8 0ba9 SR @0x0ba9, $24 +08d6 00fb 0bac SR @0x0bac, $27 +08d8 02df RET + + + +08d9 00c0 0e40 LR $0, @0x0e40 +08db 0081 0b89 LRI $1, #0x0b89 // PB mixer settings +08dd 00c2 0e08 LR $2, @0x0e08 +08df 0083 0e44 LRI $3, #0x0e44 +08e1 00c4 0e41 LR $4, @0x0e41 +08e3 00c5 0e09 LR $5, @0x0e09 +08e5 02bf 8282 CALL 0x8282 // Call third ROM mixer function +08e7 00f8 0ba9 SR @0x0ba9, $24 +08e9 00fb 0bac SR @0x0bac, $27 +08eb 00c0 0e40 LR $0, @0x0e40 +08ed 0081 0b8d LRI $1, #0x0b8d // aux stuff +08ef 00c2 0e0b LR $2, @0x0e0b +08f1 0083 0e44 LRI $3, #0x0e44 +08f3 00c4 0e41 LR $4, @0x0e41 +08f5 00c5 0e0c LR $5, @0x0e0c +08f7 02bf 8282 CALL 0x8282 // Call third ROM mixer function +08f9 00f8 0baa SR @0x0baa, $24 +08fb 00fb 0bad SR @0x0bad, $27 +08fd 02df RET + + + + +08fe 00c0 0e40 LR $0, @0x0e40 +0900 0081 0b89 LRI $1, #0x0b89 // PB mixer settings +0902 00c2 0e08 LR $2, @0x0e08 +0904 0083 0e44 LRI $3, #0x0e44 +0906 00c4 0e41 LR $4, @0x0e41 +0908 00c5 0e09 LR $5, @0x0e09 +090a 02bf 8282 CALL 0x8282 // Call third ROM mixer function +090c 00f8 0ba9 SR @0x0ba9, $24 +090e 00fb 0bac SR @0x0bac, $27 +0910 00c0 0e40 LR $0, @0x0e40 +0912 0081 0b91 LRI $1, #0x0b91 // aux stuff +0914 00c2 0e0e LR $2, @0x0e0e +0916 0083 0e44 LRI $3, #0x0e44 +0918 00c4 0e41 LR $4, @0x0e41 +091a 00c5 0e0f LR $5, @0x0e0f +091c 02bf 8282 CALL 0x8282 // Call third ROM mixer function +091e 00f8 0bab SR @0x0bab, $24 +0920 00fb 0bae SR @0x0bae, $27 +0922 02df RET + + + +0923 00c0 0e40 LR $0, @0x0e40 +0925 0081 0b89 LRI $1, #0x0b89 // PB mixer settings +0927 00c2 0e08 LR $2, @0x0e08 +0929 0083 0e44 LRI $3, #0x0e44 +092b 00c4 0e41 LR $4, @0x0e41 +092d 00c5 0e09 LR $5, @0x0e09 +092f 02bf 8282 CALL 0x8282 // Call third ROM mixer function +0931 00f8 0ba9 SR @0x0ba9, $24 +0933 00fb 0bac SR @0x0bac, $27 +0935 00c0 0e40 LR $0, @0x0e40 +0937 0081 0b8d LRI $1, #0x0b8d +0939 00c2 0e0b LR $2, @0x0e0b +093b 0083 0e44 LRI $3, #0x0e44 +093d 00c4 0e41 LR $4, @0x0e41 +093f 00c5 0e0c LR $5, @0x0e0c +0941 02bf 8282 CALL 0x8282 // Call third ROM mixer function +0943 00f8 0baa SR @0x0baa, $24 +0945 00fb 0bad SR @0x0bad, $27 +0947 00c0 0e40 LR $0, @0x0e40 +0949 0081 0b91 LRI $1, #0x0b91 +094b 00c2 0e0e LR $2, @0x0e0e +094d 0083 0e44 LRI $3, #0x0e44 +094f 00c4 0e41 LR $4, @0x0e41 +0951 00c5 0e0f LR $5, @0x0e0f +0953 02bf 8282 CALL 0x8282 // Call third ROM mixer function +0955 00f8 0bab SR @0x0bab, $24 +0957 00fb 0bae SR @0x0bae, $27 +0959 02df RET + + + + +095a 00c0 0e40 LR $0, @0x0e40 +095c 0081 0b89 LRI $1, #0x0b89 // PB mixer settings +095e 00c2 0e08 LR $2, @0x0e08 +0960 0083 0e44 LRI $3, #0x0e44 +0962 00c4 0e41 LR $4, @0x0e41 +0964 00c5 0e09 LR $5, @0x0e09 +0966 02bf 8282 CALL 0x8282 // Call third ROM mixer function +0968 00f8 0ba9 SR @0x0ba9, $24 +096a 00fb 0bac SR @0x0bac, $27 +096c 00c0 0e43 LR $0, @0x0e43 +096e 0081 0b97 LRI $1, #0x0b97 +0970 00c2 0e0a LR $2, @0x0e0a +0972 0083 0e44 LRI $3, #0x0e44 +0974 02bf 845d CALL 0x845d +0976 00f8 0baf SR @0x0baf, $24 +0978 02df RET + + + +0979 00c0 0e40 LR $0, @0x0e40 +097b 0081 0b89 LRI $1, #0x0b89 // PB mixer settings +097d 00c2 0e08 LR $2, @0x0e08 +097f 0083 0e44 LRI $3, #0x0e44 +0981 00c4 0e41 LR $4, @0x0e41 +0983 00c5 0e09 LR $5, @0x0e09 +0985 02bf 8282 CALL 0x8282 // Call third ROM mixer function +0987 00f8 0ba9 SR @0x0ba9, $24 +0989 00fb 0bac SR @0x0bac, $27 +098b 00c0 0e40 LR $0, @0x0e40 +098d 0081 0b8d LRI $1, #0x0b8d +098f 00c2 0e0b LR $2, @0x0e0b +0991 0083 0e44 LRI $3, #0x0e44 +0993 00c4 0e41 LR $4, @0x0e41 +0995 00c5 0e0c LR $5, @0x0e0c +0997 02bf 8282 CALL 0x8282 // Call third ROM mixer function +0999 00f8 0baa SR @0x0baa, $24 +099b 00fb 0bad SR @0x0bad, $27 +099d 00c0 0e43 LR $0, @0x0e43 +099f 0081 0b97 LRI $1, #0x0b97 +09a1 00c2 0e0a LR $2, @0x0e0a +09a3 0083 0e44 LRI $3, #0x0e44 +09a5 1c80 MRR $4, $0 +09a6 00c5 0e0d LR $5, @0x0e0d +09a8 02bf 8282 CALL 0x8282 // Call third ROM mixer function +09aa 00f8 0baf SR @0x0baf, $24 +09ac 00fb 0bb0 SR @0x0bb0, $27 +09ae 02df RET + + + +09af 00c0 0e40 LR $0, @0x0e40 +09b1 0081 0b89 LRI $1, #0x0b89 // PB mixer settings +09b3 00c2 0e08 LR $2, @0x0e08 +09b5 0083 0e44 LRI $3, #0x0e44 +09b7 00c4 0e41 LR $4, @0x0e41 +09b9 00c5 0e09 LR $5, @0x0e09 +09bb 02bf 8282 CALL 0x8282 // Call third ROM mixer function +09bd 00f8 0ba9 SR @0x0ba9, $24 +09bf 00fb 0bac SR @0x0bac, $27 +09c1 00c0 0e40 LR $0, @0x0e40 +09c3 0081 0b91 LRI $1, #0x0b91 +09c5 00c2 0e0e LR $2, @0x0e0e +09c7 0083 0e44 LRI $3, #0x0e44 +09c9 00c4 0e41 LR $4, @0x0e41 +09cb 00c5 0e0f LR $5, @0x0e0f +09cd 02bf 8282 CALL 0x8282 // Call third ROM mixer function +09cf 00f8 0bab SR @0x0bab, $24 +09d1 00fb 0bae SR @0x0bae, $27 +09d3 00c0 0e43 LR $0, @0x0e43 +09d5 0081 0b95 LRI $1, #0x0b95 +09d7 00c2 0e10 LR $2, @0x0e10 +09d9 0083 0e44 LRI $3, #0x0e44 +09db 1c80 MRR $4, $0 +09dc 00c5 0e0a LR $5, @0x0e0a +09de 02bf 8282 CALL 0x8282 // Call third ROM mixer function +09e0 00f8 0bb1 SR @0x0bb1, $24 +09e2 00fb 0baf SR @0x0baf, $27 +09e4 02df RET + + + +09e5 00c0 0e40 LR $0, @0x0e40 +09e7 0081 0b89 LRI $1, #0x0b89 // PB mixer settings +09e9 00c2 0e08 LR $2, @0x0e08 +09eb 0083 0e44 LRI $3, #0x0e44 +09ed 00c4 0e41 LR $4, @0x0e41 +09ef 00c5 0e09 LR $5, @0x0e09 +09f1 02bf 8282 CALL 0x8282 // Call third ROM mixer function +09f3 00f8 0ba9 SR @0x0ba9, $24 +09f5 00fb 0bac SR @0x0bac, $27 +09f7 00c0 0e40 LR $0, @0x0e40 +09f9 0081 0b8d LRI $1, #0x0b8d +09fb 00c2 0e0b LR $2, @0x0e0b +09fd 0083 0e44 LRI $3, #0x0e44 +09ff 00c0 0e41 LR $0, @0x0e41 +0a01 00c5 0e0c LR $5, @0x0e0c +0a03 02bf 8282 CALL 0x8282 // Call third ROM mixer function +0a05 00f8 0baa SR @0x0baa, $24 +0a07 00fb 0bad SR @0x0bad, $27 +0a09 00c0 0e40 LR $0, @0x0e40 +0a0b 0081 0b91 LRI $1, #0x0b91 +0a0d 00c2 0e0e LR $2, @0x0e0e +0a0f 0083 0e44 LRI $3, #0x0e44 +0a11 00c4 0e41 LR $4, @0x0e41 +0a13 00c5 0e0f LR $5, @0x0e0f +0a15 02bf 8282 CALL 0x8282 // Call third ROM mixer function +0a17 00f8 0bab SR @0x0bab, $24 +0a19 00fb 0bae SR @0x0bae, $27 +0a1b 00c0 0e43 LR $0, @0x0e43 +0a1d 0081 0b97 LRI $1, #0x0b97 +0a1f 00c2 0e0a LR $2, @0x0e0a +0a21 0083 0e44 LRI $3, #0x0e44 +0a23 1c80 MRR $4, $0 +0a24 00c5 0e0d LR $5, @0x0e0d +0a26 02bf 8282 CALL 0x8282 // Call third ROM mixer function +0a28 00f8 0baf SR @0x0baf, $24 +0a2a 00fb 0bb0 SR @0x0bb0, $27 +0a2c 00c0 0e43 LR $0, @0x0e43 +0a2e 0081 0b95 LRI $1, #0x0b95 +0a30 00c2 0e10 LR $2, @0x0e10 +0a32 0083 0e44 LRI $3, #0x0e44 +0a34 02bf 845d CALL 0x845d +0a36 00f8 0bb1 SR @0x0bb1, $24 +0a38 02df RET + + + + +0a39 00c0 0e40 LR $0, @0x0e40 +0a3b 0081 0b89 LRI $1, #0x0b89 // PB mixer settings +0a3d 00c2 0e08 LR $2, @0x0e08 +0a3f 1c62 MRR $3, $2 +0a40 00c4 0e41 LR $4, @0x0e41 +0a42 00c5 0e09 LR $5, @0x0e09 +0a44 02bf 80e7 CALL 0x80e7 // Call ROM mixer function +0a46 00f8 0ba9 SR @0x0ba9, $24 +0a48 00fb 0bac SR @0x0bac, $27 +0a4a 00c0 0e43 LR $0, @0x0e43 +0a4c 0081 0b91 LRI $1, #0x0b91 +0a4e 00c2 0e0e LR $2, @0x0e0e +0a50 1c62 MRR $3, $2 +0a51 1c80 MRR $4, $0 +0a52 00c5 0e0f LR $5, @0x0e0f +0a54 02bf 80e7 CALL 0x80e7 // Call ROM mixer function +0a56 00f8 0bab SR @0x0bab, $24 +0a58 00fb 0bae SR @0x0bae, $27 +0a5a 02df RET + + +0a5b 00c0 0e40 LR $0, @0x0e40 +0a5d 0081 0b89 LRI $1, #0x0b89 // PB mixer settings +0a5f 00c2 0e08 LR $2, @0x0e08 +0a61 1c62 MRR $3, $2 +0a62 00c4 0e41 LR $4, @0x0e41 +0a64 00c5 0e09 LR $5, @0x0e09 +0a66 02bf 80e7 CALL 0x80e7 // Call ROM mixer function +0a68 00f8 0ba9 SR @0x0ba9, $24 +0a6a 00fb 0bac SR @0x0bac, $27 +0a6c 00c0 0e43 LR $0, @0x0e43 +0a6e 0081 0b91 LRI $1, #0x0b91 +0a70 00c2 0e0e LR $2, @0x0e0e +0a72 1c62 MRR $3, $2 +0a73 1c80 MRR $4, $0 +0a74 00c5 0e0f LR $5, @0x0e0f +0a76 02bf 80e7 CALL 0x80e7 // Call ROM mixer function +0a78 00f8 0bab SR @0x0bab, $24 +0a7a 00fb 0bae SR @0x0bae, $27 +0a7c 00c0 0e40 LR $0, @0x0e40 +0a7e 0081 0b8d LRI $1, #0x0b8d +0a80 00c2 0e0b LR $2, @0x0e0b +0a82 1c62 MRR $3, $2 +0a83 00c4 0e41 LR $4, @0x0e41 +0a85 00c5 0e0c LR $5, @0x0e0c +0a87 02bf 80e7 CALL 0x80e7 // Call ROM mixer function +0a89 00f8 0baa SR @0x0baa, $24 +0a8b 00fb 0bad SR @0x0bad, $27 +0a8d 00c0 0e43 LR $0, @0x0e43 +0a8f 0081 0b99 LRI $1, #0x0b99 +0a91 00c2 0e0d LR $2, @0x0e0d +0a93 1c62 MRR $3, $2 +0a94 02bf 81f9 CALL 0x81f9 // Call second ROM mixer function +0a96 00f8 0bb0 SR @0x0bb0, $24 +0a98 02df RET + + + +0a99 00c0 0e40 LR $0, @0x0e40 +0a9b 0081 0b89 LRI $1, #0x0b89 // PB mixer settings +0a9d 00c2 0e08 LR $2, @0x0e08 +0a9f 0083 0e44 LRI $3, #0x0e44 +0aa1 00c4 0e41 LR $4, @0x0e41 +0aa3 00c5 0e09 LR $5, @0x0e09 +0aa5 02bf 8282 CALL 0x8282 // Call third ROM mixer function +0aa7 00f8 0ba9 SR @0x0ba9, $24 +0aa9 00fb 0bac SR @0x0bac, $27 +0aab 00c0 0e43 LR $0, @0x0e43 +0aad 0081 0b91 LRI $1, #0x0b91 +0aaf 00c2 0e0e LR $2, @0x0e0e +0ab1 0083 0e44 LRI $3, #0x0e44 +0ab3 1c80 MRR $4, $0 +0ab4 00c5 0e0f LR $5, @0x0e0f +0ab6 02bf 8282 CALL 0x8282 // Call third ROM mixer function +0ab8 00f8 0bab SR @0x0bab, $24 +0aba 00fb 0bae SR @0x0bae, $27 +0abc 02df RET + + + +0abd 00c0 0e40 LR $0, @0x0e40 +0abf 0081 0b89 LRI $1, #0x0b89 // PB mixer settings +0ac1 00c2 0e08 LR $2, @0x0e08 +0ac3 0083 0e44 LRI $3, #0x0e44 +0ac5 00c4 0e41 LR $4, @0x0e41 +0ac7 00c5 0e09 LR $5, @0x0e09 +0ac9 02bf 8282 CALL 0x8282 // Call third ROM mixer function +0acb 00f8 0ba9 SR @0x0ba9, $24 +0acd 00fb 0bac SR @0x0bac, $27 +0acf 00c0 0e43 LR $0, @0x0e43 +0ad1 0081 0b91 LRI $1, #0x0b91 +0ad3 00c2 0e0e LR $2, @0x0e0e +0ad5 0083 0e44 LRI $3, #0x0e44 +0ad7 1c80 MRR $4, $0 +0ad8 00c5 0e0f LR $5, @0x0e0f +0ada 02bf 8282 CALL 0x8282 // Call third ROM mixer function +0adc 00f8 0bab SR @0x0bab, $24 +0ade 00fb 0bae SR @0x0bae, $27 +0ae0 00c0 0e40 LR $0, @0x0e40 +0ae2 0081 0b8d LRI $1, #0x0b8d +0ae4 00c2 0e0b LR $2, @0x0e0b +0ae6 0083 0e44 LRI $3, #0x0e44 +0ae8 00c4 0e41 LR $4, @0x0e41 +0aea 00c5 0e0c LR $5, @0x0e0c +0aec 02bf 8282 CALL 0x8282 // Call third ROM mixer function +0aee 00f8 0baa SR @0x0baa, $24 +0af0 00fb 0bad SR @0x0bad, $27 +0af2 00c0 0e43 LR $0, @0x0e43 +0af4 0081 0b99 LRI $1, #0x0b99 +0af6 00c2 0e0d LR $2, @0x0e0d +0af8 0083 0e44 LRI $3, #0x0e44 +0afa 02bf 845d CALL 0x845d +0afc 00f8 0bb0 SR @0x0bb0, $24 +0afe 02df RET + + +// JMP Table for commands +0aff 0082 +0b00 013e +0b01 01bc +0b02 0248 +0b03 0413 +0b04 0427 +0b05 0165 +0b06 0574 +0b07 0b37 +0b08 015f +0b09 0478 +0b0a 0474 +0b0b 0476 +0b0c 01a9 +0b0d 043b +0b0e 047a +0b0f 0bb1 +0b10 0175 + +// JMP Table for mixerCtrl +0b11 0768 +0b12 077a +0b13 079d +0b14 07c0 +0b15 07f4 +0b16 0811 +0b17 0844 +0b18 0877 +0b19 08c6 +0b1a 08d9 +0b1b 08fe +0b1c 0923 +0b1d 095a +0b1e 0979 +0b1f 09af +0b20 09e5 +0b21 0a39 +0b22 0a5b +0b23 0768 +0b24 0768 +0b25 0768 +0b26 0768 +0b27 0768 +0b28 0768 +0b29 0a99 +0b2a 0abd +0b2b 0768 +0b2c 0768 +0b2d 0768 +0b2e 0768 +0b2f 0768 +0b30 0768 + +// JMP Table for srcSelect +0b31 05a8 +0b32 065d +0b33 0707 + +// the COEF Table addresses.. i think there are t.ree tables eac. wit. ~200 bytes +// we could check if it is setup by the GAME too +0b34 1000 +0b35 1200 +0b36 1400 + + +// +// Opcode_08() - Dolphin HLE Plugin doesn't support this command on HLE so prolly no game has ever called it + +0b37 8e00 S40 +0b38 8100 CLR $30 +0b39 8970 CLR.L $31 : $30, @$0 +0b3a 191c LRRI $28, @$0 +0b3b 2ece SRS @DSMAH, $30 +0b3c 2ccf SRS @DSMAL, $28 +0b3d 16cd 0e80 SI @DSPA, #0x0e80 +0b3f 16c9 0000 SI @DSCR, #0x0000 +0b41 16cb 0100 SI @DSBL, #0x0100 +0b43 1f7e MRR $27, $30 +0b44 1f3c MRR $25, $28 +0b45 8100 CLR $30 +0b46 26c9 LRS $30, @DSCR +0b47 02a0 0004 ANDCF $30, #0x0004 +0b49 029c 0b46 JZR 0x0b46 // wait for DMA loop +0b4b 191e LRRI $30, @$0 +0b4c 191c LRRI $28, @$0 +0b4d 2ece SRS @DSMAH, $30 +0b4e 2ccf SRS @DSMAL, $28 +0b4f 16cd 0280 SI @DSPA, #0x0280 +0b51 16c9 0000 SI @DSCR, #0x0000 +0b53 16cb 0280 SI @DSBL, #0x0280 +0b55 1c80 MRR $4, $0 +0b56 0080 0280 LRI $0, #0x0280 +0b58 00c1 0e1b LR $1, @0x0e1b +0b5a 0085 0000 LRI $5, #0x0000 +0b5c 0089 007f LRI $9, #0x007f +0b5e 0082 0f00 LRI $2, #0x0f00 +0b60 0083 16b4 LRI $3, #0x16b4 +0b62 1ce3 MRR $7, $3 +0b63 8100 CLR $30 +0b64 26c9 LRS $30, @DSCR +0b65 02a0 0004 ANDCF $30, #0x0004 +0b67 029c 0b64 JZR 0x0b64 // wait for DMA loop +0b69 8f00 S16 +0b6a 8a78 M2.L : $31, @$0 +0b6b 8c68 CLR15.L : $29, @$0 +0b6c f100 LSL16 $31 +0b6d 1a3f SRR @$1, $31 +0b6e 84e3 CLRP.LD : $26, $25, @$3 +0b6f 107e LOOPI #0x7e +0b70 f2e3 MADD.LD $24, $26 : $26, $25, @$3 +0b71 f2e7 MADD.LDN $24, $26 : $26, $25, @$3 +0b72 f278 MADD.L $24, $26 : $31, @$0 +0b73 6e68 MOVP.L $30 : $29, @$0 +0b74 f132 LSL16.S $31 : @$2, $30 +0b75 1a3f SRR @$1, $31 +0b76 119e 0b80 BLOOPI #0x9e, 0x0b80 +0b78 1c67 MRR $3, $7 +0b79 84e3 CLRP.LD : $26, $25, @$3 +0b7a 107e LOOPI #0x7e +0b7b f2e3 MADD.LD $24, $26 : $26, $25, @$3 +0b7c f2e7 MADD.LDN $24, $26 : $26, $25, @$3 +0b7d f278 MADD.L $24, $26 : $31, @$0 +0b7e 6e68 MOVP.L $30 : $29, @$0 +0b7f f132 LSL16.S $31 : @$2, $30 +0b80 1a3f SRR @$1, $31 +0b81 1c67 MRR $3, $7 +0b82 84e3 CLRP.LD : $26, $25, @$3 +0b83 107e LOOPI #0x7e +0b84 f2e3 MADD.LD $24, $26 : $26, $25, @$3 +0b85 f2e7 MADD.LDN $24, $26 : $26, $25, @$3 +0b86 f200 MADD $24, $26 +0b87 6e00 MOVP $30 +0b88 1b5e SRRI @$2, $30 +0b89 00e1 0e1b SR @0x0e1b, $1 +0b8b 0080 0280 LRI $0, #0x0280 +0b8d 0083 0f00 LRI $3, #0x0f00 +0b8f 0081 0000 LRI $1, #0x0000 +0b91 0082 0140 LRI $2, #0x0140 +0b93 0089 ffff LRI $9, #0xffff +0b95 8900 CLR $31 +0b96 8100 CLR $30 +0b97 8f00 S16 +0b98 11a0 0ba0 BLOOPI #0xa0, 0x0ba0 +0b9a 197f LRRI $31, @$3 +0b9b 9930 ASR16.S $31 : @$0, $30 +0b9c 1b1e SRRI @$0, $30 +0b9d 1b3f SRRI @$1, $31 +0b9e 7d29 NEG.S $31 : @$1, $29 +0b9f 1b5f SRRI @$2, $31 +0ba0 1b5d SRRI @$2, $29 +0ba1 8e00 S40 +0ba2 1fdb MRR $30, $27 +0ba3 1f99 MRR $28, $25 +0ba4 2ece SRS @DSMAH, $30 +0ba5 2ccf SRS @DSMAL, $28 +0ba6 16cd 0e80 SI @DSPA, #0x0e80 +0ba8 16c9 0001 SI @DSCR, #0x0001 +0baa 16cb 0100 SI @DSBL, #0x0100 +0bac 02bf 055c CALL 0x055c // Wait for DMA control reg +0bae 1c04 MRR $0, $4 +0baf 029f 0068 JMP 0x0068 // Return to message loop. + + +// Looks like some "new command" that have been appended +// i think i have seen it in monkey ball only... dunno + +// Opcode_16() +0bb1 8e00 S40 +0bb2 8100 CLR $30 +0bb3 8970 CLR.L $31 : $30, @$0 +0bb4 191c LRRI $28, @$0 +0bb5 2ece SRS @DSMAH, $30 +0bb6 2ccf SRS @DSMAL, $28 +0bb7 16cd 07c0 SI @DSPA, #0x07c0 +0bb9 16c9 0001 SI @DSCR, #0x0001 +0bbb 16cb 0500 SI @DSBL, #0x0500 +0bbd 02bf 055c CALL 0x055c // Wait for DMA control reg +0bbf 8100 CLR $30 +0bc0 8970 CLR.L $31 : $30, @$0 +0bc1 191c LRRI $28, @$0 +0bc2 2ece SRS @DSMAH, $30 +0bc3 2ccf SRS @DSMAL, $28 +0bc4 16cd 07c0 SI @DSPA, #0x07c0 +0bc6 16c9 0000 SI @DSCR, #0x0000 +0bc8 8900 CLR $31 +0bc9 0d20 LRIS $29, #0x20 +0bca 2dcb SRS @DSBL, $29 +0bcb 4c00 ADD $30, $31 +0bcc 1c80 MRR $4, $0 +0bcd 0080 07c0 LRI $0, #0x07c0 +0bcf 0083 0000 LRI $3, #0x0000 +0bd1 1c43 MRR $2, $3 +0bd2 0a00 LRIS $26, #0x00 +0bd3 27c9 LRS $31, @DSCR +0bd4 03a0 0004 ANDCF $31, #0x0004 +0bd6 029c 0bd3 JZR 0x0bd3 // wait for DMA loop +0bd8 2ece SRS @DSMAH, $30 +0bd9 2ccf SRS @DSMAL, $28 +0bda 16cd 07d0 SI @DSPA, #0x07d0 +0bdc 16c9 0000 SI @DSCR, #0x0000 +0bde 16cb 04e0 SI @DSBL, #0x04e0 +0be0 8f00 S16 +0be1 80f0 NX.LDX : $25, $27, @$1 +0be2 80c0 NX.LDX : $24, $26, @$0 +0be3 6a00 MOVAX $30, $25 +0be4 4800 ADDAX $30, $24 +0be5 114f 0bee BLOOPI #0x4f, 0x0bee +0be7 80f0 NX.LDX : $25, $27, @$1 +0be8 80c0 NX.LDX : $24, $26, @$0 +0be9 6b32 MOVAX.S $31, $25 : @$2, $30 +0bea 4922 ADDAX.S $31, $24 : @$2, $28 +0beb 80f0 NX.LDX : $25, $27, @$1 +0bec 80c0 NX.LDX : $24, $26, @$0 +0bed 6a3a MOVAX.S $30, $25 : @$2, $31 +0bee 482a ADDAX.S $30, $24 : @$2, $29 +0bef 80f0 NX.LDX : $25, $27, @$1 +0bf0 80c0 NX.LDX : $24, $26, @$0 +0bf1 6b32 MOVAX.S $31, $25 : @$2, $30 +0bf2 4922 ADDAX.S $31, $24 : @$2, $28 +0bf3 1b5f SRRI @$2, $31 +0bf4 1b5d SRRI @$2, $29 +0bf5 80f0 NX.LDX : $25, $27, @$1 +0bf6 80c0 NX.LDX : $24, $26, @$0 +0bf7 6800 MOVAX $30, $24 +0bf8 7c00 NEG $30 +0bf9 4a00 ADDAX $30, $25 +0bfa 114f 0c05 BLOOPI #0x4f, 0x0c05 +0bfc 80f0 NX.LDX : $25, $27, @$1 +0bfd 80c0 NX.LDX : $24, $26, @$0 +0bfe 6932 MOVAX.S $31, $24 : @$2, $30 +0bff 7d00 NEG $31 +0c00 4b22 ADDAX.S $31, $25 : @$2, $28 +0c01 80f0 NX.LDX : $25, $27, @$1 +0c02 80c0 NX.LDX : $24, $26, @$0 +0c03 683a MOVAX.S $30, $24 : @$2, $31 +0c04 7c00 NEG $30 +0c05 4a2a ADDAX.S $30, $25 : @$2, $29 +0c06 80f0 NX.LDX : $25, $27, @$1 +0c07 80c0 NX.LDX : $24, $26, @$0 +0c08 6932 MOVAX.S $31, $24 : @$2, $30 +0c09 7d00 NEG $31 +0c0a 4b22 ADDAX.S $31, $25 : @$2, $28 +0c0b 1b5f SRRI @$2, $31 +0c0c 1b5d SRRI @$2, $29 +0c0d 1c04 MRR $0, $4 +0c0e 029f 0068 JMP 0x0068 // Return to message loop. + +////////////////////////////////////////////////////////////////////////////// +// +// Exception Functions() +// +////////////////////////////////////////////////////////////////////////////// + +// exception vector 0002 +0c10 8e00 S40 +0c11 16fc ecc0 SI @DMBH, #0xecc0 +0c13 1fcc MRR $30, $12 +0c14 1d9e MRR $12, $30 +0c15 2efd SRS @DMBL, $30 +0c16 26fc LRS $30, @DMBH +0c17 02a0 8000 ANDCF $30, #0x8000 +0c19 029c 0c16 JZR 0x0c16 // wait for dsp mailbox +0c1b 0000 NOP +0c1c 0000 NOP +0c1d 0000 NOP +0c1e 02ff RTI + +// exception vector 0004 +0c1f 8e00 S40 +0c20 00f0 0e17 SR @0x0e17, $16 +0c22 00fe 0e18 SR @0x0e18, $30 +0c24 00fc 0e19 SR @0x0e19, $28 +0c26 1fcc MRR $30, $12 +0c27 1d9e MRR $12, $30 +0c28 16fc feed SI @DMBH, #0xfeed +0c2a 2efd SRS @DMBL, $30 +0c2b 26fc LRS $30, @DMBH +0c2c 02a0 8000 ANDCF $30, #0x8000 +0c2e 029c 0c2b JZR 0x0c2b // wait for dsp mailbox +0c30 00d0 0e17 LR $16, @0x0e17 +0c32 00de 0e18 LR $30, @0x0e18 +0c34 00dc 0e19 LR $28, @0x0e19 +0c36 0000 NOP +0c37 0000 NOP +0c38 0000 NOP +0c39 0000 NOP +0c3a 02ff RTI + +// exception vector 0006 +// somd kind of "stop this PB" +// pseudo c: +{ + if (!pCurrPC->PBAudioAddr->looping) + { + PB->running = 0; + } + RTI +} +0c3b 8e00 S40 +0c3c 1dbc MRR $13, $28 +0c3d 1dbe MRR $13, $30 +0c3e 8100 CLR $30 +0c3f 00de 0bb7 LR $30, @0x0bb7 // PB->PBAudioAddr->looping +0c41 0601 CMPIS $32, #0x01 +0c42 0295 0c47 JEQ 0x0c47 +0c44 0e00 LRIS $30, #0x00 +0c45 00fe 0b87 SR @0x0b87, $30 // PB->running +0c47 1fcd MRR $30, $13 +0c48 1f8d MRR $28, $13 +0c49 02ff RTI + +// exception vector 0008 - do nothing +0c4a 0000 NOP +0c4b 0000 NOP +0c4c 0000 NOP +0c4d 0000 NOP +0c4e 0000 NOP +0c4f 02ff RTI + +// exception vector 000a +// this is what loads loop_yn1 etc. +// An level 5 exception should be caused when the hw ADPCM Decoder reaches the end and loops. +0c50 8e00 S40 +0c51 1dbc MRR $13, $28 +0c52 1dbe MRR $13, $30 +0c53 8100 CLR $30 +0c54 00de 0bb7 LR $30, @0x0bb7 // PB->PBAudioAddr->looping +0c56 0601 CMPIS $32, #0x01 +0c57 0295 0c5f JEQ 0x0c5f +0c59 0e00 LRIS $30, #0x00 +0c5a 00fe 0b87 SR @0x0b87, $30 // PB->running +0c5c 1fcd MRR $30, $13 +0c5d 1f8d MRR $28, $13 +0c5e 02ff RTI + +0c5f 8100 CLR $30 +0c60 00de 0b88 LR $30, @0x0b88 // PB->is_stream +0c62 0601 CMPIS $32, #0x01 +0c63 0295 0c71 JEQ 0x0c71 +0c65 00de 0bda LR $30, @0x0bda // PB->PBADPCMInfo->pred_scale +0c67 2eda SRS @pred_scale, $30 +0c68 00de 0bdb LR $30, @0x0bdb // PB->PBADPCMInfo->yn1 +0c6a 2edb SRS @yn1, $30 +0c6b 00de 0bdc LR $30, @0x0bdc // PB->PBADPCMInfo->yn2 +0c6d 2edc SRS @yn2, $30 +0c6e 1fcd MRR $30, $13 +0c6f 1f8d MRR $28, $13 +0c70 02ff RTI + +// this is done for streaming +0c71 00de 0bda LR $30, @0x0bda // PB->PBADPCMInfo->pred_scale +0c73 2eda SRS @pred_scale, $30 +0c74 26db LRS $30, @yn1 +0c75 2edb SRS @yn1, $30 +0c76 26dc LRS $30, @yn2 +0c77 2edc SRS @yn2, $30 +0c78 8100 CLR $30 +0c79 00dc 0bdd LR $28, @0x0bdd // reads from the first PB->padding byte :) +0c7b 7600 INC $30 +0c7c 00fc 0bdd SR @0x0bdd, $28 +0c7e 8100 CLR $30 +0c7f 1fcd MRR $30, $13 +0c80 1f8d MRR $28, $13 +0c81 02ff RTI + + +// exception vector 000c +0c82 0000 NOP +0c83 0000 NOP +0c84 0000 NOP +0c85 0000 NOP +0c86 0000 NOP +0c87 02ff RTI + + +// exception vector 000e +0c88 0000 NOP +0c89 0000 NOP +0c8a 0000 NOP +0c8b 0000 NOP +0c8c 02ff RTI + +////////////////////////////////////////////////////////////////////////////// +// +// End of exception functions +// +////////////////////////////////////////////////////////////////////////////// + + +// Jmp table for function below +// i think case 0x03 is the standard case +0c8d 0c9f LRIS $28, #0x9f // some kind of soft-reset for the UCode +0c8e 0ca2 LRIS $28, #0xa2 // looks like code to dump the UCode memory for debugging +0c8f 0cda LRIS $28, #0xda // rest the UCode and jump to ROM +0c90 0cdd LRIS $28, #0xdd // normal case to return to the main-loop + + +// Wait for new message from the CPU +0c91 8e00 S40 +0c92 8100 CLR $30 +0c93 8900 CLR $31 +0c94 02bf 0ce0 CALL 0x0ce0 // wait for answer for our "0xDCD10002"-message... and we have to wait really long :( +0c96 27ff LRS $31, @CMBL +0c97 009e 0c8d LRI $30, #0x0c8d +0c99 4c00 ADD $30, $31 +0c9a 1c7e MRR $3, $30 +0c9b 0313 ILRR $31, @$3 +0c9c 1c7f MRR $3, $31 +0c9d 176f JMPR $3 +0c9e 0021 HALT + +//////////////////////////////////////////////////////////////////////////7 + +// case 0x00: +0c9f 029f 0030 JMP 0x0030 +0ca1 0021 HALT + +// case 0x01: +0ca2 8100 CLR $30 +0ca3 8900 CLR $31 +0ca4 02bf 0ce0 CALL 0x0ce0 // wait for CMBH +0ca6 24ff LRS $28, @CMBL +0ca7 02bf 0ce6 CALL 0x0ce6 // wait for CMBH, R31 +0ca9 25ff LRS $29, @CMBL +0caa 02bf 0ce6 CALL 0x0ce6 // wait for CMBH, R31 +0cac 27ff LRS $31, @CMBL +0cad 2ece SRS @DSMAH, $30 +0cae 2ccf SRS @DSMAL, $28 +0caf 16c9 0001 SI @DSCR, #0x0001 +0cb1 2fcd SRS @DSPA, $31 +0cb2 2dcb SRS @DSBL, $29 +0cb3 8100 CLR $30 +0cb4 8900 CLR $31 +0cb5 02bf 0ce0 CALL 0x0ce0 // wait for CMBH +0cb7 24ff LRS $28, @CMBL +0cb8 1c9e MRR $4, $30 +0cb9 1cbc MRR $5, $28 +0cba 02bf 0ce6 CALL 0x0ce6 // wait for CMBH, R31 +0cbc 25ff LRS $29, @CMBL +0cbd 02bf 0ce6 CALL 0x0ce6 // wait for CMBH, R31 +0cbf 27ff LRS $31, @CMBL +0cc0 1cdf MRR $6, $31 +0cc1 1cfd MRR $7, $29 +0cc2 8100 CLR $30 +0cc3 02bf 0ce0 CALL 0x0ce0 // wait for CMBH +0cc5 26ff LRS $30, @CMBL +0cc6 1c1e MRR $0, $30 +0cc7 8900 CLR $31 +0cc8 02bf 0ce6 CALL 0x0ce6 // wait for CMBH, R31 +0cca 20ff LRS $24, @CMBL +0ccb 1f5f MRR $26, $31 +0ccc 02bf 0ce0 CALL 0x0ce0 // wait for CMBH +0cce 21ff LRS $25, @CMBL +0ccf 02bf 0ce0 CALL 0x0ce0 // wait for CMBH +0cd1 23ff LRS $27, @CMBL +0cd2 26c9 LRS $30, @DSCR +0cd3 02a0 0004 ANDCF $30, #0x0004 +0cd5 029c 0cd2 JZR 0x0cd2 +0cd7 029f 80b5 JMP 0x80b5 +0cd9 0021 HALT + +// case 0x03: +0cda 029f 8000 JMP 0x8000 +0cdc 0021 HALT + +// case 0x04: +0cdd 029f 0045 JMP 0x0045 +0cdf 0021 HALT + +// wait for cpu mail +0ce0 26fe LRS $30, @CMBH +0ce1 02c0 8000 ANDF $30, #0x8000 +0ce3 029c 0ce0 JZR 0x0ce0 +0ce5 02df RET + +// wait for cpu mail +0ce6 27fe LRS $31, @CMBH +0ce7 03c0 8000 ANDF $31, #0x8000 +0ce9 029c 0ce6 JZR 0x0ce6 +0ceb 02df RET + diff --git a/docs/DSP/DSP_InterC/DSP_InterC.sln b/docs/DSP/DSP_InterC/DSP_InterC.sln new file mode 100644 index 0000000000..5c7b2aa21d --- /dev/null +++ b/docs/DSP/DSP_InterC/DSP_InterC.sln @@ -0,0 +1,20 @@ + +Microsoft Visual Studio Solution File, Format Version 10.00 +# Visual Studio 2008 +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "DSP_InterC", "DSP_InterC\DSP_InterC.vcproj", "{A010425E-9D5E-461E-910D-0804C2A944D5}" +EndProject +Global + GlobalSection(SolutionConfigurationPlatforms) = preSolution + Debug|Win32 = Debug|Win32 + Release|Win32 = Release|Win32 + EndGlobalSection + GlobalSection(ProjectConfigurationPlatforms) = postSolution + {A010425E-9D5E-461E-910D-0804C2A944D5}.Debug|Win32.ActiveCfg = Debug|Win32 + {A010425E-9D5E-461E-910D-0804C2A944D5}.Debug|Win32.Build.0 = Debug|Win32 + {A010425E-9D5E-461E-910D-0804C2A944D5}.Release|Win32.ActiveCfg = Release|Win32 + {A010425E-9D5E-461E-910D-0804C2A944D5}.Release|Win32.Build.0 = Release|Win32 + EndGlobalSection + GlobalSection(SolutionProperties) = preSolution + HideSolutionNode = FALSE + EndGlobalSection +EndGlobal diff --git a/docs/DSP/DSP_InterC/DSP_InterC/DSPExt.cpp b/docs/DSP/DSP_InterC/DSP_InterC/DSPExt.cpp new file mode 100644 index 0000000000..d27902b729 --- /dev/null +++ b/docs/DSP/DSP_InterC/DSP_InterC/DSPExt.cpp @@ -0,0 +1,320 @@ +/*==================================================================== + + filename: opcodes.h + project: GameCube DSP Tool (gcdsp) + created: 2005.03.04 + mail: duddie@walla.com + + Copyright (c) 2005 Duddie + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License + as published by the Free Software Foundation; either version 2 + of the License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + + ====================================================================*/ +// +// +// At the moment just ls and sl are using the prolog +// perhaps all actions on r03 must be in the prolog +// +#include + +#include "OutBuffer.h" + + + +// +void dsp_op_ext_r_epi(uint16 _Opcode) +{ + uint8 op = (_Opcode >> 2) & 0x3; + uint8 reg = _Opcode & 0x3; + + switch (op) + { + case 0x00: + OutBuffer::AddCode("Error: dsp_op_ext_r_epi"); + break; + + case 0x01: + OutBuffer::AddCode("%s--", OutBuffer::GetRegName(reg)); + // g_dsp.r[reg]--; + break; + + case 0x02: + OutBuffer::AddCode("%s++", OutBuffer::GetRegName(reg)); + //g_dsp.r[reg]++; + break; + + case 0x03: + OutBuffer::AddCode("%s += %s", OutBuffer::GetRegName(reg), OutBuffer::GetRegName(reg+4)); + // g_dsp.r[reg] += g_dsp.r[reg + 4]; + break; + } +} + + +void dsp_op_ext_mv(uint16 _Opcode) +{ + uint8 sreg = _Opcode & 0x3; + uint8 dreg = ((_Opcode >> 2) & 0x3); + + OutBuffer::AddCode("%s = %s", OutBuffer::GetRegName(dreg + 0x18), OutBuffer::GetRegName(sreg + 0x1c)); + + // g_dsp.r[dreg + 0x18] = g_dsp.r[sreg + 0x1c]; +} + + +void dsp_op_ext_s(uint16 _Opcode) +{ + uint8 dreg = _Opcode & 0x3; + uint8 sreg = ((_Opcode >> 3) & 0x3) + 0x1c; + + OutBuffer::AddCode("WriteDMEM(%s, %s)", OutBuffer::GetRegName(dreg), OutBuffer::GetRegName(sreg)); + // dsp_dmem_write(g_dsp.r[dreg], g_dsp.r[sreg]); + + if (_Opcode & 0x04) + { + OutBuffer::AddCode("%s += %s", OutBuffer::GetRegName(dreg), OutBuffer::GetRegName(dreg+4)); + // g_dsp.r[dreg] += g_dsp.r[dreg + 4]; + } + else + { + OutBuffer::AddCode("%s++", OutBuffer::GetRegName(dreg)); + //g_dsp.r[dreg]++; + } +} + + +void dsp_op_ext_l(uint16 _Opcode) +{ + uint8 sreg = _Opcode & 0x3; + uint8 dreg = ((_Opcode >> 3) & 0x7) + 0x18; + + OutBuffer::AddCode("%s = ReadDMEM(%s)", OutBuffer::GetRegName(dreg), OutBuffer::GetRegName(sreg)); + // uint16 val = dsp_dmem_read(g_dsp.r[sreg]); + // g_dsp.r[dreg] = val; + + if (_Opcode & 0x04) + { + OutBuffer::AddCode("%s += %s", OutBuffer::GetRegName(sreg), OutBuffer::GetRegName(sreg+4)); + // g_dsp.r[sreg] += g_dsp.r[sreg + 4]; + } + else + { + OutBuffer::AddCode("%s++", OutBuffer::GetRegName(sreg)); + // g_dsp.r[sreg]++; + } +} + + +void dsp_op_ext_ls_pro(uint16 _Opcode) +{ + uint8 areg = (_Opcode & 0x1) + 0x1e; + + OutBuffer::AddCode("WriteDMEM(%s, %s)", OutBuffer::GetRegName(0x03), OutBuffer::GetRegName(areg)); + // dsp_dmem_write(g_dsp.r[0x03], g_dsp.r[areg]); + + if (_Opcode & 0x8) + { + OutBuffer::AddCode("%s += %s", OutBuffer::GetRegName(0x03), OutBuffer::GetRegName(0x07)); + // g_dsp.r[0x03] += g_dsp.r[0x07]; + } + else + { + OutBuffer::AddCode("%s++", OutBuffer::GetRegName(0x03)); + // g_dsp.r[0x03]++; + } +} + + +void dsp_op_ext_ls_epi(uint16 _Opcode) +{ + uint8 dreg = ((_Opcode >> 4) & 0x3) + 0x18; + + OutBuffer::AddCode("%s = ReadDMEM(%s)", OutBuffer::GetRegName(dreg), OutBuffer::GetRegName(0x00)); + // uint16 val = dsp_dmem_read(g_dsp.r[0x00]); + // dsp_op_write_reg(dreg, val); + + if (_Opcode & 0x4) + { + OutBuffer::AddCode("%s += %s", OutBuffer::GetRegName(0x00), OutBuffer::GetRegName(0x04)); + // g_dsp.r[0x00] += g_dsp.r[0x04]; + } + else + { + OutBuffer::AddCode("%s++", OutBuffer::GetRegName(0x00)); + // g_dsp.r[0x00]++; + } +} + + +void dsp_op_ext_sl_pro(uint16 _Opcode) +{ + uint8 areg = (_Opcode & 0x1) + 0x1e; + + OutBuffer::AddCode("WriteDMEM(%s, %s)", OutBuffer::GetRegName(0x00), OutBuffer::GetRegName(areg)); + // dsp_dmem_write(g_dsp.r[0x00], g_dsp.r[areg]); + + if (_Opcode & 0x4) + { + OutBuffer::AddCode("%s += %s", OutBuffer::GetRegName(0x00), OutBuffer::GetRegName(0x04)); + // g_dsp.r[0x00] += g_dsp.r[0x04]; + } + else + { + OutBuffer::AddCode("%s++", OutBuffer::GetRegName(0x00)); + // g_dsp.r[0x00]++; + } +} + + +void dsp_op_ext_sl_epi(uint16 _Opcode) +{ + uint8 dreg = ((_Opcode >> 4) & 0x3) + 0x18; + + OutBuffer::AddCode("%s = ReadDMEM(%s)", OutBuffer::GetRegName(dreg), OutBuffer::GetRegName(0x03)); + // uint16 val = dsp_dmem_read(g_dsp.r[0x03]); + // dsp_op_write_reg(dreg, val); + + if (_Opcode & 0x8) + { + OutBuffer::AddCode("%s += %s", OutBuffer::GetRegName(0x03), OutBuffer::GetRegName(0x07)); + // g_dsp.r[0x03] += g_dsp.r[0x07]; + } + else + { + OutBuffer::AddCode("%s++", OutBuffer::GetRegName(0x03)); + // g_dsp.r[0x03]++; + } +} + + +void dsp_op_ext_ld(uint16 _Opcode) +{ + uint8 dreg1 = (((_Opcode >> 5) & 0x1) << 1) + 0x18; + uint8 dreg2 = (((_Opcode >> 4) & 0x1) << 1) + 0x19; + uint8 sreg = _Opcode & 0x3; + + OutBuffer::AddCode("%s = ReadDMEM(%s)", OutBuffer::GetRegName(dreg1), OutBuffer::GetRegName(sreg)); + OutBuffer::AddCode("%s = ReadDMEM(%s)", OutBuffer::GetRegName(dreg2), OutBuffer::GetRegName(0x03)); + + // g_dsp.r[dreg1] = dsp_dmem_read(g_dsp.r[sreg]); + // g_dsp.r[dreg2] = dsp_dmem_read(g_dsp.r[0x03]); + + if (_Opcode & 0x04) + { + OutBuffer::AddCode("%s += %s", OutBuffer::GetRegName(sreg), OutBuffer::GetRegName(sreg + 0x04)); + // g_dsp.r[sreg] += g_dsp.r[sreg + 0x04]; + } + else + { + OutBuffer::AddCode("%s++", OutBuffer::GetRegName(sreg)); + // g_dsp.r[sreg]++; + } + + if (_Opcode & 0x08) + { + OutBuffer::AddCode("%s += %s", OutBuffer::GetRegName(0x03), OutBuffer::GetRegName(sreg + 0x07)); + // g_dsp.r[0x03] += g_dsp.r[0x07]; + } + else + { + OutBuffer::AddCode("%s++", OutBuffer::GetRegName(0x03)); + // g_dsp.r[0x03]++; + } +} + + +// ================================================================================ +// +// +// +// ================================================================================ + +void dsp_op_ext_ops_pro(uint16 _Opcode) +{ + if ((_Opcode & 0xFF) == 0){return;} + + switch ((_Opcode >> 4) & 0xf) + { + case 0x00: + dsp_op_ext_r_epi(_Opcode); + break; + + case 0x01: + dsp_op_ext_mv(_Opcode); + break; + + case 0x02: + case 0x03: + dsp_op_ext_s(_Opcode); + break; + + case 0x04: + case 0x05: + case 0x06: + case 0x07: + dsp_op_ext_l(_Opcode); + break; + + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + + if (_Opcode & 0x2) + { + dsp_op_ext_sl_pro(_Opcode); + } + else + { + dsp_op_ext_ls_pro(_Opcode); + } + + return; + + case 0x0c: + case 0x0d: + case 0x0e: + case 0x0f: + dsp_op_ext_ld(_Opcode); + break; + } +} + + +void dsp_op_ext_ops_epi(uint16 _Opcode) +{ + if ((_Opcode & 0xFF) == 0){return;} + + switch ((_Opcode >> 4) & 0xf) + { + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + + if (_Opcode & 0x2) + { + dsp_op_ext_sl_epi(_Opcode); + } + else + { + dsp_op_ext_ls_epi(_Opcode); + } + + return; + } +} + + diff --git a/docs/DSP/DSP_InterC/DSP_InterC/DSPExt.h b/docs/DSP/DSP_InterC/DSP_InterC/DSPExt.h new file mode 100644 index 0000000000..b6fb8fc9be --- /dev/null +++ b/docs/DSP/DSP_InterC/DSP_InterC/DSPExt.h @@ -0,0 +1,33 @@ +/*==================================================================== + + filename: opcodes.h + project: GameCube DSP Tool (gcdsp) + created: 2005.03.04 + mail: duddie@walla.com + + Copyright (c) 2005 Duddie + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License + as published by the Free Software Foundation; either version 2 + of the License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + + ====================================================================*/ + +#ifndef _GDSP_EXT_OP_H +#define _GDSP_EXT_OP_H + +void dsp_op_ext_ops_pro(uint16 _Opcode); +void dsp_op_ext_ops_epi(uint16 _Opcode); + + +#endif diff --git a/docs/DSP/DSP_InterC/DSP_InterC/DSPOpcodes.cpp b/docs/DSP/DSP_InterC/DSP_InterC/DSPOpcodes.cpp new file mode 100644 index 0000000000..6efa29459a --- /dev/null +++ b/docs/DSP/DSP_InterC/DSP_InterC/DSPOpcodes.cpp @@ -0,0 +1,2353 @@ +#include + +#include "DSPOpcodes.h" +#include "DSPExt.h" + +#define SR_CMP_MASK 0x3f +#define DSP_REG_MASK 0x1f + +/* + +bool CheckCondition(uint8 _Condition) +{ + bool taken = false; + + switch (_Condition & 0xf) + { + case 0x0: + + if ((!(g_dsp.r[R_SR] & 0x02)) && (!(g_dsp.r[R_SR] & 0x08))) + { + taken = true; + } + + break; + + case 0x3: + + if ((g_dsp.r[R_SR] & 0x02) || (g_dsp.r[R_SR] & 0x04) || (g_dsp.r[R_SR] & 0x08)) + { + taken = true; + } + + break; + + // old from duddie + case 0x1: // seems okay + + if ((!(g_dsp.r[R_SR] & 0x02)) && (g_dsp.r[R_SR] & 0x08)) + { + taken = true; + } + + break; + + case 0x2: + + if (!(g_dsp.r[R_SR] & 0x08)) + { + taken = true; + } + + break; + + case 0x4: + + if (!(g_dsp.r[R_SR] & 0x04)) + { + taken = true; + } + + break; + + case 0x5: + + if (g_dsp.r[R_SR] & 0x04) + { + taken = true; + } + + break; + + case 0xc: + + if (!(g_dsp.r[R_SR] & 0x40)) + { + taken = true; + } + + break; + + case 0xd: + + if (g_dsp.r[R_SR] & 0x40) + { + taken = true; + } + + break; + + case 0xf: + taken = true; + break; + + default: + // DebugLog("Unknown condition check: 0x%04x\n", _Condition & 0xf); + break; + } + + return(taken); +} +*/ + +// ======================================================================= + +//------------------------------------------------------------------------------- +void (*dsp_op[])(uint16 opc) = +{ + dsp_op0, dsp_op1, dsp_op2, dsp_op3, + dsp_op4, dsp_op5, dsp_op6, dsp_op7, + dsp_op8, dsp_op9, dsp_opab, dsp_opab, + dsp_opcd, dsp_opcd, dsp_ope, dsp_opf, +}; + +void DecodeOpcode(uint16 op) +{ + dsp_op[op >> 12](op); + +} +void dsp_op_unknown(uint16 opc) +{ + ErrorLog("dsp_op_unknown somewhere"); + OutBuffer::AddCode("unknown somewhere"); +} + + +void dsp_opc_call(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_call"); + +/* uint16 dest = FetchOpcode(); + if (CheckCondition(opc & 0xf)) + { + dsp_reg_store_stack(DSP_STACK_C, g_dsp.pc); + g_dsp.pc = dest; + } */ +} + + +void dsp_opc_ifcc(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_call"); + +/* if (!CheckCondition(opc & 0xf)) + { + FetchOpcode(); // skip the next opcode + }*/ +} + + +void dsp_opc_jcc(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_call"); + +/* uint16 dest = FetchOpcode(); + + if (CheckCondition(opc & 0xf)) + { + g_dsp.pc = dest; + }*/ +} + + +void dsp_opc_jmpa(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_call"); + +/* uint8 reg; + uint16 addr; + + if ((opc & 0xf) != 0xf) + { + ErrorLog("dsp_opc_jmpa"); + } + + reg = (opc >> 5) & 0x7; + addr = dsp_op_read_reg(reg); + + if (opc & 0x0010) + { + // CALLA + dsp_reg_store_stack(DSP_STACK_C, g_dsp.pc); + } + + g_dsp.pc = addr;*/ +} + + +// NEW (added condition check) +void dsp_opc_ret(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_ret"); + +/* if (CheckCondition(opc & 0xf)) + { + g_dsp.pc = dsp_reg_load_stack(DSP_STACK_C); + }*/ +} + + +void dsp_opc_rti(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_rti"); + +/* if ((opc & 0xf) != 0xf) + { + ErrorLog("dsp_opc_rti"); + } + + g_dsp.r[R_SR] = dsp_reg_load_stack(DSP_STACK_D); + g_dsp.pc = dsp_reg_load_stack(DSP_STACK_C); + + g_dsp.exception_in_progress_hack = false;*/ +} + + +void dsp_opc_halt(uint16 opc) +{ + OutBuffer::AddCode("HALT"); + +/* g_dsp.cr |= 0x4; + g_dsp.pc = g_dsp.err_pc;*/ +} + + +void dsp_opc_loop(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_loop"); + +/* uint16 reg = opc & 0x1f; + uint16 cnt = g_dsp.r[reg]; + uint16 loop_pc = g_dsp.pc; + + while (cnt--) + { + gdsp_loop_step(); + g_dsp.pc = loop_pc; + } + + g_dsp.pc = loop_pc + 1; */ +} + + +void dsp_opc_loopi(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_loopi"); + +/* uint16 cnt = opc & 0xff; + uint16 loop_pc = g_dsp.pc; + + while (cnt--) + { + gdsp_loop_step(); + g_dsp.pc = loop_pc; + } + + g_dsp.pc = loop_pc + 1;*/ +} + + +void dsp_opc_bloop(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_bloop"); + +/* uint16 reg = opc & 0x1f; + uint16 cnt = g_dsp.r[reg]; + uint16 loop_pc = FetchOpcode(); + + if (cnt) + { + dsp_reg_store_stack(0, g_dsp.pc); + dsp_reg_store_stack(2, loop_pc); + dsp_reg_store_stack(3, cnt); + } + else + { + g_dsp.pc = loop_pc + 1; + }*/ +} + + +void dsp_opc_bloopi(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_bloopi"); + +/* uint16 cnt = opc & 0xff; + uint16 loop_pc = FetchOpcode(); + + if (cnt) + { + dsp_reg_store_stack(0, g_dsp.pc); + dsp_reg_store_stack(2, loop_pc); + dsp_reg_store_stack(3, cnt); + } + else + { + g_dsp.pc = loop_pc + 1; + }*/ +} + + +//------------------------------------------------------------- + + +void dsp_opc_mrr(uint16 opc) +{ + uint8 sreg = opc & 0x1f; + uint8 dreg = (opc >> 5) & 0x1f; + + OutBuffer::AddCode("%s = %s", OutBuffer::GetRegName(dreg), OutBuffer::GetRegName(sreg)); + +// uint16 val = dsp_op_read_reg(sreg); +// dsp_op_write_reg(dreg, val); +} + + +void dsp_opc_lrr(uint16 opc) +{ + uint8 sreg = (opc >> 5) & 0x3; + uint8 dreg = opc & 0x1f; + + OutBuffer::AddCode("%s = ReadDMEM(%s)", OutBuffer::GetRegName(dreg), OutBuffer::GetRegName(sreg)); + +// uint16 val = dsp_dmem_read(g_dsp.r[sreg]); +// dsp_op_write_reg(dreg, val); + + // post processing of source reg + switch ((opc >> 7) & 0x3) + { + case 0x0: // LRR + break; + + case 0x1: // LRRD + OutBuffer::AddCode("%s--", OutBuffer::GetRegName(sreg)); + // g_dsp.r[sreg]--; + break; + + case 0x2: // LRRI + OutBuffer::AddCode("%s++", OutBuffer::GetRegName(sreg)); + //g_dsp.r[sreg]++; + break; + + case 0x3: + OutBuffer::AddCode("%s += %s", OutBuffer::GetRegName(sreg), OutBuffer::GetRegName(sreg+4)); + // g_dsp.r[sreg] += g_dsp.r[sreg + 4]; + break; + } +} + + +void dsp_opc_srr(uint16 opc) +{ + uint8 dreg = (opc >> 5) & 0x3; + uint8 sreg = opc & 0x1f; + + OutBuffer::AddCode("WriteDMEM(%s, %s)", OutBuffer::GetRegName(dreg), OutBuffer::GetRegName(sreg)); + + //uint16 val = dsp_op_read_reg(sreg); + // dsp_dmem_write(g_dsp.r[dreg], val); + + // post processing of source reg + switch ((opc >> 7) & 0x3) + { + case 0x0: // SRR + break; + + case 0x1: // SRRD + OutBuffer::AddCode("%s--", OutBuffer::GetRegName(dreg)); + // g_dsp.r[dreg]--; + break; + + case 0x2: // SRRI + OutBuffer::AddCode("%s++", OutBuffer::GetRegName(dreg)); + // g_dsp.r[dreg]++; + break; + + case 0x3: // SRRX + OutBuffer::AddCode("%s += %s", OutBuffer::GetRegName(dreg), OutBuffer::GetRegName(dreg+4)); + //g_dsp.r[dreg] += g_dsp.r[dreg + 4]; + break; + } +} + + +void dsp_opc_ilrr(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_ilrr"); + +/* uint16 reg = opc & 0x3; + uint16 dreg = 0x1e + ((opc >> 8) & 1); + + // always to acc0 ? + g_dsp.r[dreg] = dsp_imem_read(g_dsp.r[reg]); + + switch ((opc >> 2) & 0x3) + { + case 0x0: // no change + break; + + case 0x1: // post decrement + g_dsp.r[reg]--; + break; + + case 0x2: // post increment + g_dsp.r[reg]++; + break; + + default: + ErrorLog("dsp_opc_ilrr"); + }*/ +} + + +void dsp_opc_lri(uint16 opc) +{ + uint8 reg = opc & DSP_REG_MASK; + uint16 imm = FetchOpcode(); + + OutBuffer::AddCode("%s = 0x%02x", OutBuffer::GetRegName(reg), imm); + // dsp_op_write_reg(reg, imm); +} + + +void dsp_opc_lris(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_lris"); + +/* uint8 reg = ((opc >> 8) & 0x7) + 0x18; + uint16 imm = (sint8)opc; + dsp_op_write_reg(reg, imm);*/ +} + + +void dsp_opc_lr(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_lr"); + +/* uint8 reg = opc & DSP_REG_MASK; + uint16 addr = FetchOpcode(); + uint16 val = dsp_dmem_read(addr); + dsp_op_write_reg(reg, val);*/ +} + + +void dsp_opc_sr(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_sr"); + + /*uint8 reg = opc & DSP_REG_MASK; + uint16 addr = FetchOpcode(); + uint16 val = dsp_op_read_reg(reg); + dsp_dmem_write(addr, val);*/ +} + + +void dsp_opc_si(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_si"); + + //uint16 addr = (sint8)opc; + //uint16 imm = readimemory(); + //dsp_dmem_write(addr, imm); +} + + +void dsp_opc_tstaxh(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_tstaxh"); + + //uint8 reg = (opc >> 8) & 0x1; + //sint16 val = dsp_get_ax_h(reg); + + //Update_SR_Register(val); +} + + +void dsp_opc_clr(uint16 opc) +{ + uint8 reg = (opc >> 11) & 0x1; + + OutBuffer::AddCode("ACC%i = 0", reg); + OutBuffer::AddCode("Update_SR_Register(ACC%i)", reg); + + //dsp_set_long_acc(reg, 0); + + //Update_SR_Register((sint64)0); +} + + +void dsp_opc_clrp(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_clrp"); + + //g_dsp.r[0x14] = 0x0000; + //g_dsp.r[0x15] = 0xfff0; + //g_dsp.r[0x16] = 0x00ff; + //g_dsp.r[0x17] = 0x0010; +} + + +// NEW +void dsp_opc_mulc(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_mulc"); + + // math new prod + //uint8 sreg = (opc >> 11) & 0x1; + //uint8 treg = (opc >> 12) & 0x1; + + //sint64 prod = dsp_get_acc_m(sreg) * dsp_get_ax_h(treg) * GetMultiplyModifier(); + //dsp_set_long_prod(prod); + + //Update_SR_Register(prod); +} + + +// NEW +void dsp_opc_mulcmvz(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_mulcmvz"); + + ErrorLog("dsp_opc_mulcmvz ni"); +} + + +// NEW +void dsp_opc_mulcmv(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_mulcmv"); + + ErrorLog("dsp_opc_mulcmv ni"); +} + + +void dsp_opc_cmpar(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_cmpar"); + + //uint8 rreg = ((opc >> 12) & 0x1) + 0x1a; + //uint8 areg = (opc >> 11) & 0x1; + + //// we compare + //sint64 rr = (sint16)g_dsp.r[rreg]; + //rr <<= 16; + + //sint64 ar = dsp_get_long_acc(areg); + + //Update_SR_Register(ar - rr); +} + + +void dsp_opc_cmp(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_cmp"); + + //sint64 acc0 = dsp_get_long_acc(0); + //sint64 acc1 = dsp_get_long_acc(1); + + //Update_SR_Register(acc0 - acc1); +} + + +void dsp_opc_tsta(uint16 opc) +{ + uint8 reg = (opc >> 11) & 0x1; + OutBuffer::AddCode("Update_SR_Register(ACC%i)", reg); + + //uint8 reg = (opc >> 11) & 0x1; + //sint64 acc = dsp_get_long_acc(reg); + + //Update_SR_Register(acc); +} + + +// NEW +void dsp_opc_addaxl(uint16 opc) +{ + uint8 sreg = (opc >> 9) & 0x1; + uint8 dreg = (opc >> 8) & 0x1; + + OutBuffer::AddCode("ACC%i += AX%i_l", dreg, sreg); + OutBuffer::AddCode("Update_SR_Register(ACC%i)", dreg); + + //sint64 acc = dsp_get_long_acc(dreg); + //sint64 acx = dsp_get_ax_l(sreg); + + //acc += acx; + + //dsp_set_long_acc(dreg, acc); + + //Update_SR_Register(acc); +} + + +// NEW +void dsp_opc_addarn(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_addarn"); + + //uint8 dreg = opc & 0x3; + //uint8 sreg = (opc >> 2) & 0x3; + + //g_dsp.r[dreg] += (sint16)g_dsp.r[0x04 + sreg]; +} + + +// NEW +void dsp_opc_mulcac(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_mulcac"); + + //sint64 TempProd = dsp_get_long_prod(); + + //// update prod + //uint8 sreg = (opc >> 12) & 0x1; + //sint64 Prod = (sint64)dsp_get_acc_m(sreg) * (sint64)dsp_get_acc_h(sreg) * GetMultiplyModifier(); + //dsp_set_long_prod(Prod); + + //// update acc + //uint8 rreg = (opc >> 8) & 0x1; + //dsp_set_long_acc(rreg, TempProd); +} + + +// NEW +void dsp_opc_movr(uint16 opc) +{ + uint8 areg = (opc >> 8) & 0x1; + uint8 sreg = ((opc >> 9) & 0x3) + 0x18; + + OutBuffer::AddCode("ACC%i = (%s << 16) & ~0xFFFF", areg, OutBuffer::GetRegName(sreg)); + OutBuffer::AddCode("Update_SR_Register(ACC%i)", areg); + + //sint64 acc = (sint16)g_dsp.r[sreg]; + //acc <<= 16; + //acc &= ~0xffff; + + //dsp_set_long_acc(areg, acc); + + //Update_SR_Register(acc); +} + + +void dsp_opc_movax(uint16 opc) +{ + uint8 sreg = (opc >> 9) & 0x1; + uint8 dreg = (opc >> 8) & 0x1; + + OutBuffer::AddCode("%s = %s", OutBuffer::GetRegName(0x1c + dreg), OutBuffer::GetRegName(0x18 + sreg)); + OutBuffer::AddCode("%s = %s", OutBuffer::GetRegName(0x1e + dreg), OutBuffer::GetRegName(0x1a + sreg)); + + //g_dsp.r[0x1c + dreg] = g_dsp.r[0x18 + sreg]; + //g_dsp.r[0x1e + dreg] = g_dsp.r[0x1a + sreg]; + + OutBuffer::AddCode("%s = (%s < 0) ? 0xFFFF : 0x0000", OutBuffer::GetRegName(0x10 + dreg), + OutBuffer::GetRegName(0x1a + sreg)); + + //if ((sint16)g_dsp.r[0x1a + sreg] < 0) + //{ + // g_dsp.r[0x10 + dreg] = 0xffff; + //} + //else + //{ + // g_dsp.r[0x10 + dreg] = 0; + //} + + dsp_opc_tsta(dreg << 11); +} + + +// NEW +void dsp_opc_xorr(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_xorr"); + + //uint8 sreg = (opc >> 9) & 0x1; + //uint8 dreg = (opc >> 8) & 0x1; + + //g_dsp.r[0x1e + dreg] ^= g_dsp.r[0x1a + sreg]; + + //dsp_opc_tsta(dreg << 11); +} + + +void dsp_opc_andr(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_andr"); + + //uint8 sreg = (opc >> 9) & 0x1; + //uint8 dreg = (opc >> 8) & 0x1; + + //g_dsp.r[0x1e + dreg] &= g_dsp.r[0x1a + sreg]; + + //dsp_opc_tsta(dreg << 11); +} + + +// NEW +void dsp_opc_orr(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_orr"); + + //uint8 sreg = (opc >> 9) & 0x1; + //uint8 dreg = (opc >> 8) & 0x1; + + //g_dsp.r[0x1e + dreg] |= g_dsp.r[0x1a + sreg]; + + //dsp_opc_tsta(dreg << 11); +} + + +// NEW +void dsp_opc_andc(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_andc"); + + //uint8 D = (opc >> 8) & 0x1; + + //uint16 ac1 = dsp_get_acc_m(D); + //uint16 ac2 = dsp_get_acc_m(1 - D); + + //dsp_set_long_acc(D, ac1 & ac2); + + //if ((ac1 & ac2) == 0) + //{ + // g_dsp.r[R_SR] |= 0x20; + //} + //else + //{ + // g_dsp.r[R_SR] &= ~0x20; + //} +} + + +//------------------------------------------------------------- + +void dsp_opc_nx(uint16 opc) +{} + + +// NEW +void dsp_opc_andfc(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_andfc"); + + //if (opc & 0xf) + //{ + // ErrorLog("dsp_opc_andfc"); + //} + + //uint8 reg = (opc >> 8) & 0x1; + //uint16 imm = FetchOpcode(); + //uint16 val = dsp_get_acc_m(reg); + + //if ((val & imm) == imm) + //{ + // g_dsp.r[R_SR] |= 0x40; + //} + //else + //{ + // g_dsp.r[R_SR] &= ~0x40; + //} +} + + +void dsp_opc_andf(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_andf"); + + //uint8 reg; + //uint16 imm; + //uint16 val; + + //if (opc & 0xf) + //{ + // ErrorLog("dsp_opc_andf"); + //} + + //reg = 0x1e + ((opc >> 8) & 0x1); + //imm = FetchOpcode(); + //val = g_dsp.r[reg]; + + //if ((val & imm) == 0) + //{ + // g_dsp.r[R_SR] |= 0x40; + //} + //else + //{ + // g_dsp.r[R_SR] &= ~0x40; + //} +} + + +void dsp_opc_subf(uint16 opc) +{ + if (opc & 0xf) + { + ErrorLog("dsp_opc_subf"); + } + + uint8 reg = 0x1e + ((opc >> 8) & 0x1); + sint64 imm = (sint16)FetchOpcode(); + + OutBuffer::AddCode("missing: dsp_opc_subf"); + + //sint64 val = (sint16)g_dsp.r[reg]; + //sint64 res = val - imm; + + //Update_SR_Register(res); +} + + +void dsp_opc_xori(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_xori"); + + //if (opc & 0xf) + //{ + // ErrorLog("dsp_opc_xori"); + //} + + //uint8 reg = 0x1e + ((opc >> 8) & 0x1); + //uint16 imm = FetchOpcode(); + //g_dsp.r[reg] ^= imm; + + //Update_SR_Register((sint16)g_dsp.r[reg]); +} + + +void dsp_opc_andi(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_andi"); + + //if (opc & 0xf) + //{ + // ErrorLog("dsp_opc_andi"); + //} + + //uint8 reg = 0x1e + ((opc >> 8) & 0x1); + //uint16 imm = FetchOpcode(); + //g_dsp.r[reg] &= imm; + + //Update_SR_Register((sint16)g_dsp.r[reg]); +} + + +// F|RES: i am not sure if this shouldnt be the whole ACC +// +void dsp_opc_ori(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_ori"); + + //if (opc & 0xf) + //{ + // return(ErrorLog("dsp_opc_ori")); + //} + + //uint8 reg = 0x1e + ((opc >> 8) & 0x1); + //uint16 imm = FetchOpcode(); + //g_dsp.r[reg] |= imm; + + //Update_SR_Register((sint16)g_dsp.r[reg]); +} + + +//------------------------------------------------------------- + +void dsp_opc_add(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_add"); + + //uint8 areg = (opc >> 8) & 0x1; + //sint64 acc0 = dsp_get_long_acc(0); + //sint64 acc1 = dsp_get_long_acc(1); + + //sint64 res = acc0 + acc1; + + //dsp_set_long_acc(areg, res); + + //Update_SR_Register(res); +} + + +//------------------------------------------------------------- + +void dsp_opc_addp(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_addp"); + + //uint8 dreg = (opc >> 8) & 0x1; + //sint64 acc = dsp_get_long_acc(dreg); + //acc = acc + dsp_get_long_prod(); + //dsp_set_long_acc(dreg, acc); + + //Update_SR_Register(acc); +} + + +void dsp_opc_cmpis(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_cmpis"); + + //uint8 areg = (opc >> 8) & 0x1; + + //sint64 acc = dsp_get_long_acc(areg); + //sint64 val = (sint8)opc; + //val <<= 16; + + //sint64 res = acc - val; + + //Update_SR_Register(res); +} + + +// NEW +// verified at the console +void dsp_opc_addpaxz(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_addpaxz"); + + //uint8 dreg = (opc >> 8) & 0x1; + //uint8 sreg = (opc >> 9) & 0x1; + + //sint64 prod = dsp_get_long_prod() & ~0x0ffff; + //sint64 ax_h = dsp_get_long_acx(sreg); + //sint64 acc = (prod + ax_h) & ~0x0ffff; + + //dsp_set_long_acc(dreg, acc); + + //Update_SR_Register(acc); +} + + +// NEW +void dsp_opc_movpz(uint16 opc) +{ + uint8 dreg = (opc >> 8) & 0x01; + + OutBuffer::AddCode("ACC%i = PROD & ~0xffff", dreg); + OutBuffer::AddCode("Update_SR_Register(ACC%i)", dreg); + + //// overwrite acc and clear low part + //sint64 prod = dsp_get_long_prod(); + //sint64 acc = prod & ~0xffff; + //dsp_set_long_acc(dreg, acc); + + //Update_SR_Register(acc); +} + + +void dsp_opc_decm(uint16 opc) +{ + uint8 dreg = (opc >> 8) & 0x01; + + OutBuffer::AddCode("ACC%i -= 0x10000", dreg); + OutBuffer::AddCode("Update_SR_Register(ACC%i)", dreg); + + //sint64 sub = 0x10000; + //sint64 acc = dsp_get_long_acc(dreg); + //acc -= sub; + //dsp_set_long_acc(dreg, acc); + + //Update_SR_Register(acc); +} + + +void dsp_opc_dec(uint16 opc) +{ + uint8 dreg = (opc >> 8) & 0x01; + + OutBuffer::AddCode("ACC%i -= 1", dreg); + OutBuffer::AddCode("Update_SR_Register(ACC%i)", dreg); + + //sint64 acc = dsp_get_long_acc(dreg) - 1; + //dsp_set_long_acc(dreg, acc); + + //Update_SR_Register(acc); +} + + +void dsp_opc_incm(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_incm"); + + //uint8 dreg = (opc >> 8) & 0x1; + + //sint64 sub = 0x10000; + //sint64 acc = dsp_get_long_acc(dreg); + //acc += sub; + //dsp_set_long_acc(dreg, acc); + + //Update_SR_Register(acc); +} + + +void dsp_opc_inc(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_inc"); + + //uint8 dreg = (opc >> 8) & 0x1; + + //sint64 acc = dsp_get_long_acc(dreg); + //acc++; + //dsp_set_long_acc(dreg, acc); + + //Update_SR_Register(acc); +} + + +void dsp_opc_neg(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_neg"); + + //uint8 areg = (opc >> 8) & 0x1; + + //sint64 acc = dsp_get_long_acc(areg); + //acc = 0 - acc; + //dsp_set_long_acc(areg, acc); + + //Update_SR_Register(acc); +} + + +void dsp_opc_movnp(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_movnp"); + + ErrorLog("dsp_opc_movnp\n"); +} + + +// NEW +void dsp_opc_addax(uint16 opc) +{ + // OutBuffer::AddCode("missing: dsp_opc_addax"); + + uint8 areg = (opc >> 8) & 0x1; + uint8 sreg = (opc >> 9) & 0x1; + + OutBuffer::AddCode("ACC%i += AX%i", areg, sreg); + OutBuffer::AddCode("Update_SR_Register(ACC%i)", areg); + + //sint64 ax = dsp_get_long_acx(sreg); + //sint64 acc = dsp_get_long_acc(areg); + //acc += ax; + //dsp_set_long_acc(areg, acc); + + //Update_SR_Register(acc); +} + + +void dsp_opc_addr(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_addr"); + + //uint8 areg = (opc >> 8) & 0x1; + //uint8 sreg = ((opc >> 9) & 0x3) + 0x18; + + //sint64 ax = (sint16)g_dsp.r[sreg]; + //ax <<= 16; + + //sint64 acc = dsp_get_long_acc(areg); + //acc += ax; + //dsp_set_long_acc(areg, acc); + + //Update_SR_Register(acc); +} + + +void dsp_opc_subr(uint16 opc) +{ + uint8 areg = (opc >> 8) & 0x1; + uint8 sreg = ((opc >> 9) & 0x3) + 0x18; + + OutBuffer::AddCode("ACC%i -= (sint64)((sint16)%s << 16)", areg, OutBuffer::GetRegName(sreg)); + OutBuffer::AddCode("Update_SR_Register(ACC%i)", areg); + + //sint64 ax = (sint16)g_dsp.r[sreg]; + //ax <<= 16; + + //sint64 acc = dsp_get_long_acc(areg); + //acc -= ax; + //dsp_set_long_acc(areg, acc); + + //Update_SR_Register(acc); +} + +// NEW +void dsp_opc_subax(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_subax"); + + //int regD = (opc >> 8) & 0x1; + //int regT = (opc >> 9) & 0x1; + + //sint64 Acc = dsp_get_long_acc(regD) - dsp_get_long_acx(regT); + + //dsp_set_long_acc(regD, Acc); + //Update_SR_Register(Acc); +} + +void dsp_opc_addis(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_addis"); + + //uint8 areg = (opc >> 8) & 0x1; + + //sint64 Imm = (sint8)opc; + //Imm <<= 16; + //sint64 acc = dsp_get_long_acc(areg); + //acc += Imm; + //dsp_set_long_acc(areg, acc); + + //Update_SR_Register(acc); +} + + +void dsp_opc_addi(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_addi"); + + //uint8 areg = (opc >> 8) & 0x1; + + //sint64 sub = (sint16)FetchOpcode(); + //sub <<= 16; + //sint64 acc = dsp_get_long_acc(areg); + //acc += sub; + //dsp_set_long_acc(areg, acc); + + //Update_SR_Register(acc); +} + + +void dsp_opc_lsl16(uint16 opc) +{ + uint8 areg = (opc >> 8) & 0x1; + + OutBuffer::AddCode("ACC%i <<= 16", areg); + OutBuffer::AddCode("Update_SR_Register(ACC%i)", areg); + + //sint64 acc = dsp_get_long_acc(areg); + //acc <<= 16; + //dsp_set_long_acc(areg, acc); + + //Update_SR_Register(acc); +} + + +// NEW +void dsp_opc_madd(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_madd"); + + //uint8 sreg = (opc >> 8) & 0x1; + + //sint64 prod = dsp_get_long_prod(); + //prod += (sint64)dsp_get_ax_l(sreg) * (sint64)dsp_get_ax_h(sreg) * GetMultiplyModifier(); + //dsp_set_long_prod(prod); +} + + +void dsp_opc_lsr16(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_lsr16"); + + //uint8 areg = (opc >> 8) & 0x1; + + //sint64 acc = dsp_get_long_acc(areg); + //acc >>= 16; + //dsp_set_long_acc(areg, acc); + + //Update_SR_Register(acc); +} + + +void dsp_opc_asr16(uint16 opc) +{ + uint8 areg = (opc >> 11) & 0x1; + + OutBuffer::AddCode("ACC%i >>= 16", areg); + OutBuffer::AddCode("Update_SR_Register(ACC%i)", areg); + + //sint64 acc = dsp_get_long_acc(areg); + //acc >>= 16; + //dsp_set_long_acc(areg, acc); + + //Update_SR_Register(acc); +} + + +union UOpcodeShifti +{ + uint16 Hex; + struct + { + signed shift : 6; + unsigned negating : 1; + unsigned arithmetic : 1; + unsigned areg : 1; + unsigned op : 7; + }; + struct + { + unsigned ushift : 6; + }; + UOpcodeShifti(uint16 _Hex) + : Hex(_Hex) {} +}; + +void dsp_opc_shifti(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_shifti"); + + //UOpcodeShifti Opcode(opc); + + //// direction: left + //bool ShiftLeft = true; + //uint16 shift = Opcode.ushift; + + //if ((Opcode.negating) && (Opcode.shift < 0)) + //{ + // ShiftLeft = false; + // shift = -Opcode.shift; + //} + + //sint64 acc; + //uint64 uacc; + + //if (Opcode.arithmetic) + //{ + // // arithmetic shift + // uacc = dsp_get_long_acc(Opcode.areg); + + // if (!ShiftLeft) + // { + // uacc >>= shift; + // } + // else + // { + // uacc <<= shift; + // } + + // acc = uacc; + //} + //else + //{ + // acc = dsp_get_long_acc(Opcode.areg); + + // if (!ShiftLeft) + // { + // acc >>= shift; + // } + // else + // { + // acc <<= shift; + // } + //} + + //dsp_set_long_acc(Opcode.areg, acc); + + //Update_SR_Register(acc); +} + + +//------------------------------------------------------------- +// hcs give me this code!! +void dsp_opc_dar(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_dar"); + + //uint8 reg = opc & 0x3; + + //int temp = g_dsp.r[reg] + g_dsp.r[8]; + + //if (temp <= 0x7ff){g_dsp.r[reg] = temp;} + //else {g_dsp.r[reg]--;} +} + + +// hcs give me this code!! +void dsp_opc_iar(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_iar"); + + //uint8 reg = opc & 0x3; + + //int temp = g_dsp.r[reg] + g_dsp.r[8]; + + //if (temp <= 0x7ff){g_dsp.r[reg] = temp;} + //else {g_dsp.r[reg]++;} +} + + +//------------------------------------------------------------- + +void dsp_opc_sbclr(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_sbclr"); + + //uint8 bit = (opc & 0xff) + 6; + //g_dsp.r[R_SR] &= ~(1 << bit); +} + + +void dsp_opc_sbset(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_sbset"); + + //uint8 bit = (opc & 0xff) + 6; + //g_dsp.r[R_SR] |= (1 << bit); +} + + +void dsp_opc_srbith(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_srbith"); + +// switch ((opc >> 8) & 0xf) +// { +// case 0xe: // SET40 +// g_dsp.r[R_SR] &= ~(1 << 14); +// break; +// +///* case 0xf: // SET16 // that doesnt happen on a real console +// g_dsp.r[R_SR] |= (1 << 14); +// break;*/ +// +// default: +// break; +// } +} + + +//------------------------------------------------------------- + +void dsp_opc_movp(uint16 opc) +{ + uint8 dreg = (opc >> 8) & 0x1; + + OutBuffer::AddCode("ACC%i = PROD", dreg); + + //sint64 prod = dsp_get_long_prod(); + //sint64 acc = prod; + //dsp_set_long_acc(dreg, acc); +} + + +void dsp_opc_mul(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_mul"); + + //uint8 sreg = (opc >> 11) & 0x1; + //sint64 prod = (sint64)dsp_get_ax_h(sreg) * (sint64)dsp_get_ax_l(sreg) * GetMultiplyModifier(); + + //dsp_set_long_prod(prod); + + //Update_SR_Register(prod); +} + +// NEW +void dsp_opc_mulac(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_mulac"); + + //// add old prod to acc + //uint8 rreg = (opc >> 8) & 0x1; + //sint64 acR = dsp_get_long_acc(rreg) + dsp_get_long_prod(); + //dsp_set_long_acc(rreg, acR); + + //// math new prod + //uint8 sreg = (opc >> 11) & 0x1; + //sint64 prod = dsp_get_ax_l(sreg) * dsp_get_ax_h(sreg) * GetMultiplyModifier(); + //dsp_set_long_prod(prod); + + //Update_SR_Register(prod); +} + + +void dsp_opc_mulmv(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_mulmv"); + + //uint8 rreg = (opc >> 8) & 0x1; + //sint64 prod = dsp_get_long_prod(); + //sint64 acc = prod; + //dsp_set_long_acc(rreg, acc); + + //uint8 areg = ((opc >> 11) & 0x1) + 0x18; + //uint8 breg = ((opc >> 11) & 0x1) + 0x1a; + //sint64 val1 = (sint16)g_dsp.r[areg]; + //sint64 val2 = (sint16)g_dsp.r[breg]; + + //prod = val1 * val2 * GetMultiplyModifier(); + + //dsp_set_long_prod(prod); + + //Update_SR_Register(prod); +} + + +// NEW +void dsp_opc_mulmvz(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_mulmvz"); + + //uint8 sreg = (opc >> 11) & 0x1; + //uint8 rreg = (opc >> 8) & 0x1; + + //// overwrite acc and clear low part + //sint64 prod = dsp_get_long_prod(); + //sint64 acc = prod & ~0xffff; + //dsp_set_long_acc(rreg, acc); + + //// math prod + //prod = (sint64)g_dsp.r[0x18 + sreg] * (sint64)g_dsp.r[0x1a + sreg] * GetMultiplyModifier(); + //dsp_set_long_prod(prod); + + //Update_SR_Register(prod); +} + + +// NEW +void dsp_opc_mulx(uint16 opc) +{ + // OutBuffer::AddCode("missing: dsp_opc_mulx"); + + uint8 sreg = ((opc >> 12) & 0x1); + uint8 treg = ((opc >> 11) & 0x1); + + OutBuffer::AddCode("PROD = %s * %s * MultiplyModifier", (sreg == 0) ? "AX0_l" : "AX0_h", + (treg == 0) ? "AX1_l" : "AX1_h"); + OutBuffer::AddCode("Update_SR_Register(PROD)"); + + //sint64 val1 = (sreg == 0) ? dsp_get_ax_l(0) : dsp_get_ax_h(0); + //sint64 val2 = (treg == 0) ? dsp_get_ax_l(1) : dsp_get_ax_h(1); + + //sint64 prod = val1 * val2 * GetMultiplyModifier(); + //dsp_set_long_prod(prod); + + //Update_SR_Register(prod); +} + + +// NEW +void dsp_opc_mulxac(uint16 opc) +{ + //// add old prod to acc + uint8 rreg = (opc >> 8) & 0x1; + //sint64 acR = dsp_get_long_acc(rreg) + dsp_get_long_prod(); + //dsp_set_long_acc(rreg, acR); + + OutBuffer::AddCode("ACC%i += PROD", rreg); + + //// math new prod + uint8 sreg = (opc >> 12) & 0x1; + uint8 treg = (opc >> 11) & 0x1; + + OutBuffer::AddCode("PROD = %s * %s * MultiplyModifier", (sreg == 0) ? "AX0_l" : "AX0_h", + (treg == 0) ? "AX1_l" : "AX1_h"); + OutBuffer::AddCode("Update_SR_Register(PROD)"); + + //sint64 val1 = (sreg == 0) ? dsp_get_ax_l(0) : dsp_get_ax_h(0); + //sint64 val2 = (treg == 0) ? dsp_get_ax_l(1) : dsp_get_ax_h(1); + + //sint64 prod = val1 * val2 * GetMultiplyModifier(); + //dsp_set_long_prod(prod); + + //Update_SR_Register(prod); +} + + +// NEW +void dsp_opc_mulxmv(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_mulxmv"); + + //// add old prod to acc + //uint8 rreg = ((opc >> 8) & 0x1); + //sint64 acR = dsp_get_long_prod(); + //dsp_set_long_acc(rreg, acR); + + //// math new prod + //uint8 sreg = (opc >> 12) & 0x1; + //uint8 treg = (opc >> 11) & 0x1; + + //sint64 val1 = (sreg == 0) ? dsp_get_ax_l(0) : dsp_get_ax_h(0); + //sint64 val2 = (treg == 0) ? dsp_get_ax_l(1) : dsp_get_ax_h(1); + + //sint64 prod = val1 * val2 * GetMultiplyModifier(); + //dsp_set_long_prod(prod); + + //Update_SR_Register(prod); +} + + +// NEW +void dsp_opc_mulxmvz(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_mulxmvz"); + + //// overwrite acc and clear low part + //uint8 rreg = (opc >> 8) & 0x1; + //sint64 prod = dsp_get_long_prod(); + //sint64 acc = prod & ~0xffff; + //dsp_set_long_acc(rreg, acc); + + //// math prod + //uint8 sreg = (opc >> 12) & 0x1; + //uint8 treg = (opc >> 11) & 0x1; + + //sint64 val1 = (sreg == 0) ? dsp_get_ax_l(0) : dsp_get_ax_h(0); + //sint64 val2 = (treg == 0) ? dsp_get_ax_l(1) : dsp_get_ax_h(1); + + //prod = val1 * val2 * GetMultiplyModifier(); + //dsp_set_long_prod(prod); + + //Update_SR_Register(prod); +} + + +// NEW +void dsp_opc_sub(uint16 opc) +{ + uint8 D = (opc >> 8) & 0x1; + + OutBuffer::AddCode("ACC%i -= ACC%i", D, 1-D); + + //sint64 Acc1 = dsp_get_long_acc(D); + //sint64 Acc2 = dsp_get_long_acc(1 - D); + + //Acc1 -= Acc2; + + //dsp_set_long_acc(D, Acc1); +} + + +//------------------------------------------------------------- +// +// --- Table E +// +//------------------------------------------------------------- + +// NEW +void dsp_opc_maddx(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_maddx"); + + //uint8 sreg = (opc >> 9) & 0x1; + //uint8 treg = (opc >> 8) & 0x1; + + //sint64 val1 = (sreg == 0) ? dsp_get_ax_l(0) : dsp_get_ax_h(0); + //sint64 val2 = (treg == 0) ? dsp_get_ax_l(1) : dsp_get_ax_h(1); + + //sint64 prod = dsp_get_long_prod(); + //prod += val1 * val2 * GetMultiplyModifier(); + //dsp_set_long_prod(prod); +} + + +// NEW +void dsp_opc_msubx(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_msubx"); + + //uint8 sreg = (opc >> 9) & 0x1; + //uint8 treg = (opc >> 8) & 0x1; + + //sint64 val1 = (sreg == 0) ? dsp_get_ax_l(0) : dsp_get_ax_h(0); + //sint64 val2 = (treg == 0) ? dsp_get_ax_l(1) : dsp_get_ax_h(1); + + //sint64 prod = dsp_get_long_prod(); + //prod -= val1 * val2 * GetMultiplyModifier(); + //dsp_set_long_prod(prod); +} + + +// NEW +void dsp_opc_maddc(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_maddc"); + + //uint sreg = (opc >> 9) & 0x1; + //uint treg = (opc >> 8) & 0x1; + + //sint64 val1 = dsp_get_acc_m(sreg); + //sint64 val2 = dsp_get_ax_h(treg); + + //sint64 prod = dsp_get_long_prod(); + //prod += val1 * val2 * GetMultiplyModifier(); + //dsp_set_long_prod(prod); +} + + +// NEW +void dsp_opc_msubc(uint16 opc) +{ + OutBuffer::AddCode("missing: dsp_opc_msubc"); + + //uint sreg = (opc >> 9) & 0x1; + //uint treg = (opc >> 8) & 0x1; + + //sint64 val1 = dsp_get_acc_m(sreg); + //sint64 val2 = dsp_get_ax_h(treg); + + //sint64 prod = dsp_get_long_prod(); + //prod -= val1 * val2 * GetMultiplyModifier(); + //dsp_set_long_prod(prod); +} + + +//------------------------------------------------------------- +void dsp_op0(uint16 opc) +{ + if (opc == 0) + { + return; + } + + switch ((opc >> 8) & 0xf) + { + case 0x0: + + switch ((opc >> 4) & 0xf) + { + case 0x0: + + switch (opc & 0xf) + { + case 0x4: + case 0x5: + case 0x6: + case 0x7: + dsp_opc_dar(opc); + break; + + case 0x8: + case 0x9: + case 0xa: + case 0xb: + dsp_opc_iar(opc); + break; + + default: + ErrorLog("dsp_op0"); + break; + } + + break; + + case 0x1: + dsp_opc_addarn(opc); + break; + + case 0x2: // HALT + dsp_opc_halt(opc); + break; + + case 0x4: // LOOP + case 0x5: // LOOP + dsp_opc_loop(opc); + break; + + case 0x6: // BLOOP + case 0x7: // BLOOP + dsp_opc_bloop(opc); + break; + + case 0x8: // LRI + case 0x9: // LRI + dsp_opc_lri(opc); + break; + + case 0xC: // LR + case 0xD: // LR + dsp_opc_lr(opc); + break; + + case 0xE: // SR + case 0xF: // SR + dsp_opc_sr(opc); + break; + + default: + ErrorLog("dsp_op0"); + break; + } + + break; + + case 0x2: + + switch ((opc >> 4) & 0xf) + { + case 0x0: // ADDI + dsp_opc_addi(opc); + break; + + case 0x1: // IL + dsp_opc_ilrr(opc); + break; + + case 0x2: // XORI + dsp_opc_xori(opc); + break; + + case 0x4: // ANDI + dsp_opc_andi(opc); + break; + + case 0x6: // ORI + dsp_opc_ori(opc); + break; + + case 0x7: // + dsp_opc_ifcc(opc); + break; + + case 0x8: // SUBF + dsp_opc_subf(opc); + break; + + case 0x9: // Jxx + dsp_opc_jcc(opc); + break; + + case 0xa: // ANDF + dsp_opc_andf(opc); + break; + + case 0xb: // CALL + dsp_opc_call(opc); + break; + + case 0xc: + dsp_opc_andfc(opc); + break; + + case 0xd: // RET + dsp_opc_ret(opc); + break; + + case 0xf: // RTI + dsp_opc_rti(opc); + break; + + default: + ErrorLog("dsp_op0"); + break; + } + + break; + + case 0x3: + + switch ((opc >> 4) & 0xf) + { + case 0x0: // ADDAI + dsp_opc_addi(opc); + break; + + case 0x1: // ILR + dsp_opc_ilrr(opc); + break; + + case 0x2: // XORI + dsp_opc_xori(opc); + break; + + case 0x4: // ANDI + dsp_opc_andi(opc); + break; + + case 0x6: // ORI + dsp_opc_ori(opc); + break; + + case 0x8: // SUBF + dsp_opc_subf(opc); + break; + + case 0xa: // ANDF + dsp_opc_andf(opc); + break; + + case 0xc: // ANDFC + dsp_opc_andfc(opc); + break; + + default: + ErrorLog("dsp_op0"); + break; + } + + break; + + case 0x4: + case 0x5: + dsp_opc_addis(opc); + break; + + case 0x6: // SUBISF + case 0x7: + dsp_opc_cmpis(opc); + break; + + case 0x8: // LRIS + case 0x9: + case 0xa: + case 0xb: + case 0xc: + case 0xd: + case 0xe: + case 0xf: + dsp_opc_lris(opc); + break; + + default: + ErrorLog("dsp_op0"); + break; + } +} + + +void dsp_op1(uint16 opc) +{ + switch ((opc >> 8) & 0xf) + { + case 0x0: + dsp_opc_loopi(opc); + break; + + case 0x1: // BLOOPI + dsp_opc_bloopi(opc); + break; + + case 0x2: // SBCLR + dsp_opc_sbclr(opc); + break; + + case 0x3: // SBSET + dsp_opc_sbset(opc); + break; + + case 0x4: // shifti + case 0x5: + dsp_opc_shifti(opc); + break; + + case 0x6: // SI + dsp_opc_si(opc); + break; + + case 0x7: // JMPA/CALLA + dsp_opc_jmpa(opc); + break; + + case 0x8: // LRRx + case 0x9: // LRRx + dsp_opc_lrr(opc); + break; + + case 0xa: // SRRx + case 0xb: // SRRx + dsp_opc_srr(opc); + break; + + case 0xc: // MRR + case 0xd: // MRR + case 0xe: // MRR + case 0xf: // MRR + dsp_opc_mrr(opc); + break; + + default: + ErrorLog("dsp_op1"); + break; + } +} + + +void dsp_op2(uint16 opc) +{ + // lrs, srs + uint8 reg = ((opc >> 8) & 0x7) + 0x18; + uint16 addr = (sint8) opc; + + if (opc & 0x0800) + { + OutBuffer::AddCode("WriteDMEM(%s, %s)", OutBuffer::GetMemName(addr), OutBuffer::GetRegName(reg)); + + // srs + // dsp_dmem_write(addr, g_dsp.r[reg]); + } + else + { + OutBuffer::AddCode("%s = ReadDMEM(%s)", OutBuffer::GetRegName(reg), OutBuffer::GetMemName(addr)); + + // lrs + // g_dsp.r[reg] = dsp_dmem_read(addr); + } +} + + +void dsp_op3(uint16 opc) +{ + dsp_op_ext_ops_pro(opc); + + switch ((opc >> 8) & 0xf) + { + case 0x0: + case 0x1: + case 0x2: + case 0x3: + dsp_opc_xorr(opc); + break; + + case 0x4: + case 0x5: + case 0x6: + case 0x7: + dsp_opc_andr(opc); + break; + + case 0x8: + case 0x9: + case 0xa: + case 0xb: + dsp_opc_orr(opc); + break; + + case 0xc: + case 0xd: + dsp_opc_andc(opc); + break; + + default: + ErrorLog("dsp_op3"); + break; + } + + dsp_op_ext_ops_epi(opc); +} + + +void dsp_op4(uint16 opc) +{ + dsp_op_ext_ops_pro(opc); + + switch ((opc >> 8) & 0xf) + { + case 0x0: + case 0x1: + case 0x2: + case 0x3: + case 0x4: + case 0x5: + case 0x6: + case 0x7: + dsp_opc_addr(opc); + break; + + case 0x8: + case 0x9: + case 0xa: + case 0xb: + dsp_opc_addax(opc); + break; + + case 0xc: + case 0xd: + dsp_opc_add(opc); + break; + + case 0xe: + case 0xf: + dsp_opc_addp(opc); + break; + + default: + ErrorLog("dsp_op4"); + break; + } + + dsp_op_ext_ops_epi(opc); +} + + +void dsp_op5(uint16 opc) +{ + dsp_op_ext_ops_pro(opc); + + switch ((opc >> 8) & 0xf) + { + case 0x0: + case 0x1: + case 0x2: + case 0x3: + case 0x4: + case 0x5: + case 0x6: + case 0x7: + dsp_opc_subr(opc); + break; + + case 0x8: + case 0x9: + case 0xa: + case 0xb: + dsp_opc_subax(opc); + break; + + case 0xc: + case 0xd: + dsp_opc_sub(opc); + break; + + default: + ErrorLog("dsp_op5: %x", (opc >> 8) & 0xf); + break; + } + + dsp_op_ext_ops_epi(opc); +} + + +void dsp_op6(uint16 opc) +{ + dsp_op_ext_ops_pro(opc); + + switch ((opc >> 8) & 0xf) + { + case 0x00: // MOVR + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + dsp_opc_movr(opc); + break; + + case 0x8: // MVAXA + case 0x9: + case 0xa: + case 0xb: + dsp_opc_movax(opc); + break; + + case 0xe: + case 0xf: + dsp_opc_movp(opc); + break; + + default: + ErrorLog("dsp_op6"); + break; + } + + dsp_op_ext_ops_epi(opc); +} + + +void dsp_op7(uint16 opc) +{ + dsp_op_ext_ops_pro(opc); + + switch ((opc >> 8) & 0xf) + { + case 0x0: + case 0x1: + case 0x2: + case 0x3: + dsp_opc_addaxl(opc); + break; + + case 0x4: + case 0x5: + dsp_opc_incm(opc); + break; + + case 0x6: + case 0x7: + dsp_opc_inc(opc); + break; + + case 0x8: + case 0x9: + dsp_opc_decm(opc); + break; + + case 0xa: + case 0xb: + dsp_opc_dec(opc); + break; + + case 0xc: + case 0xd: + dsp_opc_neg(opc); + break; + + case 0xe: + case 0xf: + dsp_opc_movnp(opc); + break; + + default: + ErrorLog("dsp_op7"); + break; + } + + dsp_op_ext_ops_epi(opc); +} + + +void dsp_op8(uint16 opc) +{ + dsp_op_ext_ops_pro(opc); + + switch ((opc >> 8) & 0xf) + { + case 0x0: + case 0x8: + dsp_opc_nx(opc); + break; + + case 0x1: // CLR 0 + case 0x9: // CLR 1 + dsp_opc_clr(opc); + break; + + case 0x2: // CMP + dsp_opc_cmp(opc); + break; + + case 0x4: // CLRP + dsp_opc_clrp(opc); + break; + + case 0x6: + case 0x7: + dsp_opc_tstaxh(opc); + break; + + case 0xc: + case 0xb: + case 0xe: // SET40 + case 0xd: + case 0xa: + case 0xf: + dsp_opc_srbith(opc); + break; + + default: + ErrorLog("dsp_op8"); + break; + } + + dsp_op_ext_ops_epi(opc); +} + + +void dsp_op9(uint16 opc) +{ + dsp_op_ext_ops_pro(opc); + + switch ((opc >> 8) & 0xf) + { + case 0x02: + case 0x03: + case 0x0a: + case 0x0b: + dsp_opc_mulmvz(opc); + break; + + case 0x04: + case 0x05: + case 0x0c: + case 0x0d: + dsp_opc_mulac(opc); + break; + + case 0x6: + case 0x7: + case 0xe: + case 0xf: + dsp_opc_mulmv(opc); + break; + + case 0x0: + case 0x8: + dsp_opc_mul(opc); + break; + + case 0x1: + case 0x9: + dsp_opc_asr16(opc); + break; + + default: + ErrorLog("dsp_op9"); + break; + } + + dsp_op_ext_ops_epi(opc); +} + + +void dsp_opab(uint16 opc) +{ + dsp_op_ext_ops_pro(opc); + + switch ((opc >> 8) & 0x7) + { + case 0x0: + dsp_opc_mulx(opc); + break; + + case 0x1: + dsp_opc_tsta(opc); + break; + + case 0x2: + case 0x3: + dsp_opc_mulxmvz(opc); + break; + + case 0x4: + case 0x5: + dsp_opc_mulxac(opc); + break; + + case 0x6: + case 0x7: + dsp_opc_mulxmv(opc); + break; + + default: + ErrorLog("dsp_opab"); + } + + dsp_op_ext_ops_epi(opc); +} + + +void dsp_opcd(uint16 opc) +{ + dsp_op_ext_ops_pro(opc); + + switch ((opc >> 8) & 0x7) + { + case 0x0: // MULC + dsp_opc_mulc(opc); + break; + + case 0x1: // CMPAR + dsp_opc_cmpar(opc); + break; + + case 0x2: // MULCMVZ + case 0x3: + dsp_opc_mulcmvz(opc); + break; + + case 0x4: // MULCAC + case 0x5: + dsp_opc_mulcac(opc); + break; + + case 0x6: // MULCMV + case 0x7: + dsp_opc_mulcmv(opc); + break; + + default: + ErrorLog("dsp_opcd"); + } + + dsp_op_ext_ops_epi(opc); +} + + +void dsp_ope(uint16 opc) +{ + dsp_op_ext_ops_pro(opc); + + switch ((opc >> 10) & 0x3) + { + case 0x00: // MADDX + dsp_opc_maddx(opc); + break; + + case 0x01: // MSUBX + dsp_opc_msubx(opc); + break; + + case 0x02: // MADDC + dsp_opc_maddc(opc); + break; + + case 0x03: // MSUBC + dsp_opc_msubc(opc); + break; + + default: + ErrorLog("dsp_ope"); + } + + dsp_op_ext_ops_epi(opc); +} + + +void dsp_opf(uint16 opc) +{ + dsp_op_ext_ops_pro(opc); + + switch ((opc >> 8) & 0xf) + { + case 0x0: + case 0x1: + dsp_opc_lsl16(opc); + break; + + case 0x02: + case 0x03: + dsp_opc_madd(opc); + break; + + case 0x4: + case 0x5: + dsp_opc_lsr16(opc); + break; + + case 0x8: + case 0x9: + case 0xa: + case 0xb: + dsp_opc_addpaxz(opc); + break; + + case 0xe: + case 0xf: + dsp_opc_movpz(opc); + break; + + default: + ErrorLog("dsp_opf"); + break; + } + + dsp_op_ext_ops_epi(opc); +} + + diff --git a/docs/DSP/DSP_InterC/DSP_InterC/DSPOpcodes.h b/docs/DSP/DSP_InterC/DSP_InterC/DSPOpcodes.h new file mode 100644 index 0000000000..ec250031b6 --- /dev/null +++ b/docs/DSP/DSP_InterC/DSP_InterC/DSPOpcodes.h @@ -0,0 +1,48 @@ +/*==================================================================== + + filename: gdsp_opcodes.h + project: GCemu + created: 2004-6-18 + mail: duddie@walla.com + + Copyright (c) 2005 Duddie & Tratax + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License + as published by the Free Software Foundation; either version 2 + of the License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + + ====================================================================*/ +#ifndef _GDSP_OPCODES_H +#define _GDSP_OPCODES_H + +void dsp_op0(uint16 opc); +void dsp_op1(uint16 opc); +void dsp_op2(uint16 opc); +void dsp_op3(uint16 opc); +void dsp_op4(uint16 opc); +void dsp_op5(uint16 opc); +void dsp_op6(uint16 opc); +void dsp_op7(uint16 opc); +void dsp_op8(uint16 opc); +void dsp_op9(uint16 opc); +void dsp_opab(uint16 opc); +void dsp_opcd(uint16 opc); +void dsp_ope(uint16 opc); +void dsp_opf(uint16 opc); + + +#define R_SR 0x13 + +#define FLAG_ENABLE_INTERUPT 11 + +#endif diff --git a/docs/DSP/DSP_InterC/DSP_InterC/DSP_InterC.cpp b/docs/DSP/DSP_InterC/DSP_InterC/DSP_InterC.cpp new file mode 100644 index 0000000000..31c88990e1 --- /dev/null +++ b/docs/DSP/DSP_InterC/DSP_InterC/DSP_InterC.cpp @@ -0,0 +1,52 @@ +// DSP_InterC.cpp : Defines the entry point for the console application. +// + +#include "stdafx.h" + +#include "DSPOpcodes.h" + +uint16 g_IMemory[0x1000]; +uint16 g_currentAddress; + +uint16 FetchOpcode() +{ + uint16 value = swap16(g_IMemory[g_currentAddress & 0x0FFF]); + g_currentAddress++; + return value; +} + +void DecodeOpcode(uint16 op); + +void Decode(uint16 startAddress, uint16 endAddress) +{ + g_currentAddress = startAddress; + + while (g_currentAddress < endAddress) + { + uint16 oldPC = g_currentAddress; + uint16 op = FetchOpcode(); + + OutBuffer::Add("// l_%4X:", oldPC); + DecodeOpcode(op); + } +} + + +int _tmain(int argc, _TCHAR* argv[]) +{ + FILE* pFile = fopen("c:\\_\\dsp_rom.bin", "rb"); + if (pFile == NULL) + return -1; + + fread(g_IMemory, 0x1000, 1, pFile); + fclose(pFile); + + + ////// + OutBuffer::Init(); + Decode(0x80e7, 0x81f9); + + + return 0; +} + diff --git a/docs/DSP/DSP_InterC/DSP_InterC/DSP_InterC.vcproj b/docs/DSP/DSP_InterC/DSP_InterC/DSP_InterC.vcproj new file mode 100644 index 0000000000..ec800df5b6 --- /dev/null +++ b/docs/DSP/DSP_InterC/DSP_InterC/DSP_InterC.vcproj @@ -0,0 +1,249 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/docs/DSP/DSP_InterC/DSP_InterC/OutBuffer.cpp b/docs/DSP/DSP_InterC/DSP_InterC/OutBuffer.cpp new file mode 100644 index 0000000000..e8a6673ee5 --- /dev/null +++ b/docs/DSP/DSP_InterC/DSP_InterC/OutBuffer.cpp @@ -0,0 +1,155 @@ +// stdafx.cpp : source file that includes just the standard includes +// DSP_InterC.pch will be the pre-compiled header +// stdafx.obj will contain the pre-compiled type information + +#include "stdafx.h" + +#include +#include + +namespace OutBuffer +{ + void Init() + { + + } + + void Add(const char* _fmt, ...) + { + static char Msg[2048]; + va_list ap; + + va_start(ap, _fmt); + vsprintf(Msg, _fmt, ap); + va_end(ap); + + printf("%s\n", Msg); + } + + void AddCode(const char* _fmt, ...) + { + static char Msg[2048]; + va_list ap; + + va_start(ap, _fmt); + vsprintf(Msg, _fmt, ap); + va_end(ap); + + printf(" %s;\n", Msg); + } + + // predefined labels + typedef struct pdlabel_t + { + uint16 addr; + const char* name; + const char* description; + } pdlabels_t; + + pdlabel_t regnames[] = + { + {0x00, "R00", "Register 00",}, + {0x01, "R01", "Register 01",}, + {0x02, "R02", "Register 02",}, + {0x03, "R03", "Register 03",}, + {0x04, "R04", "Register 04",}, + {0x05, "R05", "Register 05",}, + {0x06, "R06", "Register 06",}, + {0x07, "R07", "Register 07",}, + {0x08, "R08", "Register 08",}, + {0x09, "R09", "Register 09",}, + {0x0a, "R10", "Register 10",}, + {0x0b, "R11", "Register 11",}, + {0x0c, "ST0", "Call stack",}, + {0x0d, "ST1", "Data stack",}, + {0x0e, "ST2", "Loop address stack",}, + {0x0f, "ST3", "Loop counter",}, + {0x00, "ACH0", "Accumulator High 0",}, + {0x11, "ACH1", "Accumulator High 1",}, + {0x12, "CR", "Config Register",}, + {0x13, "SR", "Special Register",}, + {0x14, "PROD_l", "PROD L",}, + {0x15, "PROD_m1", "PROD M1",}, + {0x16, "PROD_h", "PROD H",}, + {0x17, "PROD_m2", "PROD M2",}, + {0x18, "AX0_l", "Additional Accumulators Low 0",}, + {0x19, "AX1_l", "Additional Accumulators Low 1",}, + {0x1a, "AX0_h", "Additional Accumulators High 0",}, + {0x1b, "AX1_h", "Additional Accumulators High 1",}, + {0x1c, "AC0_l", "Register 28",}, + {0x1d, "AC1_l", "Register 29",}, + {0x1e, "AC0_m", "Register 00",}, + {0x1f, "AC1_m", "Register 00",}, + + // additional to resolve special names + {0x20, "ACC0", "Accumulators 0",}, + {0x21, "ACC1", "Accumulators 1",}, + {0x22, "AX0", "Additional Accumulators 0",}, + {0x23, "AX1", "Additional Accumulators 1",}, + }; + + const pdlabel_t pdlabels[] = + { + {0xffa0, "COEF_A1_0", "COEF_A1_0",}, + {0xffa1, "COEF_A2_0", "COEF_A2_0",}, + {0xffa2, "COEF_A1_1", "COEF_A1_1",}, + {0xffa3, "COEF_A2_1", "COEF_A2_1",}, + {0xffa4, "COEF_A1_2", "COEF_A1_2",}, + {0xffa5, "COEF_A2_2", "COEF_A2_2",}, + {0xffa6, "COEF_A1_3", "COEF_A1_3",}, + {0xffa7, "COEF_A2_3", "COEF_A2_3",}, + {0xffa8, "COEF_A1_4", "COEF_A1_4",}, + {0xffa9, "COEF_A2_4", "COEF_A2_4",}, + {0xffaa, "COEF_A1_5", "COEF_A1_5",}, + {0xffab, "COEF_A2_5", "COEF_A2_5",}, + {0xffac, "COEF_A1_6", "COEF_A1_6",}, + {0xffad, "COEF_A2_6", "COEF_A2_6",}, + {0xffae, "COEF_A1_7", "COEF_A1_7",}, + {0xffaf, "COEF_A2_7", "COEF_A2_7",}, + {0xffc9, "DSCR", "DSP DMA Control Reg",}, + {0xffcb, "DSBL", "DSP DMA Block Length",}, + {0xffcd, "DSPA", "DSP DMA DMEM Address",}, + {0xffce, "DSMAH", "DSP DMA Mem Address H",}, + {0xffcf, "DSMAL", "DSP DMA Mem Address L",}, + {0xffd1, "SampleFormat", "SampleFormat",}, + + {0xffd3, "Unk Zelda", "Unk Zelda writes to it",}, + + {0xffd4, "ACSAH", "Accelerator start address H",}, + {0xffd5, "ACSAL", "Accelerator start address L",}, + {0xffd6, "ACEAH", "Accelerator end address H",}, + {0xffd7, "ACEAL", "Accelerator end address L",}, + {0xffd8, "ACCAH", "Accelerator current address H",}, + {0xffd9, "ACCAL", "Accelerator current address L",}, + {0xffda, "pred_scale", "pred_scale",}, + {0xffdb, "yn1", "yn1",}, + {0xffdc, "yn2", "yn2",}, + {0xffdd, "ARAM", "Direct Read from ARAM (uses ADPCM)",}, + {0xffde, "GAIN", "Gain",}, + {0xffef, "AMDM", "ARAM DMA Request Mask",}, + {0xfffb, "DIRQ", "DSP IRQ Request",}, + {0xfffc, "DMBH", "DSP Mailbox H",}, + {0xfffd, "DMBL", "DSP Mailbox L",}, + {0xfffe, "CMBH", "CPU Mailbox H",}, + {0xffff, "CMBL", "CPU Mailbox L",}, + }; + + const char* GetRegName(uint16 reg) + { + return regnames[reg].name; + } + + const char* GetMemName(uint16 addr) + { + static char Buffer[1024]; + for (int i=0; i 0); +} + + +// --------------------------------------------------------------------------------------- +// +// --- reg +// +// --------------------------------------------------------------------------------------- + +inline uint16 dsp_op_read_reg(uint8 reg) +{ + uint16 val; + + switch (reg & 0x1f) + { + case 0x0c: + case 0x0d: + case 0x0e: + case 0x0f: + val = dsp_reg_load_stack(reg - 0x0c); + break; + + default: + val = g_dsp.r[reg]; + break; + } + + return(val); +} + + +inline void dsp_op_write_reg(uint8 reg, uint16 val) +{ + switch (reg & 0x1f) + { + case 0x0c: + case 0x0d: + case 0x0e: + case 0x0f: + dsp_reg_store_stack(reg - 0x0c, val); + break; + + default: + g_dsp.r[reg] = val; + break; + } +} + + +// --------------------------------------------------------------------------------------- +// +// --- prod +// +// --------------------------------------------------------------------------------------- + + +inline sint64 dsp_get_long_prod() +{ + sint64 val; + sint64 low_prod; + val = (sint8)g_dsp.r[0x16]; + val <<= 32; + low_prod = g_dsp.r[0x15]; + low_prod += g_dsp.r[0x17]; + low_prod <<= 16; + low_prod |= g_dsp.r[0x14]; + val += low_prod; + return(val); +} + + +inline void dsp_set_long_prod(sint64 val) +{ + g_dsp.r[0x14] = (uint16)val; + val >>= 16; + g_dsp.r[0x15] = (uint16)val; + val >>= 16; + g_dsp.r[0x16] = (uint16)val; + g_dsp.r[0x17] = 0; +} + + +// --------------------------------------------------------------------------------------- +// +// --- acc +// +// --------------------------------------------------------------------------------------- + +inline sint64 dsp_get_long_acc(uint8 reg) +{ + _dbg_assert_(reg < 2); + sint64 val; + sint64 low_acc; + val = (sint8)g_dsp.r[0x10 + reg]; + val <<= 32; + low_acc = g_dsp.r[0x1e + reg]; + low_acc <<= 16; + low_acc |= g_dsp.r[0x1c + reg]; + val |= low_acc; + return(val); +} + + +inline uint64 dsp_get_ulong_acc(uint8 reg) +{ + _dbg_assert_(reg < 2); + uint64 val; + uint64 low_acc; + val = (uint8)g_dsp.r[0x10 + reg]; + val <<= 32; + low_acc = g_dsp.r[0x1e + reg]; + low_acc <<= 16; + low_acc |= g_dsp.r[0x1c + reg]; + val |= low_acc; + return(val); +} + + +inline void dsp_set_long_acc(uint8 _reg, sint64 val) +{ + _dbg_assert_(_reg < 2); + g_dsp.r[0x1c + _reg] = (uint16)val; + val >>= 16; + g_dsp.r[0x1e + _reg] = (uint16)val; + val >>= 16; + g_dsp.r[0x10 + _reg] = (uint16)val; +} + + +inline sint16 dsp_get_acc_l(uint8 _reg) +{ + _dbg_assert_(_reg < 2); + return(g_dsp.r[0x1c + _reg]); +} + + +inline sint16 dsp_get_acc_m(uint8 _reg) +{ + _dbg_assert_(_reg < 2); + return(g_dsp.r[0x1e + _reg]); +} + + +inline sint16 dsp_get_acc_h(uint8 _reg) +{ + _dbg_assert_(_reg < 2); + return(g_dsp.r[0x10 + _reg]); +} + + +// --------------------------------------------------------------------------------------- +// +// --- acx +// +// --------------------------------------------------------------------------------------- + + +inline sint64 dsp_get_long_acx(uint8 _reg) +{ + _dbg_assert_(_reg < 2); + sint64 val = (sint16)g_dsp.r[0x1a + _reg]; + val <<= 16; + sint64 low_acc = g_dsp.r[0x18 + _reg]; + val |= low_acc; + return(val); +} + + +inline sint16 dsp_get_ax_l(uint8 _reg) +{ + _dbg_assert_(_reg < 2); + return(g_dsp.r[0x18 + _reg]); +} + + +inline sint16 dsp_get_ax_h(uint8 _reg) +{ + _dbg_assert_(_reg < 2); + return(g_dsp.r[0x1a + _reg]); +} + + +#endif diff --git a/docs/DSP/DSP_InterC/DSP_InterC/stdafx.cpp b/docs/DSP/DSP_InterC/DSP_InterC/stdafx.cpp new file mode 100644 index 0000000000..6b8280251a --- /dev/null +++ b/docs/DSP/DSP_InterC/DSP_InterC/stdafx.cpp @@ -0,0 +1,23 @@ +// stdafx.cpp : source file that includes just the standard includes +// DSP_InterC.pch will be the pre-compiled header +// stdafx.obj will contain the pre-compiled type information + +#include "stdafx.h" + +// TODO: reference any additional headers you need in STDAFX.H +// and not in this file + +#include + +void ErrorLog(const char* _fmt, ...) +{ + char Msg[512]; + va_list ap; + + va_start(ap, _fmt); + vsprintf(Msg, _fmt, ap); + va_end(ap); + + printf("Error"); + +} \ No newline at end of file diff --git a/docs/DSP/DSP_InterC/DSP_InterC/stdafx.h b/docs/DSP/DSP_InterC/DSP_InterC/stdafx.h new file mode 100644 index 0000000000..1d7c35fd96 --- /dev/null +++ b/docs/DSP/DSP_InterC/DSP_InterC/stdafx.h @@ -0,0 +1,39 @@ +// stdafx.h : include file for standard system include files, +// or project specific include files that are used frequently, but +// are changed infrequently +// + +#pragma once + +#include "targetver.h" + +#include +#include + + + + + + +typedef unsigned char uint8; +typedef unsigned short uint16; +typedef unsigned int uint32; +typedef unsigned long long uint64; +typedef unsigned int uint; + +typedef signed char sint8; +typedef signed short sint16; +typedef signed int sint32; +typedef signed long long sint64; + +extern uint16 FetchOpcode(); +extern void ErrorLog(const char* _fmt, ...); + +inline uint16 swap16(uint16 x) +{ + return((x >> 8) | (x << 8)); +} + +#include "OutBuffer.h" + +// TODO: reference additional headers your program requires here diff --git a/docs/DSP/DSP_InterC/DSP_InterC/targetver.h b/docs/DSP/DSP_InterC/DSP_InterC/targetver.h new file mode 100644 index 0000000000..a38195a4ef --- /dev/null +++ b/docs/DSP/DSP_InterC/DSP_InterC/targetver.h @@ -0,0 +1,13 @@ +#pragma once + +// The following macros define the minimum required platform. The minimum required platform +// is the earliest version of Windows, Internet Explorer etc. that has the necessary features to run +// your application. The macros work by enabling all features available on platform versions up to and +// including the version specified. + +// Modify the following defines if you have to target a platform prior to the ones specified below. +// Refer to MSDN for the latest info on corresponding values for different platforms. +#ifndef _WIN32_WINNT // Specifies that the minimum required platform is Windows Vista. +#define _WIN32_WINNT 0x0600 // Change this to the appropriate value to target other versions of Windows. +#endif + diff --git a/docs/DSP/DSP_UC_Zelda.txt b/docs/DSP/DSP_UC_Zelda.txt new file mode 100644 index 0000000000..0bb019e729 --- /dev/null +++ b/docs/DSP/DSP_UC_Zelda.txt @@ -0,0 +1,3088 @@ +// Zelda UCode - CRC: 0x09CD143F + +// This is a disassembly done using an outdated disasm. Need to redisasm and transfer +// the comments. + +// This is a very complex little ucode. Quite a bit more so than AX. +// It also seems to use features of the DSP that AX neglects (the reverse is true as well, +// this ucode doesn't seem to use the hardware ADPCM feature at all, instead opting to +// decode a different ADPCM format manually). + +// The value 0x50 is VERY common as a loop size. Many, especially intermediate/output +// sample buffers seem to be of this size. Half that size, 0x28, is also seen. + +// MemMap + + +// 0x0400 to 0x04C0 - Some kind of CommandoBlock + + + +// exception vector +0000 029f 0012 JMP 0x0012 +0002 0000 NOP +0003 0000 NOP +0004 02ff RTI +0005 0000 NOP +0006 02ff RTI +0007 0000 NOP +0008 02ff RTI +0009 0000 NOP +000a 02ff RTI +000b 0000 NOP +000c 02ff RTI +000d 0000 NOP +000e 029f 05b8 JMP 0x05b8 + + +0010 029f 004e JMP 0x004e + +// Handler for 0000 exception (reset?) +0012 1205 SBCLR #0x05 // interesting, what is this flag? must be important. +0013 02bf 0057 CALL 0x0057 // InitHardware() + +// clear memory +0015 8100 CLR $AC0.M +0016 009f 1000 LRI $AC1.M, #0x1000 +0018 0080 0000 LRI $R00, #0x0000 +001a 005f LOOP $AC1.M +001b 1b1e SRRI @$R00, $AC0.M + +001c 02bf 0688 CALL 0x0688 // InitGlobalsVars() +001e 02bf 04c0 CALL 0x04c0 +0020 02bf 0e14 CALL 0x0e14 // Init some kind of table +0022 0e00 LRIS $AC0.M, #0x00 +0023 02bf 066a CALL 0x066a // SendMessageViaDSPMailBox_DCD1(AC0.M) +0025 009e 1111 LRI $AC0.M, #0x1111 +0027 02bf 0674 CALL 0x0674 // SendMessageViaDSPMailBox_F355(AC0.M) +0029 0e00 LRIS $AC0.M, #0x00 +002a 00fe 034e SR @0x034e, $AC0.M +002c 1305 SBSET #0x05 +002d 029f 06c5 JMP 0x06c5 -> jump to MessageLoop() + +// CommandHandler() +002f 00df 0357 LR $AC1.M, @0x0357 +0031 00ff 0345 SR @0x0345, $AC1.M +0033 00de 0356 LR $AC0.M, @0x0356 +0035 1ffe MRR $AC1.M, $AC0.M +0036 0340 00ff ANDI $ACC1, #0x00ff +0038 00ff 0344 SR @0x0344, $AC1.M +003a 1479 LSR $ACC0, #0x39 +003b 0240 007e ANDI $ACC0, #0x007e +003d 00fe 0343 SR @0x0343, $AC0.M +003f 0200 0075 ADDI $ACC0, #0x0075 // offset of "JMP Table Opcodes" +0041 1c1e MRR $R00, $AC0.M +0042 170f JMPR $R00 // JMP to OpcodeHandler +0043 0092 00ff LRI $CR, #0x00ff +0045 0e04 LRIS $AC0.M, #0x04 +0046 02bf 066a CALL 0x066a // SendMessageViaDSPMailBox_DCD1(AC0.M) +0048 00de 0356 LR $AC0.M, @0x0356 +004a 02bf 0674 CALL 0x0674 // SendMessageViaDSPMailBox_F355(AC0.M) +004c 029f 002d JMP 0x002d + + +// task start vector (0x0010) jumps here immediately. +004e 1205 SBCLR #0x05 +004f 02bf 0057 CALL 0x0057 // InitHardware() +0051 0e01 LRIS $AC0.M, #0x01 +0052 02bf 066a CALL 0x066a // SendMessageViaDSPMailBox_DCD1(AC0.M) +0054 1305 SBSET #0x05 +0055 029f 002d JMP 0x002d + + +// InitHardware() +0057 1202 SBCLR #0x02 +0058 1203 SBCLR #0x03 +0059 1204 SBCLR #0x04 +005a 1306 SBSET #0x06 +005b 8e00 S40 +005c 8c00 CLR15 +005d 8b00 M0 +// Initialize the loop index registers to #ffff to neutralize them. +005e 009e ffff LRI $AC0.M, #0xffff +0060 1d1e MRR $R08, $AC0.M +0061 1d3e MRR $R09, $AC0.M +0062 1d5e MRR $R10, $AC0.M +0063 1d7e MRR $R11, $AC0.M +0064 0092 00ff LRI $CR, #0x00ff +0066 02df RET + + +// ReadWholeMessage($R00) +0067 0090 0000 LRI $ACH0, #0x0000 +0069 0c00 LRIS $AC0.L, #0x00 +006a 0081 0358 LRI $R01, #0x0358 +006c 007e 0071 BLOOP $AC0.M, 0x0071 +006e 193e LRRI $AC0.M, @$R01 +006f 1b1e SRRI @$R00, $AC0.M +0070 193e LRRI $AC0.M, @$R01 +0071 1b1e SRRI @$R00, $AC0.M +0072 02df RET + +// Opcode_03() -> direct return +0073 029f 0043 JMP 0x0043 + +// JMP Table Opcodes +0075 029f 0043 JMP 0x0043 // dummy handler -> direct return +0077 029f 0095 JMP 0x0095 +0079 029f 0243 JMP 0x0243 +007b 029f 0073 JMP 0x0073 +007d 029f 0580 JMP 0x0580 +007f 029f 0592 JMP 0x0592 +0081 029f 0469 JMP 0x0469 +0083 029f 041d JMP 0x041d +0085 029f 0485 JMP 0x0485 +0087 029f 044d JMP 0x044d +0089 029f 0043 JMP 0x0043 // dummy handler -> direct return +008b 029f 0043 JMP 0x0043 // dummy handler -> direct return +008d 029f 0043 JMP 0x0043 // dummy handler -> direct return +008f 029f 00b2 JMP 0x00b2 +0091 029f 0043 JMP 0x0043 // dummy handler -> direct return +0093 029f 0043 JMP 0x0043 // dummy handler -> direct return + + +// Opcode_01() - DsetupTable() +0095 0080 0380 LRI $R00, #0x0380 +0097 0e04 LRIS $AC0.M, #0x04 +0098 02bf 0067 CALL 0x0067 // ReadWholeMessage($R00) +009a 0081 0382 LRI $R01, #0x0382 +009c 009f 0000 LRI $AC1.M, #0x0000 +009e 0080 0280 LRI $R00, #0x0280 +00a0 02bf 0523 CALL 0x0523 // RAMtoDMEM(DMEM=$AC1.M, *R01=MEMADDR, R00=Len) +00a2 0081 0384 LRI $R01, #0x0384 +00a4 009f 0300 LRI $AC1.M, #0x0300 +00a6 0080 0020 LRI $R00, #0x0020 +00a8 02bf 0523 CALL 0x0523 // RAMtoDMEM(DMEM=$AC1.M, *R01=MEMADDR, R00=Len) +00aa 00de 0345 LR $AC0.M, @0x0345 +00ac 00fe 0342 SR @0x0342, $AC0.M +00ae 02bf 0bec CALL 0x0bec +00b0 029f 0043 JMP 0x0043 + +// Opcode_0D() - DsetDolbyDelay +00b2 0080 0374 LRI $R00, #0x0374 +00b4 0e01 LRIS $AC0.M, #0x01 +00b5 00fe 0377 SR @0x0377, $AC0.M +00b7 00fe 037c SR @0x037c, $AC0.M +00b9 02bf 0067 CALL 0x0067 // ReadWholeMessage($R00) +00bb 00de 0345 LR $AC0.M, @0x0345 +00bd 00fe 0376 SR @0x0376, $AC0.M +00bf 029f 0043 JMP 0x0043 + +// Load some kind of command block with size C0 +00c1 0081 034c LRI $R01, #0x034c +00c3 009f 0400 LRI $AC1.M, #0x0400 +00c5 0080 00c0 LRI $R00, #0x00c0 +00c7 02bf 0523 CALL 0x0523 // RAMtoDMEM(DMEM=$AC1.M, *R01=MEMADDR, R00=Len) +00c9 02df RET + +// Copy something out. +00ca 0081 034c LRI $R01, #0x034c +00cc 009f 0400 LRI $AC1.M, #0x0400 +00ce 0080 0080 LRI $R00, #0x0080 +00d0 0081 034c LRI $R01, #0x034c +00d2 193e LRRI $AC0.M, @$R01 +00d3 193c LRRI $AC0.L, @$R01 +00d4 0098 0000 LRI $AX0.L, #0x0000 +00d6 7000 ADDAXL $AC0.M, $AX0.L +00d7 02bf 0532 CALL 0x0532 // DMEMtoRAM(DMEM=$AC1.M, AC0=MEMADDR, R00=Len) +00d9 02df RET + +// CopyMemory(LEN=$AC1.M, *R00=SRC, *R03=DEST) +// Hm, is it really? The MOVR loop doesn't involve R03. +00da 191e LRRI $AC0.M, @$R00 +00db 191a LRRI $AX0.H, @$R00 +00dc 005f LOOP $AC1.M +00dd 64a0 MOVR.LS $AC0.M, $AX0.H : $AX0.H, $AC0.M // ??? Does the .LS makes any sense? shouldnt it be just a load? um yeah it makes sense, that's a LOOP, not a BLOOP. wonder about the SRRIs though. +00de 1b7e SRRI @$R03, $AC0.M +00df 1b7a SRRI @$R03, $AX0.H +00e0 02df RET + +// Decrypt???? (btw, wonder if LRRI disasm is broken). +00e1 191e LRRI $AC0.M, @$R00 +00e2 191a LRRI $AX0.H, @$R00 +00e3 007f 00e8 BLOOP $AC1.M, 0x00e8 +00e5 32b2 XORR.SL $AC0.M, $AX1.H : $AC0.M, $AX1.H +00e6 65a0 MOVR.LS $AC1.M, $AX0.H : $AX0.H, $AC0.M +00e7 33ba XORR.SLM $AC1.M, $AX1.H : $AC0.M, $AX1.H +00e8 64a1 MOVR.LS $AC0.M, $AX0.H : $AX0.H, $AC1.M +00e9 0000 NOP +00ea 02df RET + +// Multiply loop of some kind... +// Reads from arrays pointed to by R00, R03 +// Writes to array pointed to by R00, i think - extensions are unclear. +// TODO: Figure out what LSR $ACC1, #0x3f means .. just a clear? +// Loop count in AC1.M. +00eb 8a00 M2 +00ec 157f LSR $ACC1, #0x3f +00ed 1c20 MRR $R01, $R00 +00ee 1c03 MRR $R00, $R03 +00ef 193a LRRI $AX0.H, @$R01 +00f0 9051 MUL.L $AX0.L, $AX0.H : $AX0.H, @$R01 +00f1 925b MULMVZ.L $AX0.L, $AX0.H, $AC0.M : $AX1.H, @$R03 +00f2 007f 00f7 BLOOP $AC1.M, 0x00f7 +00f4 4651 ADDR.L $AC0.M, $AX1.H : $AX0.H, @$R01 +00f5 92b2 MULMVZ.SL $AX0.L, $AX0.H, $AC0.M : $AC0.M, $AX1.H +00f6 4651 ADDR.L $AC0.M, $AX1.H : $AX0.H, @$R01 +00f7 92b2 MULMVZ.SL $AX0.L, $AX0.H, $AC0.M : $AC0.M, $AX1.H +00f8 8b00 M0 +00f9 02df RET + +// Another multiply loop of some kind .... +// Loop count in AC1.M. +00fa 8a00 M2 +00fb 191a LRRI $AX0.H, @$R00 +00fc 9050 MUL.L $AX0.L, $AX0.H : $AX0.H, @$R00 +00fd 9250 MULMVZ.L $AX0.L, $AX0.H, $AC0.M : $AX0.H, @$R00 +00fe 005f LOOP $AC1.M +00ff 92a0 MULMVZ.LS $AX0.L, $AX0.H, $AC0.M : $AX0.H, $AC0.M +0100 8b00 M0 +0101 02df RET + +// Clear some memory (called by op2) +0102 8100 CLR $AC0.M +0103 8900 CLR $AC1.M +0104 0e50 LRIS $AC0.M, #0x50 +0105 0080 0d00 LRI $R00, #0x0d00 +0107 005e LOOP $AC0.M +0108 1b1f SRRI @$R00, $AC1.M +0109 0080 0d60 LRI $R00, #0x0d60 +010b 005e LOOP $AC0.M +010c 1b1f SRRI @$R00, $AC1.M +010d 02bf 0e3f CALL 0x0e3f +010f 8100 CLR $AC0.M +0110 8900 CLR $AC1.M +0111 0e50 LRIS $AC0.M, #0x50 +0112 0080 0ca0 LRI $R00, #0x0ca0 +0114 005e LOOP $AC0.M +0115 1b1f SRRI @$R00, $AC1.M +0116 0080 0f40 LRI $R00, #0x0f40 +0118 005e LOOP $AC0.M +0119 1b1f SRRI @$R00, $AC1.M +011a 0080 0fa0 LRI $R00, #0x0fa0 +011c 005e LOOP $AC0.M +011d 1b1f SRRI @$R00, $AC1.M +011e 0080 0a00 LRI $R00, #0x0a00 +0120 005e LOOP $AC0.M +0121 1b1f SRRI @$R00, $AC1.M +0122 0080 09a0 LRI $R00, #0x09a0 +0124 005e LOOP $AC0.M +0125 1b1f SRRI @$R00, $AC1.M +0126 02df RET + + +// A function with multiplies that doesn't change the mode? +// Looks like a stereo mixer or something +0127 00c0 03a0 LR $R00, @0x03a0 +0129 191a LRRI $AX0.H, @$R00 +012a 00df 03a1 LR $AC1.M, @0x03a1 +012c 009b 00a0 LRI $AX1.H, #0x00a0 +012e 0081 0393 LRI $R01, #0x0393 +0130 18bc LRRD $AC0.L, @$R01 +0131 b871 MULX.L $AX0.H, $AX1.H : $AC0.M, @$R01 +0132 bc00 MULXAC $AX0.H, $AX1.H, $AC0.M +0133 0080 0050 LRI $R00, #0x0050 +0135 0508 ADDIS $ACC1, #0x08 +0136 02bf 0525 CALL 0x0525 // RAMtoDMEM(DMEM=$AC1.M, AC0=MEMADDR, R00=Len) +0138 00de 0390 LR $AC0.M, @0x0390 +013a 02a0 0001 ANDCF $AC0.M, #0x0001 +013c 029d 0145 JNZ 0x0145 +013e 0080 0398 LRI $R00, #0x0398 +0140 0e08 LRIS $AC0.M, #0x08 +0141 00c1 03a1 LR $R01, @0x03a1 +0143 02bf 0b2e CALL 0x0b2e +0145 0f50 LRIS $AC1.M, #0x50 +0146 00c0 03a1 LR $R00, @0x03a1 +0148 00da 0394 LR $AX0.H, @0x0394 +//.. +014a 8600 TSTAXH $AX0.H +014b 0295 0152 JEQ 0x0152 +014d 1c7a MRR $R03, $AX0.H +014e 00d8 0395 LR $AX0.L, @0x0395 +0150 02bf 00eb CALL 0x00eb // one of the multiply loops +0152 0f50 LRIS $AC1.M, #0x50 +0153 00c0 03a1 LR $R00, @0x03a1 +0155 00da 0396 LR $AX0.H, @0x0396 +//.. +0157 8600 TSTAXH $AX0.H +0158 0295 015f JEQ 0x015f +015a 1c7a MRR $R03, $AX0.H +015b 00d8 0397 LR $AX0.L, @0x0397 +015d 02bf 00eb CALL 0x00eb // one of the multiply loops +015f 00de 0390 LR $AC0.M, @0x0390 +0161 02a0 0002 ANDCF $AC0.M, #0x0002 +0163 02dd RETNZ +//.. +0164 0080 0398 LRI $R00, #0x0398 +0166 0e08 LRIS $AC0.M, #0x08 +0167 00c1 03a1 LR $R01, @0x03a1 +0169 02bf 0b2e CALL 0x0b2e +016b 02df RET + +// Yet another mixer? this one does both 0x50 and 0x28 loops. +016c 8900 CLR $AC1.M +016d 009f 0dc0 LRI $AC1.M, #0x0dc0 +016f 00ff 03a1 SR @0x03a1, $AC1.M +0171 009f 03a8 LRI $AC1.M, #0x03a8 +0173 00ff 03a2 SR @0x03a2, $AC1.M +0175 009f 03a4 LRI $AC1.M, #0x03a4 +0177 00ff 03a0 SR @0x03a0, $AC1.M +0179 1104 019f BLOOPI #0x04, 0x019f // scary bloopi - end of instruction! +017b 00c0 03a2 LR $R00, @0x03a2 +017d 0083 0390 LRI $R03, #0x0390 +017f 0f0e LRIS $AC1.M, #0x0e +0180 02bf 00da CALL 0x00da // CopyMemory(LEN=$AC1.M, *R00=SRC, *R03=DEST) +0182 00da 0390 LR $AX0.H, @0x0390 +0184 8600 TSTAXH $AX0.H +0185 0295 0191 JEQ 0x0191 +0187 00df 03a1 LR $AC1.M, @0x03a1 +0189 1c7f MRR $R03, $AC1.M +018a 0550 ADDIS $ACC1, #0x50 +018b 1c1f MRR $R00, $AC1.M +018c 0f06 LRIS $AC1.M, #0x06 +018d 02bf 00da CALL 0x00da // CopyMemory(LEN=$AC1.M, *R00=SRC, *R03=DEST) +018f 02bf 0127 CALL 0x0127 +//.. +0191 00de 03a2 LR $AC0.M, @0x03a2 +0193 0410 ADDIS $ACC0, #0x10 +0194 00fe 03a2 SR @0x03a2, $AC0.M +0196 00de 03a1 LR $AC0.M, @0x03a1 +0198 0460 ADDIS $ACC0, #0x60 +0199 00fe 03a1 SR @0x03a1, $AC0.M +019b 00de 03a0 LR $AC0.M, @0x03a0 +019d 7400 INCM $AC0.M +019e 00fe 03a0 SR @0x03a0, $AC0.Ma +// end of BLOOPI 0179 +01a0 0f50 LRIS $AC1.M, #0x50 +01a1 0080 0c00 LRI $R00, #0x0c00 +01a3 0083 0e80 LRI $R03, #0x0e80 +01a5 0098 7fff LRI $AX0.L, #0x7fff +01a7 02bf 00eb CALL 0x00eb // one of the multiply loops +01a9 0f50 LRIS $AC1.M, #0x50 +01aa 0080 0c00 LRI $R00, #0x0c00 +01ac 0083 0ee0 LRI $R03, #0x0ee0 +01ae 0098 b820 LRI $AX0.L, #0xb820 +01b0 02bf 00eb CALL 0x00eb // one of the multiply loops +01b2 0f28 LRIS $AC1.M, #0x28 // half size! +01b3 0080 0c78 LRI $R00, #0x0c78 +01b5 0083 0e80 LRI $R03, #0x0e80 +01b7 0098 b820 LRI $AX0.L, #0xb820 +01b9 02bf 00eb CALL 0x00eb // one of the multiply loops +01bb 0f28 LRIS $AC1.M, #0x28 // half size! +01bc 0080 0c78 LRI $R00, #0x0c78 +01be 0083 0ee0 LRI $R03, #0x0ee0 +01c0 0098 7fff LRI $AX0.L, #0x7fff +01c2 02bf 00eb CALL 0x00eb // one of the multiply loops +01c4 8100 CLR $AC0.M +01c5 8900 CLR $AC1.M +01c6 0e50 LRIS $AC0.M, #0x50 // bufsize. looks like buf clearing +01c7 0080 0c00 LRI $R00, #0x0c00 +01c9 005e LOOP $AC0.M +01ca 1b1f SRRI @$R00, $AC1.M +01cb 0080 0c50 LRI $R00, #0x0c50 +01cd 005e LOOP $AC0.M +01ce 1b1f SRRI @$R00, $AC1.M +01cf 02df RET + + + +01d0 00c0 03a0 LR $R00, @0x03a0 +01d2 181a LRR $AX0.H, @$R00 +01d3 8100 CLR $AC0.M +01d4 181e LRR $AC0.M, @$R00 +01d5 00db 0391 LR $AX1.H, @0x0391 +01d7 7400 INCM $AC0.M +01d8 d100 CMPAXH $AC1.M, $AX0.H +01d9 0270 IF_0 +01da 8100 CLR $AC0.M +01db 1b1e SRRI @$R00, $AC0.M +01dc 00df 03a1 LR $AC1.M, @0x03a1 +01de 009b 00a0 LRI $AX1.H, #0x00a0 +01e0 0081 0393 LRI $R01, #0x0393 +01e2 18bc LRRD $AC0.L, @$R01 +01e3 b871 MULX.L $AX0.H, $AX1.H : $AC0.M, @$R01 +01e4 bc00 MULXAC $AX0.H, $AX1.H, $AC0.M +01e5 0080 0050 LRI $R00, #0x0050 +01e7 02bf 0532 CALL 0x0532 // DMEMtoRAM(DMEM=$AC1.M, AC0=MEMADDR, R00=Len) +01e9 02df RET + + +// Another zany mixer... this time on half-length buffers (0x28 instead of 0x50)? +01ea 8900 CLR $AC1.M +01eb 0f28 LRIS $AC1.M, #0x28 +01ec 0080 0c50 LRI $R00, #0x0c50 +01ee 0083 0ea8 LRI $R03, #0x0ea8 +01f0 0098 b820 LRI $AX0.L, #0xb820 +01f2 02bf 00eb CALL 0x00eb // one of the multiply loops +01f4 8900 CLR $AC1.M +01f5 0f28 LRIS $AC1.M, #0x28 +01f6 0080 0c50 LRI $R00, #0x0c50 +01f8 0083 0f08 LRI $R03, #0x0f08 +01fa 0098 7fff LRI $AX0.L, #0x7fff +01fc 02bf 00eb CALL 0x00eb // one of the multiply loops +01fe 009f 0dc0 LRI $AC1.M, #0x0dc0 +0200 00ff 03a1 SR @0x03a1, $AC1.M +0202 009f 03a8 LRI $AC1.M, #0x03a8 +0204 00ff 03a2 SR @0x03a2, $AC1.M +0206 009f 03a4 LRI $AC1.M, #0x03a4 +0208 00ff 03a0 SR @0x03a0, $AC1.M +020a 1104 0228 BLOOPI #0x04, 0x0228 +020c 00c0 03a2 LR $R00, @0x03a2 +020e 0083 0390 LRI $R03, #0x0390 +0210 0f0e LRIS $AC1.M, #0x0e +0211 02bf 00da CALL 0x00da // CopyMemory(LEN=$AC1.M, *R00=SRC, *R03=DEST) +0213 00da 0390 LR $AX0.H, @0x0390 +0215 8600 TSTAXH $AX0.H +0216 0295 021a JEQ 0x021a +0218 02bf 01d0 CALL 0x01d0 +021a 00de 03a2 LR $AC0.M, @0x03a2 +021c 0410 ADDIS $ACC0, #0x10 +021d 00fe 03a2 SR @0x03a2, $AC0.M +021f 00de 03a1 LR $AC0.M, @0x03a1 +0221 0460 ADDIS $ACC0, #0x60 +0222 00fe 03a1 SR @0x03a1, $AC0.M +0224 00de 03a0 LR $AC0.M, @0x03a0 +0226 7400 INCM $AC0.M +0227 00fe 03a0 SR @0x03a0, $AC0.M +0229 02df RET + + + +022a 0081 0386 LRI $R01, #0x0386 +022c 009f 03a8 LRI $AC1.M, #0x03a8 +022e 0080 0040 LRI $R00, #0x0040 +0230 02bf 0523 CALL 0x0523 // RAMtoDMEM(DMEM=$AC1.M, *R01=MEMADDR, R00=Len) +0232 02df RET + + +// Load 32-bit value, add AX0 to it, store it back. Trash ACC0. +0233 191e LRRI $AC0.M, @$R00 +0234 189c LRRD $AC0.L, @$R00 +0235 4800 ADDAX $AC0.M, $AX0.L +0236 1b1e SRRI @$R00, $AC0.M +0237 1b1c SRRI @$R00, $AC0.L +0238 02df RET + + +// This looks like some sort of crazy wait loop, waiting for one value to equal the other. +// Must be interrupt-driven? +0239 8100 CLR $AC0.M +023a 8900 CLR $AC1.M +023b 00df 0354 LR $AC1.M, @0x0354 +023d 00de 034e LR $AC0.M, @0x034e +023f 8200 CMP +0240 0293 0239 JX3 0x0239 +0242 02df RET + +// Opcode_02() - SyncFrame +0243 0080 0388 LRI $R00, #0x0388 +0245 0081 0067 LRI $R01, #0x0067 +0247 0e02 LRIS $AC0.M, #0x02 +0248 173f CALLR $R01 // Strange call - seems to always go to 0067 .. unless we can get here in another way than from above. +0249 00de 0344 LR $AC0.M, @0x0344 +024b 00fe 0341 SR @0x0341, $AC0.M +024d 00de 0345 LR $AC0.M, @0x0345 +024f 00fe 038e SR @0x038e, $AC0.M +0251 8100 CLR $AC0.M +0252 00fe 0355 SR @0x0355, $AC0.M +0254 02bf 022a CALL 0x022a +0256 02bf 05a4 CALL 0x05a4 // ClearAccelerator() +0258 00de 0341 LR $AC0.M, @0x0341 +025a 007e 0418 BLOOP $AC0.M, 0x0418 +025c 02bf 0102 CALL 0x0102 // Clear some memory areas... +025e 02bf 016c CALL 0x016c // mix in background music? or something? dunno +0260 02bf 095f CALL 0x095f // recalc some table? +0262 00de 0355 LR $AC0.M, @0x0355 // Increase counter at 0x0355 +0264 7400 INCM $AC0.M +0265 00fe 0355 SR @0x0355, $AC0.M +0267 8100 CLR $AC0.M +0268 00fe 0354 SR @0x0354, $AC0.M // Zero counter at 0x0354 +026a 00de 0342 LR $AC0.M, @0x0342 // Read 0x0342, that number of times, process the loop. +026c 007e 03c0 BLOOP $AC0.M, 0x03c0 // Strange loop - goes outside this function... +026e 02bf 0239 CALL 0x0239 // This one waits for interrupts. +0270 8100 CLR $AC0.M +0271 8900 CLR $AC1.M +0272 00de 0354 LR $AC0.M, @0x0354 // 0x354 is obviously interesting. +0274 147c LSR $ACC0, #0x3c +0275 0200 04fc ADDI $ACC0, #0x04fc +0277 1c1e MRR $R00, $AC0.M +0278 181f LRR $AC1.M, @$R00 // Table lookup from DRAM @ 0x04fc. Something must have initialized it. +0279 00de 0354 LR $AC0.M, @0x0354 +027b 0240 000f ANDI $ACC0, #0x000f +027d 3d80 ANDC.LS $AC1.M : $AX0.L, $AC0.M +027e 03c0 8000 ANDF $AC1.M, #0x8000 +0280 029c 03bc JZR 0x03bc +0282 00d8 0354 LR $AX0.L, @0x0354 +0284 009a 0180 LRI $AX0.H, #0x0180 +0286 8100 CLR $AC0.M +0287 00de 0380 LR $AC0.M, @0x0380 +0289 00dc 0381 LR $AC0.L, @0x0381 +028b 9000 MUL $AX0.L, $AX0.H +028c 9400 MULAC $AX0.L, $AX0.H, $AC0.M +028d 00fe 034c SR @0x034c, $AC0.M +028f 00fc 034d SR @0x034d, $AC0.L +0291 02bf 00c1 CALL 0x00c1 +0293 00da 0400 LR $AX0.H, @0x0400 +0295 8600 TSTAXH $AX0.H +0296 0295 03bc JEQ 0x03bc +0298 00da 0401 LR $AX0.H, @0x0401 +029a 8600 TSTAXH $AX0.H +029b 0294 03bc JNE 0x03bc +029d 00da 0433 LR $AX0.H, @0x0433 +029f 00fa 03f8 SR @0x03f8, $AX0.H +02a1 00da 0406 LR $AX0.H, @0x0406 +02a3 8600 TSTAXH $AX0.H +02a4 0294 0dff JNE 0x0dff +02a6 8100 CLR $AC0.M +02a7 00de 0480 LR $AC0.M, @0x0480 +02a9 0609 CMPIS $ACC0, #0x09 +02aa 0295 02bd JEQ 0x02bd +02ac 0605 CMPIS $ACC0, #0x05 +02ad 0295 02bd JEQ 0x02bd +02af 0608 CMPIS $ACC0, #0x08 +02b0 0295 098f JEQ 0x098f +02b2 0610 CMPIS $ACC0, #0x10 +02b3 0295 0a14 JEQ 0x0a14 +02b5 0620 CMPIS $ACC0, #0x20 +02b6 0295 0a9a JEQ 0x0a9a +02b8 0621 CMPIS $ACC0, #0x21 +02b9 0295 0aa2 JEQ 0x0aa2 +02bb 029f 087c JMP 0x087c + +// Choose from one of several 0x50 size buffers and do something? +02bd 00d8 0402 LR $AX0.L, @0x0402 +02bf 8100 CLR $AC0.M +02c0 8900 CLR $AC1.M +02c1 00dc 0430 LR $AC0.L, @0x0430 +02c3 8d00 SET15 +02c4 0950 LRIS $AX1.L, #0x50 +02c5 a000 MULX $AX0.L, $AX1.L +02c6 a400 MULXAC $AX0.L, $AX1.L, $AC0.M +02c7 1404 LSL $ACC0, #0x04 +02c8 8c00 CLR15 +02c9 1ffe MRR $AC1.M, $AC0.M +02ca 0083 0580 LRI $R03, #0x0580 +02cc 02bf 073d CALL 0x073d +02ce 029f 02d0 JMP 0x02d0 + + +02d0 0080 0580 LRI $R00, #0x0580 +02d2 0081 0520 LRI $R01, #0x0520 +02d4 0099 0000 LRI $AX1.L, #0x0000 +02d6 02bf 0d7f CALL 0x0d7f +02d8 00da 04a8 LR $AX0.H, @0x04a8 +02da 8600 TSTAXH $AX0.H +02db 0295 02e1 JEQ 0x02e1 +02dd 0080 0520 LRI $R00, #0x0520 +02df 02bf 0c84 CALL 0x0c84 +02e1 009e 0520 LRI $AC0.M, #0x0520 +02e3 00fe 038f SR @0x038f, $AC0.M +02e5 8900 CLR $AC1.M +02e6 00df 0484 LR $AC1.M, @0x0484 +02e8 0340 001f ANDI $ACC1, #0x001f +02ea b900 TST $AC1.M +02eb 0295 0311 JEQ 0x0311 +02ed 00de 038f LR $AC0.M, @0x038f +02ef 5c00 SUB $AC0.M, $AC1.M +02f0 00fe 038f SR @0x038f, $AC0.M +02f2 1c7e MRR $R03, $AC0.M +02f3 0080 0440 LRI $R00, #0x0440 +02f5 05fe ADDIS $ACC1, #0xfe +02f6 02bf 00da CALL 0x00da // CopyMemory(LEN=$AC1.M, *R00=SRC, *R03=DEST) +02f8 0080 0490 LRI $R00, #0x0490 +02fa 00c1 038f LR $R01, @0x038f +02fc 8900 CLR $AC1.M +02fd 00df 0484 LR $AC1.M, @0x0484 +02ff 0340 001f ANDI $ACC1, #0x001f +0301 02bf 0b4d CALL 0x0b4d +0303 00de 038f LR $AC0.M, @0x038f +0305 0450 ADDIS $ACC0, #0x50 +0306 1c1e MRR $R00, $AC0.M +0307 0083 0440 LRI $R03, #0x0440 +0309 8900 CLR $AC1.M +030a 00df 0484 LR $AC1.M, @0x0484 +030c 0340 001f ANDI $ACC1, #0x001f +030e 05fe ADDIS $ACC1, #0xfe +030f 02bf 00da CALL 0x00da // CopyMemory(LEN=$AC1.M, *R00=SRC, *R03=DEST) +0311 00de 0484 LR $AC0.M, @0x0484 +0313 0240 0020 ANDI $ACC0, #0x0020 +0315 0295 0333 JEQ 0x0333 +0317 0080 04a4 LRI $R00, #0x04a4 +0319 00c1 038f LR $R01, @0x038f +031b 0082 0454 LRI $R02, #0x0454 +031d 0083 04a7 LRI $R03, #0x04a7 +031f 18fa LRRD $AX0.H, @$R03 +0320 8600 TSTAXH $AX0.H +0321 0294 0331 JNE 0x0331 +0323 18fa LRRD $AX0.H, @$R03 +0324 8600 TSTAXH $AX0.H +0325 0294 0331 JNE 0x0331 +0327 18fa LRRD $AX0.H, @$R03 +0328 8600 TSTAXH $AX0.H +0329 0294 0331 JNE 0x0331 +032b 8100 CLR $AC0.M +032c 18fe LRRD $AC0.M, @$R03 +032d 0280 7fff CMPI $AC0.M, #0x7fff +032f 0295 0333 JEQ 0x0333 +0331 02bf 0b68 CALL 0x0b68 +0333 8100 CLR $AC0.M +0334 00de 042c LR $AC0.M, @0x042c +0336 b100 TST $AC0.M +0337 0295 033d JEQ 0x033d +0339 02bf 0cd3 CALL 0x0cd3 +033b 029f 03b2 JMP 0x03b2 +033d 8100 CLR $AC0.M +033e 1c9e MRR $R04, $AC0.M +033f 1cde MRR $R06, $AC0.M +0340 7400 INCM $AC0.M +0341 1cfe MRR $R07, $AC0.M +0342 8100 CLR $AC0.M +0343 00de 0407 LR $AC0.M, @0x0407 +0345 b100 TST $AC0.M +0346 0295 0355 JEQ 0x0355 +0348 00c3 038f LR $R03, @0x038f +034a 0007 DAR $R03 +034b 0080 0477 LRI $R00, #0x0477 +034d 0084 ffff LRI $R04, #0xffff +034f 0087 ffff LRI $R07, #0xffff +0351 199a LRRN $AX0.H, @$R00 +0352 6554 MOVR.LN $AC1.M, $AX0.H : $AX0.H, @$R00 +0353 005e LOOP $AC0.M +0354 65ad MOVR.LSNM $AC1.M, $AX0.H : $AX0.H, $AC1.M +0355 00da 0485 LR $AX0.H, @0x0485 +0357 8600 TSTAXH $AX0.H +0358 0295 036b JEQ 0x036b +035a 8900 CLR $AC1.M +035b 0086 0005 LRI $R06, #0x0005 +035d 0082 040a LRI $R02, #0x040a +035f 1106 0363 BLOOPI #0x06, 0x0363 +0361 18de LRRD $AC0.M, @$R02 +0362 147f LSR $ACC0, #0x3f +0363 4d36 ADD.SN $AC1.M, $AC0.M : @$R02, $AC0.M +0364 b900 TST $AC1.M +0365 0294 036b JNE 0x036b +0367 009a 0001 LRI $AX0.H, #0x0001 +0369 00fa 0401 SR @0x0401, $AX0.H +036b 8f00 S16 +036c 0086 0002 LRI $R06, #0x0002 +036e 0082 0408 LRI $R02, #0x0408 +0370 1106 039b BLOOPI #0x06, 0x039b +0372 8100 CLR $AC0.M +0373 195e LRRI $AC0.M, @$R02 +0374 1200 SBCLR #0x00 +0375 b100 TST $AC0.M +0376 0275 IF_Q +0377 1300 SBSET #0x00 +0378 1c7e MRR $R03, $AC0.M +0379 195e LRRI $AC0.M, @$R02 +037a 195f LRRI $AC1.M, @$R02 +037b 5c00 SUB $AC0.M, $AC1.M +037c 14fb ASR $ACC0, #0x7b +037d 1f5e MRR $AX0.H, $AC0.M +037e 1f1c MRR $AX0.L, $AC0.L +037f 185e LRR $AC0.M, @$R02 +0380 0240 00ff ANDI $ACC0, #0x00ff +0382 1f7e MRR $AX1.H, $AC0.M +0383 185e LRR $AC0.M, @$R02 +0384 1478 LSR $ACC0, #0x38 +0385 009c 0000 LRI $AC0.L, #0x0000 +0387 d100 CMPAXH $AC1.M, $AX0.H +0388 0295 0390 JEQ 0x0390 +038a 185e LRR $AC0.M, @$R02 +038b 0272 IF_2 +038c 7400 INCM $AC0.M +038d 0271 IF_1 +038e 7800 DECM $AC0.M +038f 1a5e SRR @$R02, $AC0.M +0390 0006 DAR $R02 +0391 00de 038f LR $AC0.M, @0x038f +0393 5600 SUBR $AC0.M, $AX1.H +0394 029d 0399 JNZ 0x0399 +0396 1c1e MRR $R00, $AC0.M +0397 02bf 0ca9 CALL 0x0ca9 +0399 0000 NOP +039a 1b5f SRRI @$R02, $AC1.M +039b 000a IAR $R02 +039c 8e00 S40 +039d 8100 CLR $AC0.M +039e 00de 0407 LR $AC0.M, @0x0407 +03a0 b100 TST $AC0.M +03a1 0295 03b2 JEQ 0x03b2 +03a3 00c3 038f LR $R03, @0x038f +03a5 0087 004f LRI $R07, #0x004f // does this have something to do with the common 0x50 buffer size? +03a7 001f CW 0x001f ; *** UNKNOWN OPCODE *** +03a8 0080 0477 LRI $R00, #0x0477 +03aa 0084 ffff LRI $R04, #0xffff +03ac 0087 ffff LRI $R07, #0xffff +03ae 19fa LRRN $AX0.H, @$R03 +03af 6557 MOVR.LN $AC1.M, $AX0.H : $AX0.H, @$R03 +03b0 005e LOOP $AC0.M +03b1 65af MOVR.SLNM $AC1.M, $AX0.H : $AC1.M, $AX0.H +03b2 00da 0406 LR $AX0.H, @0x0406 +03b4 8600 TSTAXH $AX0.H +03b5 0294 03ba JNE 0x03ba +03b7 8100 CLR $AC0.M +03b8 00fe 0404 SR @0x0404, $AC0.M +03ba 02bf 00ca CALL 0x00ca +03bc 00de 0354 LR $AC0.M, @0x0354 +03be 7400 INCM $AC0.M +03bf 00fe 0354 SR @0x0354, $AC0.M +03c1 0e00 LRIS $AC0.M, #0x00 +03c2 00fe 034e SR @0x034e, $AC0.M +03c4 0e04 LRIS $AC0.M, #0x04 +03c5 02bf 066a CALL 0x066a // SendMessageViaDSPMailBox_DCD1(AC0.M) +03c7 00de 0355 LR $AC0.M, @0x0355 +03c9 0260 ff00 ORI $ACC0, #0xff00 +03cb 02bf 0674 CALL 0x0674 // SendMessageViaDSPMailBox_F355(AC0.M) +03cd 02bf 0c0a CALL 0x0c0a +03cf 02bf 0c1c CALL 0x0c1c +03d1 02bf 0c71 CALL 0x0c71 +03d3 00de 0341 LR $AC0.M, @0x0341 +03d5 7800 DECM $AC0.M +03d6 00fe 0341 SR @0x0341, $AC0.M +03d8 0080 09a0 LRI $R00, #0x09a0 +03da 0083 0d00 LRI $R03, #0x0d00 +03dc 0f50 LRIS $AC1.M, #0x50 +03dd 0098 5a82 LRI $AX0.L, #0x5a82 +03df 02bf 00eb CALL 0x00eb // one of the multiply loops +03e1 0080 09a0 LRI $R00, #0x09a0 +03e3 0083 0d60 LRI $R03, #0x0d60 +03e5 0f50 LRIS $AC1.M, #0x50 +03e6 02bf 00eb CALL 0x00eb // one of the multiply loops +03e8 0083 0d00 LRI $R03, #0x0d00 +03ea 02bf 0cc1 CALL 0x0cc1 +03ec 0081 0388 LRI $R01, #0x0388 +03ee 009f 0d00 LRI $AC1.M, #0x0d00 +03f0 0080 0050 LRI $R00, #0x0050 +03f2 02bf 0530 CALL 0x0530 // DMEMtoRAM(DMEM=$AC1.M, *R01=MEMADDR, R00=Len) +03f4 0080 0fa0 LRI $R00, #0x0fa0 +03f6 0083 0d60 LRI $R03, #0x0d60 +03f8 0f50 LRIS $AC1.M, #0x50 +03f9 0098 8000 LRI $AX0.L, #0x8000 +03fb 02bf 00eb CALL 0x00eb // one of the multiply loops +03fd 0083 0d60 LRI $R03, #0x0d60 +03ff 02bf 0cc1 CALL 0x0cc1 +0401 0081 038a LRI $R01, #0x038a +0403 009f 0d60 LRI $AC1.M, #0x0d60 +0405 0080 0050 LRI $R00, #0x0050 +0407 02bf 0530 CALL 0x0530 // DMEMtoRAM(DMEM=$AC1.M, *R01=MEMADDR, R00=Len) +0409 009a 0000 LRI $AX0.H, #0x0000 +040b 0098 00a0 LRI $AX0.L, #0x00a0 +040d 0080 0388 LRI $R00, #0x0388 +040f 02bf 0233 CALL 0x0233 +0411 0080 038a LRI $R00, #0x038a +0413 02bf 0233 CALL 0x0233 +0415 02bf 01ea CALL 0x01ea +0417 0000 NOP +0418 0000 NOP +0419 0080 002d LRI $R00, #0x002d +041b 029f 0603 JMP 0x0603 + + + +// Opcode_07() +041d 0080 0346 LRI $R00, #0x0346 +041f 02bf 0067 CALL 0x0067 // ReadWholeMessage($R00) +0421 02bf 0067 CALL 0x0067 // ReadWholeMessage($R00) +0423 0081 0346 LRI $R01, #0x0346 +0425 193e LRRI $AC0.M, @$R01 +0426 193c LRRI $AC0.L, @$R01 +0427 009f 0400 LRI $AC1.M, #0x0400 +0429 00c0 0345 LR $R00, @0x0345 +042b 02bf 0525 CALL 0x0525 // RAMtoDMEM(DMEM=$AC1.M, AC0=MEMADDR, R00=Len) +042d 0081 0348 LRI $R01, #0x0348 +042f 193e LRRI $AC0.M, @$R01 +0430 193c LRRI $AC0.L, @$R01 +0431 009f 0800 LRI $AC1.M, #0x0800 +0433 00c0 0345 LR $R00, @0x0345 +0435 02bf 0525 CALL 0x0525 // RAMtoDMEM(DMEM=$AC1.M, AC0=MEMADDR, R00=Len) +0437 0081 0346 LRI $R01, #0x0346 +0439 193e LRRI $AC0.M, @$R01 +043a 193c LRRI $AC0.L, @$R01 +043b 009f 0800 LRI $AC1.M, #0x0800 +043d 00c0 0345 LR $R00, @0x0345 +043f 02bf 0532 CALL 0x0532 // DMEMtoRAM(DMEM=$AC1.M, AC0=MEMADDR, R00=Len) +0441 0081 0348 LRI $R01, #0x0348 +0443 193e LRRI $AC0.M, @$R01 +0444 193c LRRI $AC0.L, @$R01 +0445 009f 0400 LRI $AC1.M, #0x0400 +0447 00c0 0345 LR $R00, @0x0345 +0449 02bf 0532 CALL 0x0532 // DMEMtoRAM(DMEM=$AC1.M, AC0=MEMADDR, R00=Len) +044b 029f 0043 JMP 0x0043 + + +// Opcode_09() +044d 0080 0346 LRI $R00, #0x0346 +044f 02bf 0067 CALL 0x0067 // ReadWholeMessage($R00) +0451 02bf 0067 CALL 0x0067 // ReadWholeMessage($R00) +0453 0081 0346 LRI $R01, #0x0346 +0455 193e LRRI $AC0.M, @$R01 +0456 193c LRRI $AC0.L, @$R01 +0457 009f 0400 LRI $AC1.M, #0x0400 +0459 00c0 0345 LR $R00, @0x0345 +045b 02bf 0525 CALL 0x0525 // RAMtoDMEM(DMEM=$AC1.M, AC0=MEMADDR, R00=Len) +045d 0081 0348 LRI $R01, #0x0348 +045f 193e LRRI $AC0.M, @$R01 +0460 193c LRRI $AC0.L, @$R01 +0461 009f 0400 LRI $AC1.M, #0x0400 +0463 00c0 0345 LR $R00, @0x0345 +0465 02bf 0532 CALL 0x0532 // DMEMtoRAM(DMEM=$AC1.M, AC0=MEMADDR, R00=Len) +0467 029f 0043 JMP 0x0043 + +// Opcode_06() +0469 0080 0346 LRI $R00, #0x0346 +046b 02bf 0067 CALL 0x0067 // ReadWholeMessage($R00) +046d 02bf 0067 CALL 0x0067 // ReadWholeMessage($R00) +046f 0081 0346 LRI $R01, #0x0346 +0471 193e LRRI $AC0.M, @$R01 +0472 193c LRRI $AC0.L, @$R01 +0473 009f 0400 LRI $AC1.M, #0x0400 +0475 00c0 0345 LR $R00, @0x0345 +0477 02bf 0555 CALL 0x0555 +0479 0081 0348 LRI $R01, #0x0348 +047b 193e LRRI $AC0.M, @$R01 +047c 193c LRRI $AC0.L, @$R01 +047d 009f 0400 LRI $AC1.M, #0x0400 +047f 00c0 0345 LR $R00, @0x0345 +0481 02bf 0532 CALL 0x0532 // DMEMtoRAM(DMEM=$AC1.M, AC0=MEMADDR, R00=Len) +0483 029f 0043 JMP 0x0043 + + +// Opcode_08() - Mixer +0485 0080 0346 LRI $R00, #0x0346 +0487 02bf 0067 CALL 0x0067 // ReadWholeMessage($R00) +0489 02bf 0067 CALL 0x0067 // ReadWholeMessage($R00) +048b 0081 0346 LRI $R01, #0x0346 +048d 193e LRRI $AC0.M, @$R01 +048e 193c LRRI $AC0.L, @$R01 +048f 009f 0400 LRI $AC1.M, #0x0400 +0491 00c0 0344 LR $R00, @0x0344 +0493 02bf 0525 CALL 0x0525 // RAMtoDMEM(DMEM=$AC1.M, AC0=MEMADDR, R00=Len) +0495 0081 0348 LRI $R01, #0x0348 +0497 193e LRRI $AC0.M, @$R01 +0498 193c LRRI $AC0.L, @$R01 +0499 009f 0800 LRI $AC1.M, #0x0800 +049b 00c0 0344 LR $R00, @0x0344 +049d 02bf 0525 CALL 0x0525 // RAMtoDMEM(DMEM=$AC1.M, AC0=MEMADDR, R00=Len) +049f 0080 0400 LRI $R00, #0x0400 +04a1 0083 0800 LRI $R03, #0x0800 +04a3 0084 0000 LRI $R04, #0x0000 +04a5 00da 0345 LR $AX0.H, @0x0345 +04a7 00df 0344 LR $AC1.M, @0x0344 +04a9 8f00 S16 +04aa 197b LRRI $AX1.H, @$R03 +04ab b800 MULX $AX0.H, $AX1.H +04ac 197b LRRI $AX1.H, @$R03 +04ad 007f 04b2 BLOOP $AC1.M, 0x04b2 +04af 199e LRRN $AC0.M, @$R00 +04b0 bc00 MULXAC $AX0.H, $AX1.H, $AC0.M +04b1 80b2 NX.SL : $AC0.M, $AX1.H +04b2 0000 NOP +04b3 8e00 S40 +04b4 0081 0346 LRI $R01, #0x0346 +04b6 193e LRRI $AC0.M, @$R01 +04b7 193c LRRI $AC0.L, @$R01 +04b8 009f 0400 LRI $AC1.M, #0x0400 +04ba 00c0 0344 LR $R00, @0x0344 +04bc 02bf 0532 CALL 0x0532 // DMEMtoRAM(DMEM=$AC1.M, AC0=MEMADDR, R00=Len) +04be 029f 0043 JMP 0x0043 + + +// dunno... is called by InitCode() +04c0 0092 00ff LRI $CR, #0x00ff +04c2 8100 CLR $AC0.M +04c3 0080 0b00 LRI $R00, #0x0b00 +04c5 10ff LOOPI #0xff +04c6 1b1e SRRI @$R00, $AC0.M +04c7 1b1e SRRI @$R00, $AC0.M +04c8 8100 CLR $AC0.M +04c9 009f 0b00 LRI $AC1.M, #0x0b00 +04cb 0080 0100 LRI $R00, #0x0100 +04cd 02bf 0573 CALL 0x0573 +04cf 02df RET + +// +04d0 02bf 04e1 CALL 0x04e1 +04d2 00df 04fb LR $AC1.M, @0x04fb +04d4 009e 0b00 LRI $AC0.M, #0x0b00 +04d6 4c00 ADD $AC0.M, $AC1.M +04d7 1c1e MRR $R00, $AC0.M +04d8 181e LRR $AC0.M, @$R00 +04d9 7400 INCM $AC0.M +04da 1a1e SRR @$R00, $AC0.M +04db 02bf 04ea CALL 0x04ea +04dd 8100 CLR $AC0.M +04de 00fe 04fb SR @0x04fb, $AC0.M +04e0 02df RET + + +// This is called by the thing above. +04e1 0092 00ff LRI $CR, #0x00ff +04e3 8100 CLR $AC0.M +04e4 009f 0b00 LRI $AC1.M, #0x0b00 +04e6 0080 0040 LRI $R00, #0x0040 +04e8 029f 0555 JMP 0x0555 ///oookay.. + +// +04ea 8100 CLR $AC0.M +04eb 009f 0b00 LRI $AC1.M, #0x0b00 +04ed 0080 0050 LRI $R00, #0x0050 +04ef 029f 0573 JMP 0x0573 + +// +04f1 02bf 04e1 CALL 0x04e1 +04f3 8900 CLR $AC1.M +04f4 0080 04fc LRI $R00, #0x04fc +04f6 8100 CLR $AC0.M +04f7 1104 0505 BLOOPI #0x04, 0x0505 +04f9 0000 NOP +04fa 191e LRRI $AC0.M, @$R00 +04fb 0000 NOP +04fc 1110 0503 BLOOPI #0x10, 0x0503 +04fe 02c0 0001 ANDF $AC0.M, #0x0001 +0500 027d IF_Z +0501 7500 INCM $AC1.M +0502 147f LSR $ACC0, #0x3f // Another bizarre super shift. +0503 0000 NOP // Do these shifts have latency? +0504 0000 NOP +0505 0000 NOP + + +0506 00de 04fc LR $AC0.M, @0x04fc +0508 00fe 0b48 SR @0x0b48, $AC0.M +050a 00de 04fd LR $AC0.M, @0x04fd +050c 00fe 0b49 SR @0x0b49, $AC0.M +050e 00de 04fe LR $AC0.M, @0x04fe +0510 00fe 0b4a SR @0x0b4a, $AC0.M +0512 00de 04ff LR $AC0.M, @0x04ff +0514 00fe 0b4b SR @0x0b4b, $AC0.M +0516 009e 0b00 LRI $AC0.M, #0x0b00 +0518 4c00 ADD $AC0.M, $AC1.M +0519 1c1e MRR $R00, $AC0.M +051a 181e LRR $AC0.M, @$R00 +051b 7400 INCM $AC0.M +051c 1a1e SRR @$R00, $AC0.M +051d 02bf 04ea CALL 0x04ea +051f 02df RET + + +0520 02bf 04ea CALL 0x04ea +0522 02df RET + +// RAMtoDMEM(DMEM=$AC1.M, *R01=MEMADDR, R00=Len) +0523 193e LRRI $AC0.M, @$R01 +0524 193c LRRI $AC0.L, @$R01 +// RAMtoDMEM(DMEM=$AC1.M, AC0=MEMADDR, R00=Len) +0525 2fcd SRS @DSPA, $AC1.M +0526 0f00 LRIS $AC1.M, #0x00 +0527 2fc9 SRS @DSCR, $AC1.M +0528 2ece SRS @DSMAH, $AC0.M +0529 2ccf SRS @DSMAL, $AC0.L +052a 1fe0 MRR $AC1.M, $R00 +052b 1501 LSL $ACC1, #0x01 +052c 2fcb SRS @DSBL, $AC1.M +052d 02bf 0536 CALL 0x0536 // WaitForDMATransfer() +052f 02df RET + + +// DMEMtoRAM(DMEM=$AC1.M, *R01=MEMADDR, R00=Len) +0530 193e LRRI $AC0.M, @$R01 +0531 193c LRRI $AC0.L, @$R01 +// DMEMtoRAM(DMEM=$AC1.M, AC0=MEMADDR, R00=Len) +0532 2fcd SRS @DSPA, $AC1.M +0533 0f01 LRIS $AC1.M, #0x01 +0534 029f 0527 JMP 0x0527 + +// WaitForDMATransfer() +0536 26c9 LRS $AC0.M, @DSCR +0537 02a0 0004 ANDCF $AC0.M, #0x0004 +0539 029c 0536 JZR 0x0536 +053b 02df RET + +// Setup DMA conroller and do a transfer. Should figure out exactly how. +053c 193e LRRI $AC0.M, @$R01 +053d 193c LRRI $AC0.L, @$R01 +053e 00ff ffcd SR @DSPA, $AC1.M +0540 0f00 LRIS $AC1.M, #0x00 +0541 00ff ffc9 SR @DSCR, $AC1.M +0543 00fe ffce SR @DSMAH, $AC0.M +0545 00fc ffcf SR @DSMAL, $AC0.L +0547 1fe0 MRR $AC1.M, $R00 +0548 1501 LSL $ACC1, #0x01 +0549 00ff ffcb SR @DSBL, $AC1.M +054b 02df RET + +// An identical copy of WaitForDMATransfer from 0536 +054c 00de ffc9 LR $AC0.M, @DSCR() +054e 02a0 0004 ANDCF $AC0.M, #0x0004 +0550 029c 054c JZR 0x054c +0552 02df RET + + +0553 193e LRRI $AC0.M, @$R01 +0554 193c LRRI $AC0.L, @$R01 +0555 0240 7fff ANDI $ACC0, #0x7fff +0557 02bf 0561 CALL 0x0561 // SetupAccelerator() +0559 007a 055f BLOOP $AX0.H, 0x055f +055b 26d3 LRS $AC0.M, @0xffd3 +055c 1b3e SRRI @$R01, $AC0.M +055d 0000 NOP +055e 0000 NOP +055f 0000 NOP +0560 02df RET + +// SetupAccelerator() +0561 1c3f MRR $R01, $AC1.M +0562 0f0a LRIS $AC1.M, #0x0a +0563 2fd1 SRS @SampleFormat, $AC1.M +0564 1f5e MRR $AX0.H, $AC0.M +0565 1f1c MRR $AX0.L, $AC0.L +0566 009e ffff LRI $AC0.M, #0xffff +0568 2ed6 SRS @ACEAH, $AC0.M +0569 2ed7 SRS @ACEAL, $AC0.M +056a 1fda MRR $AC0.M, $AX0.H +056b 1f98 MRR $AC0.L, $AX0.L +056c 147f LSR $ACC0, #0x3f +056d 2ed8 SRS @ACCAH, $AC0.M +056e 2cd9 SRS @ACCAL, $AC0.L +056f 1f40 MRR $AX0.H, $R00 +0570 02df RET + +// AC1.M is input which also falls into 0x0561. +0571 193e LRRI $AC0.M, @$R01 +0572 193c LRRI $AC0.L, @$R01 +0573 0090 0001 LRI $ACH0, #0x0001 +0575 02bf 0561 CALL 0x0561 // SetupAccelerator() +0577 007a 057e BLOOP $AX0.H, 0x057e +0579 193e LRRI $AC0.M, @$R01 +057a 2ed3 SRS @0xffd3, $AC0.M +057b 0000 NOP +057c 0000 NOP +057d 0000 NOP +057e 0000 NOP +057f 02df RET + + +// Opcode_04() +0580 0080 0346 LRI $R00, #0x0346 +0582 02bf 0067 CALL 0x0067 // ReadWholeMessage($R00) +0584 02bf 0067 CALL 0x0067 // ReadWholeMessage($R00) +0586 0081 0346 LRI $R01, #0x0346 +0588 00df 0349 LR $AC1.M, @0x0349 +058a 0340 ffff ANDI $ACC1, #0xffff +058c 00c0 0345 LR $R00, @0x0345 +058e 02bf 0523 CALL 0x0523 // RAMtoDMEM(DMEM=$AC1.M, *R01=MEMADDR, R00=Len) +0590 029f 0043 JMP 0x0043 + +// Opcode_05() +0592 0080 0346 LRI $R00, #0x0346 +0594 02bf 0067 CALL 0x0067 // ReadWholeMessage($R00) +0596 02bf 0067 CALL 0x0067 // ReadWholeMessage($R00) +0598 0081 0346 LRI $R01, #0x0346 +059a 00df 0349 LR $AC1.M, @0x0349 +059c 0340 ffff ANDI $ACC1, #0xffff +059e 00c0 0345 LR $R00, @0x0345 +05a0 02bf 0530 CALL 0x0530 // DMEMtoRAM(DMEM=$AC1.M, *R01=MEMADDR, R00=Len) +05a2 029f 0043 JMP 0x0043 + +// ClearAccelerator() +05a4 0092 00ff LRI $CR, #0x00ff +05a6 009e ffff LRI $AC0.M, #0xffff +05a8 2ed4 SRS @ACSAH, $AC0.M +05a9 2ed5 SRS @ACSAL, $AC0.M +05aa 2ed6 SRS @ACEAH, $AC0.M +05ab 2ed7 SRS @ACEAL, $AC0.M +05ac 02df RET + +// Set up accelerator to a sample format and point to a read location +05ad 00ff ffd1 SR @SampleFormat, $AC1.M +05af 0340 0003 ANDI $ACC1, #0x0003 +05b1 7900 DECM $AC1.M +05b2 02ca CW 0x02ca ; *** UNKNOWN OPCODE *** +05b3 00fe ffd8 SR @ACCAH, $AC0.M +05b5 00fc ffd9 SR @ACCAL, $AC0.L +05b7 02df RET + +// Is this statement really true? : +// Exception Handler (lvl 7) is called on new mails +05b8 1205 SBCLR #0x05 +05b9 8e00 S40 +05ba 00f0 03fd SR @0x03fd, $ACH0 +05bc 00fc 03ff SR @0x03ff, $AC0.L +05be f400 LSR16 $AC0.M +05bf 00fc 03fe SR @0x03fe, $AC0.L +05c1 00fa 03fa SR @0x03fa, $AX0.H +05c3 8100 CLR $AC0.M +05c4 00de fffe LR $AC0.M, @CMBH // Read mailbox +05c6 02c0 8000 ANDF $AC0.M, #0x8000 +05c8 029c 06b9 JZR 0x06b9 +05ca 00da ffff LR $AX0.H, @CMBL +05cc 8600 TSTAXH $AX0.H +05cd 0294 0692 JNE 0x0692 +05cf 00de fffe LR $AC0.M, @CMBH +05d1 02c0 8000 ANDF $AC0.M, #0x8000 +05d3 029c 05cf JZR 0x05cf +05d5 0240 000f ANDI $ACC0, #0x000f +05d7 1f5e MRR $AX0.H, $AC0.M +05d8 7400 INCM $AC0.M +05d9 0c00 LRIS $AC0.L, #0x00 +05da 1404 LSL $ACC0, #0x04 +05db 00fe 034e SR @0x034e, $AC0.M +05dd 1fda MRR $AC0.M, $AX0.H +05de 1f40 MRR $AX0.H, $R00 +05df 0200 04fc ADDI $ACC0, #0x04fc +05e1 1c1e MRR $R00, $AC0.M +05e2 00de ffff LR $AC0.M, @CMBL +05e4 1a1e SRR @$R00, $AC0.M +05e5 1c1a MRR $R00, $AX0.H +05e6 00de 03fe LR $AC0.M, @0x03fe +05e8 00dc 03ff LR $AC0.L, @0x03ff +05ea 00d0 03fd LR $ACH0, @0x03fd +05ec 00da 03fa LR $AX0.H, @0x03fa +05ee 1305 SBSET #0x05 +05ef 02ff RTI + +// StopUCode() +05f0 009a 0002 LRI $AX0.H, #0x0002 +05f2 00fa 03a3 SR @0x03a3, $AX0.H +05f4 00e0 03f9 SR @0x03f9, $R00 +05f6 02bf 067c CALL 0x067c // WaitForEmptyDSPMailBox_ovAC0.M() +05f8 16fc dcd1 SI @DMBH, #0xdcd1 +05fa 16fd 0002 SI @DMBL, #0x0002 +05fc 16fb 0001 SI @DIRQ, #0x0001 +05fe 0021 HALT + +// Looks like data more than it looks like code... yep, see 613. +05ff 0617 CMPIS $ACC0, #0x17 +0600 0618 CMPIS $ACC0, #0x18 +0601 0658 CMPIS $ACC0, #0x58 +0602 065b CMPIS $ACC0, #0x5b + +// Store a jump destination to RAM. Then get some data from the CPU. This data controls whether +// we will halt, reset, boot task or jump to function. +// This could very well be debug code. +0603 00e0 03f9 SR @0x03f9, $R00 +0605 009e 0005 LRI $AC0.M, #0x0005 +0607 02bf 066a CALL 0x066a // SendMessageViaDSPMailBox_DCD1(AC0.M) +0609 8e00 S40 +060a 8100 CLR $AC0.M +060b 8900 CLR $AC1.M +060c 02bf 065e CALL 0x065e +060e 27ff LRS $AC1.M, @CMBL +060f 009e 05ff LRI $AC0.M, #0x05ff +0611 4c00 ADD $AC0.M, $AC1.M +0612 1c7e MRR $R03, $AC0.M +0613 0313 ILRR $AC1.M, @$R03 // Jump table lookup. +0614 1c7f MRR $R03, $AC1.M +0615 176f JMPR $R03 +0616 0021 HALT + +// Jump table alt 0. A bit too simple :p +0617 0021 HALT + +// Jump table alt 1. Seems to simply receive a big list of register initialization +// values from the CPU. +// Ends by jumping into the rom - boot task? +// ATTENTION - sets up R06 and R07. +0618 009a 0002 LRI $AX0.H, #0x0002 +061a 00fa 03a3 SR @0x03a3, $AX0.H +061c 8100 CLR $AC0.M +061d 8900 CLR $AC1.M +061e 02bf 065e CALL 0x065e // wait for cpu mailbox +0620 24ff LRS $AC0.L, @CMBL +0621 02bf 0664 CALL 0x0664 // wait for cpu mailbox +0623 25ff LRS $AC1.L, @CMBL +0624 02bf 0664 CALL 0x0664 // wait for cpu mailbox +0626 27ff LRS $AC1.M, @CMBL +0627 2ece SRS @DSMAH, $AC0.M +0628 2ccf SRS @DSMAL, $AC0.L +0629 16c9 0001 SI @DSCR, #0x0001 +062b 2fcd SRS @DSPA, $AC1.M +062c 2dcb SRS @DSBL, $AC1.L +062d 8100 CLR $AC0.M +062e 8900 CLR $AC1.M +062f 02bf 065e CALL 0x065e // wait for cpu mailbox +0631 24ff LRS $AC0.L, @CMBL +0632 1c9e MRR $R04, $AC0.M +0633 1cbc MRR $R05, $AC0.L +0634 02bf 0664 CALL 0x0664 // wait for cpu mailbox +0636 25ff LRS $AC1.L, @CMBL +0637 02bf 0664 CALL 0x0664 // wait for cpu mailbox +0639 27ff LRS $AC1.M, @CMBL +063a 1cdf MRR $R06, $AC1.M +063b 1cfd MRR $R07, $AC1.L +063c 8100 CLR $AC0.M +063d 02bf 065e CALL 0x065e // wait for cpu mailbox +063f 26ff LRS $AC0.M, @CMBL +0640 1c1e MRR $R00, $AC0.M +0641 8900 CLR $AC1.M +0642 02bf 0664 CALL 0x0664 // wait for cpu mailbox +0644 20ff LRS $AX0.L, @CMBL +0645 1f5f MRR $AX0.H, $AC1.M +0646 02bf 065e CALL 0x065e // wait for cpu mailbox +0648 21ff LRS $AX1.L, @CMBL +0649 02bf 065e CALL 0x065e // wait for cpu mailbox +064b 23ff LRS $AX1.H, @CMBL +064c 26c9 LRS $AC0.M, @DSCR +064d 02a0 0004 ANDCF $AC0.M, #0x0004 +064f 029c 064c JZR 0x064c +// Clear some bits in SR. +0651 1206 SBCLR #0x06 +0652 1203 SBCLR #0x03 +0653 1204 SBCLR #0x04 +0654 1205 SBCLR #0x05 +// Jump into the ROM. (!) Boot task? +0655 029f 80b5 JMP 0x80b5 +0657 0021 HALT + +// Jump table alt 2. (reset DSP?) +0658 029f 8000 JMP 0x8000 +065a 0021 HALT + +// Jump table alt 3. Loads another jump destination and jumps there. +065b 00c0 03f9 LR $R00, @0x03f9 +065d 170f JMPR $R00 + +// Wait for CPU mailbox, trash ACC0. +065e 26fe LRS $AC0.M, @CMBH +065f 02c0 8000 ANDF $AC0.M, #0x8000 +0661 029c 065e JZR 0x065e +0663 02df RET + +// Wait for CPU mailbox, trash ACC1. +0664 27fe LRS $AC1.M, @CMBH +0665 03c0 8000 ANDF $AC1.M, #0x8000 +0667 029c 0664 JZR 0x0664 +0669 02df RET + +// SendMessageViaDSPMailBox_DCD1(AC0.M) +066a 02bf 0682 CALL 0x0682 // WaitForEmptyDSPMailBox_ovAC1.M() +066c 16fc dcd1 SI @DMBH, #0xdcd1 +066e 2efd SRS @DMBL, $AC0.M +066f 16fb 0001 SI @DIRQ, #0x0001 +0671 02bf 0682 CALL 0x0682 // WaitForEmptyDSPMailBox_ovAC1.M() +0673 02df RET + + + +// SendMessageViaDSPMailBox_F355(AC0.M) +0674 02bf 0682 CALL 0x0682 // WaitForEmptyDSPMailBox_ovAC1.M() +0676 16fc f355 SI @DMBH, #0xf355 +0678 2efd SRS @DMBL, $AC0.M +0679 02bf 0682 CALL 0x0682 // WaitForEmptyDSPMailBox_ovAC1.M() +067b 02df RET + +// WaitForEmptyDSPMailBox_ovAC0.M() +067c 26fc LRS $AC0.M, @DMBH +067d 02c0 8000 ANDF $AC0.M, #0x8000 +067f 029d 067c JNZ 0x067c +0681 02df RET + +// WaitForEmptyDSPMailBox_ovAC1.M() +0682 27fc LRS $AC1.M, @DMBH +0683 03c0 8000 ANDF $AC1.M, #0x8000 +0685 029d 0682 JNZ 0x0682 +0687 02df RET + +// InitGlobalsVars() +0688 009a 0280 LRI $AX0.H, #0x0280 +068a 00fa 0350 SR @0x0350, $AX0.H +068c 00fa 0351 SR @0x0351, $AX0.H +068e 0a00 LRIS $AX0.H, #0x00 +068f 00fa 0352 SR @0x0352, $AX0.H +0691 02df RET + +// Huh, the 7 exception handler sends us here? +// Uses loop indexing (R08) +0692 00e0 03fb SR @0x03fb, $R00 +0694 00e8 03fc SR @0x03fc, $R08 +0696 00c0 0350 LR $R00, @0x0350 +0698 0088 002f LRI $R08, #0x002f +069a 1b1a SRRI @$R00, $AX0.H +069b 00de fffe LR $AC0.M, @CMBH +069d 02c0 8000 ANDF $AC0.M, #0x8000 +069f 029c 069b JZR 0x069b +06a1 00dc ffff LR $AC0.L, @CMBL +06a3 1b1e SRRI @$R00, $AC0.M +06a4 1b1c SRRI @$R00, $AC0.L +06a5 1fda MRR $AC0.M, $AX0.H +06a6 7800 DECM $AC0.M +06a7 1f5e MRR $AX0.H, $AC0.M +06a8 8600 TSTAXH $AX0.H +06a9 0294 069b JNE 0x069b +06ab 8100 CLR $AC0.M +06ac 00de 0352 LR $AC0.M, @0x0352 +06ae 7400 INCM $AC0.M +06af 00fe 0352 SR @0x0352, $AC0.M +06b1 00e0 0350 SR @0x0350, $R00 +06b3 00c0 03fb LR $R00, @0x03fb +06b5 00c8 03fc LR $R08, @0x03fc +06b7 029f 05e6 JMP 0x05e6 +06b9 00e0 03fb SR @0x03fb, $R00 +06bb 00e8 03fc SR @0x03fc, $R08 +06bd 00c0 0350 LR $R00, @0x0350 +06bf 0088 002f LRI $R08, #0x002f +06c1 0a00 LRIS $AX0.H, #0x00 +06c2 1b1a SRRI @$R00, $AX0.H +06c3 029f 06ab JMP 0x06ab + + +// MessageLoop() +06c5 00c0 0351 LR $R00, @0x0351 +06c7 0088 002f LRI $R08, #0x002f + +06c9 00da 0352 LR $AX0.H, @0x0352 +06cb 8600 TSTAXH $AX0.H +06cc 0295 06ed JEQ 0x06ed +06ce 1205 SBCLR #0x05 +06cf 00da 0352 LR $AX0.H, @0x0352 +06d1 1fda MRR $AC0.M, $AX0.H +06d2 7800 DECM $AC0.M +06d3 00fe 0352 SR @0x0352, $AC0.M +06d5 1305 SBSET #0x05 +06d6 0081 0356 LRI $R01, #0x0356 +06d8 191e LRRI $AC0.M, @$R00 +06d9 02c0 8000 ANDF $AC0.M, #0x8000 +06db 029d 06f1 JNZ 0x06f1 +06dd 1f5e MRR $AX0.H, $AC0.M +06de 8600 TSTAXH $AX0.H +06df 0295 06f5 JEQ 0x06f5 +06e1 007a 06e6 BLOOP $AX0.H, 0x06e6 +06e3 191e LRRI $AC0.M, @$R00 +06e4 1b3e SRRI @$R01, $AC0.M +06e5 191e LRRI $AC0.M, @$R00 +06e6 1b3e SRRI @$R01, $AC0.M +06e7 00e0 0351 SR @0x0351, $R00 +06e9 0088 ffff LRI $R08, #0xffff +06eb 029f 002f JMP 0x002f // Command handler. + +06ed 0088 ffff LRI $R08, #0xffff +06ef 029f 002d JMP 0x002d // Just jumps back to MessageLoop + +// Store the current command, jump back to MessageLoop+2. +06f1 00e0 0351 SR @0x0351, $R00 +06f3 029f 06c9 JMP 0x06c9 + +// Default command, jump back to MessageLoop? +06f5 0080 06c5 LRI $R00, #0x06c5 +06f7 029f 05f0 JMP 0x05f0 // StopUCode() + + +// Tests the value at M(0x0032) +06f9 8100 CLR $AC0.M +06fa 0e10 LRIS $AC0.M, #0x10 +06fb 2232 LRS $AX0.H, @0x0032 +06fc 8600 TSTAXH $AX0.H +06fd 02d5 RETEQ +06fe 5400 SUBR $AC0.M, $AX0.H +06ff 0200 0458 ADDI $ACC0, #0x0458 +0701 1c1e MRR $R00, $AC0.M +0702 1fda MRR $AC0.M, $AX0.H +0703 04fe ADDIS $ACC0, #0xfe +0704 1f1e MRR $AX0.L, $AC0.M +0705 191e LRRI $AC0.M, @$R00 +0706 0291 070c JX1 0x070c +0708 191a LRRI $AX0.H, @$R00 +0709 0058 LOOP $AX0.L +070a 64a0 MOVR.LS $AC0.M, $AX0.H : $AX0.H, $AC0.M +070b 6433 MOVR.S $AC0.M, $AX0.H : @$R03, $AC0.M +070c 1b7e SRRI @$R03, $AC0.M +070d 02df RET + + +// M(0x0032) must be important... +070e 02bf 06f9 CALL 0x06f9 +0710 8100 CLR $AC0.M +0711 2632 LRS $AC0.M, @0x0032 +0712 5c00 SUB $AC0.M, $AC1.M +0713 2e32 SRS @0x0032, $AC0.M +0714 0092 00ff LRI $CR, #0x00ff +0716 02df RET + + +// Copies some values from hardware to dram. +0717 00de 04fb LR $AC0.M, @0x04fb +0719 7400 INCM $AC0.M +071a 00fe 04fb SR @0x04fb, $AC0.M +071c 8100 CLR $AC0.M +071d 2e32 SRS @0x0032, $AC0.M +071e 2e66 SRS @0x0066, $AC0.M +071f 2e67 SRS @0x0067, $AC0.M +0720 268a LRS $AC0.M, @0xff8a // What HW is this? +0721 248b LRS $AC0.L, @0xff8b +0722 2e3a SRS @0x003a, $AC0.M +0723 2c3b SRS @0x003b, $AC0.L +0724 268c LRS $AC0.M, @0xff8c +0725 248d LRS $AC0.L, @0xff8d +0726 2e38 SRS @0x0038, $AC0.M +0727 2c39 SRS @0x0039, $AC0.L +0728 02df RET + + + +0729 8100 CLR $AC0.M +072a 2689 LRS $AC0.M, @0xff89 +072b 0240 000f ANDI $ACC0, #0x000f +072d 1f5e MRR $AX0.H, $AC0.M +072e 8100 CLR $AC0.M +072f 0e10 LRIS $AC0.M, #0x10 +0730 5400 SUBR $AC0.M, $AX0.H +0731 2e32 SRS @0x0032, $AC0.M +0732 268a LRS $AC0.M, @0xff8a +0733 248b LRS $AC0.L, @0xff8b +0734 2288 LRS $AX0.H, @0xff88 +0735 2089 LRS $AX0.L, @0xff89 +0736 5800 SUBAX $AC0.M, $AX0.L +0737 0a00 LRIS $AX0.H, #0x00 +0738 2032 LRS $AX0.L, @0x0032 +0739 5800 SUBAX $AC0.M, $AX0.L +073a 2e3a SRS @0x003a, $AC0.M +073b 2c3b SRS @0x003b, $AC0.L +073c 02df RET + + +// Call, or not, 0x717 with some params. +// CR loading is .. suspicious :P +073d 0092 0004 LRI $CR, #0x0004 +073f 8100 CLR $AC0.M +0740 2604 LRS $AC0.M, @0x0004 +0741 b100 TST $AC0.M +0742 02b4 0717 CALLNE 0x0717 +0744 8100 CLR $AC0.M +0745 2601 LRS $AC0.M, @0x0001 +0746 b100 TST $AC0.M +0747 0294 07e5 JNE 0x07e5 +//.. +0749 2232 LRS $AX0.H, @0x0032 +074a c900 CMPAXH $AC0.M, $AX1.H +074b 0293 070e JX3 0x070e +074d 5500 SUBR $AC1.M, $AX0.H +074e 02bf 06f9 CALL 0x06f9 +0750 223a LRS $AX0.H, @0x003a +0751 8600 TSTAXH $AX0.H +0752 0294 0759 JNE 0x0759 +0754 8100 CLR $AC0.M +0755 263b LRS $AC0.M, @0x003b +0756 8200 CMP +0757 0291 07ab JX1 0x07ab +0759 8100 CLR $AC0.M +075a 1fdf MRR $AC0.M, $AC1.M +075b 040f ADDIS $ACC0, #0x0f +075c 147c LSR $ACC0, #0x3c +075d 1f7e MRR $AX1.H, $AC0.M +075e 0c00 LRIS $AC0.L, #0x00 +075f 1404 LSL $ACC0, #0x04 +0760 1f1e MRR $AX0.L, $AC0.M +0761 0a00 LRIS $AX0.H, #0x00 +0762 8100 CLR $AC0.M +0763 263a LRS $AC0.M, @0x003a +0764 243b LRS $AC0.L, @0x003b +0765 5800 SUBAX $AC0.M, $AX0.L +0766 0290 0771 JX0 0x0771 +0768 8100 CLR $AC0.M +0769 263b LRS $AC0.M, @0x003b +076a 5c00 SUB $AC0.M, $AC1.M +076b 2e32 SRS @0x0032, $AC0.M +076c 8100 CLR $AC0.M +076d 2e3a SRS @0x003a, $AC0.M +076e 2e3b SRS @0x003b, $AC0.M +076f 029f 0777 JMP 0x0777 + +//.. Jump target from 0766 +0771 2e3a SRS @0x003a, $AC0.M +0772 2c3b SRS @0x003b, $AC0.L +0773 0c00 LRIS $AC0.L, #0x00 +0774 1fd8 MRR $AC0.M, $AX0.L +0775 5c00 SUB $AC0.M, $AC1.M +0776 2e32 SRS @0x0032, $AC0.M +//.. Jump target from 076f +0777 8100 CLR $AC0.M +0778 1fdb MRR $AC0.M, $AX1.H +0779 02bf 07eb CALL 0x07eb +077b 2232 LRS $AX0.H, @0x0032 +077c 8600 TSTAXH $AX0.H +077d 0295 07a8 JEQ 0x07a8 // bail +077f 0a10 LRIS $AX0.H, #0x10 +0780 8100 CLR $AC0.M +0781 1fc3 MRR $AC0.M, $R03 +0782 5400 SUBR $AC0.M, $AX0.H +0783 1c7e MRR $R03, $AC0.M +0784 0080 0458 LRI $R00, #0x0458 +0786 197e LRRI $AC0.M, @$R03 +0787 197a LRRI $AX0.H, @$R03 +0788 100e LOOPI #0x0e +0789 64a2 MOVR.SL $AC0.M, $AX0.H : $AC0.M, $AX0.H +078a 1b1e SRRI @$R00, $AC0.M +078b 1b1a SRRI @$R00, $AX0.H +078c 8100 CLR $AC0.M +078d 263a LRS $AC0.M, @0x003a +078e 243b LRS $AC0.L, @0x003b +078f b100 TST $AC0.M +0790 0294 07a8 JNE 0x07a8 // bail +0792 2232 LRS $AX0.H, @0x0032 +0793 8600 TSTAXH $AX0.H +0794 0295 07a8 JEQ 0x07a8 // bail +0796 0080 0467 LRI $R00, #0x0467 +0798 8100 CLR $AC0.M +0799 268b LRS $AC0.M, @0xff8b +079a b100 TST $AC0.M +079b 0295 07a8 JEQ 0x07a8 // bail +079d 0200 000f ADDI $ACC0, #0x000f +079f 0240 000f ANDI $ACC0, #0x000f +07a1 0200 0458 ADDI $ACC0, #0x0458 +07a3 1c7e MRR $R03, $AC0.M +07a4 007a 07a7 BLOOP $AX0.H, 0x07a7 +07a6 18fe LRRD $AC0.M, @$R03 +07a7 1a9e SRRD @$R00, $AC0.M +//.. +07a8 0092 00ff LRI $CR, #0x00ff +07aa 02df RET + + + +07ab b100 TST $AC0.M +07ac 0295 07bb JEQ 0x07bb +07ae 5d00 SUB $AC1.M, $AC0.M +07af 040f ADDIS $ACC0, #0x0f +07b0 147c LSR $ACC0, #0x3c +07b1 0c00 LRIS $AC0.L, #0x00 +07b2 00e3 0363 SR @0x0363, $R03 +07b4 02bf 07eb CALL 0x07eb +07b6 00de 0363 LR $AC0.M, @0x0363 +07b8 223b LRS $AX0.H, @0x003b +07b9 4400 ADDR $AC0.M, $AX0.H +07ba 1c7e MRR $R03, $AC0.M +07bb 8100 CLR $AC0.M +07bc 2681 LRS $AC0.M, @0xff81 +07bd b100 TST $AC0.M +07be 0295 07e3 JEQ 0x07e3 // memset +07c0 2380 LRS $AX1.H, @0xff80 +07c1 2688 LRS $AC0.M, @0xff88 +07c2 2489 LRS $AC0.L, @0xff89 +07c3 1408 LSL $ACC0, #0x08 +07c4 14f4 ASR $ACC0, #0x74 +07c5 2380 LRS $AX1.H, @0xff80 +07c6 8d00 SET15 +07c7 c810 MULC.MV $AX1.H, $AC0.M : $AX0.L, $AC0.L +07c8 ae00 MULXMV $AX0.L, $AX1.H, $AC0.M +07c9 8c00 CLR15 +07ca f000 LSL16 $AC0.M +07cb 4e00 ADDP $AC0.M +07cc 238c LRS $AX1.H, @0xff8c +07cd 218d LRS $AX1.L, @0xff8d +07ce 4a00 ADDAX $AC0.M, $AX1.L +07cf 2e38 SRS @0x0038, $AC0.M +07d0 2c39 SRS @0x0039, $AC0.L +07d1 2682 LRS $AC0.M, @0xff82 +07d2 2e67 SRS @0x0067, $AC0.M +07d3 2683 LRS $AC0.M, @0xff83 +07d4 2e66 SRS @0x0066, $AC0.M +07d5 00e3 0363 SR @0x0363, $R03 +07d7 0083 0458 LRI $R03, #0x0458 +07d9 8100 CLR $AC0.M +07da 0e01 LRIS $AC0.M, #0x01 +07db 02bf 07eb CALL 0x07eb +07dd 00c3 0363 LR $R03, @0x0363 +07df 02bf 0729 CALL 0x0729 +07e1 029f 0749 JMP 0x0749 + + +// loop count = AC1.M +// strange - stores the value 1 at [1]. +// then just memset 0 and a CR=0xff. +07e3 0e01 LRIS $AC0.M, #0x01 +07e4 2e01 SRS @0x0001, $AC0.M +07e5 8100 CLR $AC0.M +07e6 005f LOOP $AC1.M +07e7 1b7e SRRI @$R03, $AC0.M +07e8 0092 00ff LRI $CR, #0x00ff +07ea 02df RET + + + +07eb 00ff 0360 SR @0x0360, $AC1.M +07ed 00fe 0361 SR @0x0361, $AC0.M +07ef 2638 LRS $AC0.M, @0x0038 +07f0 2439 LRS $AC0.L, @0x0039 +07f1 0f05 LRIS $AC1.M, #0x05 +07f2 02bf 05ad CALL 0x05ad +07f4 2638 LRS $AC0.M, @0x0038 +07f5 2439 LRS $AC0.L, @0x0039 +07f6 8900 CLR $AC1.M +07f7 00df 0361 LR $AC1.M, @0x0361 +07f9 2280 LRS $AX0.H, @0xff80 +07fa d000 MULC $AX0.H, $AC1.M +07fb 6f00 MOVP $AC1.M +07fc 4c00 ADD $AC0.M, $AC1.M +07fd 2e38 SRS @0x0038, $AC0.M +07fe 2c39 SRS @0x0039, $AC0.L +07ff 8100 CLR $AC0.M +0800 00de 0361 LR $AC0.M, @0x0361 +0802 007e 086b BLOOP $AC0.M, 0x086b +0804 0080 ffd3 LRI $R00, #0xffd3 +0806 0084 0000 LRI $R04, #0x0000 +0808 199e LRRN $AC0.M, @$R00 +0809 8900 CLR $AC1.M +080a 1ffe MRR $AC1.M, $AC0.M +080b 1401 LSL $ACC0, #0x01 +080c 0240 001e ANDI $ACC0, #0x001e +080e 0200 0300 ADDI $ACC0, #0x0300 +0810 1c3e MRR $R01, $AC0.M +0811 157c LSR $ACC1, #0x3c +0812 0340 000f ANDI $ACC1, #0x000f +0814 0a11 LRIS $AX0.H, #0x11 +0815 5500 SUBR $AC1.M, $AX0.H +0816 8100 CLR $AC0.M +0817 2680 LRS $AC0.M, @0xff80 +0818 0605 CMPIS $ACC0, #0x05 +0819 0295 0832 JEQ 0x0832 +081b 009a 00f0 LRI $AX0.H, #0x00f0 +081d 0b0f LRIS $AX1.H, #0x0f +081e 0082 0364 LRI $R02, #0x0364 +0820 1998 LRRN $AX0.L, @$R00 +0821 6000 MOVR $AC0.M, $AX0.L +0822 1107 0829 BLOOPI #0x07, 0x0829 +0824 3400 ANDR $AC0.M, $AX0.H +0825 1408 LSL $ACC0, #0x08 +0826 6032 MOVR.S $AC0.M, $AX0.L : @$R02, $AC0.M +0827 3644 ANDR.LN $AC0.M, $AX1.H : $AX0.L, @$R00 +0828 140c LSL $ACC0, #0x0c +0829 6032 MOVR.S $AC0.M, $AX0.L : @$R02, $AC0.M +082a 3400 ANDR $AC0.M, $AX0.H +082b 1408 LSL $ACC0, #0x08 +082c 6032 MOVR.S $AC0.M, $AX0.L : @$R02, $AC0.M +082d 3600 ANDR $AC0.M, $AX1.H +082e 140c LSL $ACC0, #0x0c +082f 1b5e SRRI @$R02, $AC0.M +0830 029f 0852 JMP 0x0852 + + + +0832 009a c000 LRI $AX0.H, #0xc000 +0834 0082 0364 LRI $R02, #0x0364 +0836 1998 LRRN $AX0.L, @$R00 +0837 6000 MOVR $AC0.M, $AX0.L +0838 1103 0845 BLOOPI #0x03, 0x0845 +083a 1408 LSL $ACC0, #0x08 +083b 3400 ANDR $AC0.M, $AX0.H +083c 6032 MOVR.S $AC0.M, $AX0.L : @$R02, $AC0.M +083d 140a LSL $ACC0, #0x0a +083e 3400 ANDR $AC0.M, $AX0.H +083f 6032 MOVR.S $AC0.M, $AX0.L : @$R02, $AC0.M +0840 140c LSL $ACC0, #0x0c +0841 3400 ANDR $AC0.M, $AX0.H +0842 6032 MOVR.S $AC0.M, $AX0.L : @$R02, $AC0.M +0843 140e LSL $ACC0, #0x0e +0844 3444 ANDR.LN $AC0.M, $AX0.H : $AX0.L, @$R00 +0845 6032 MOVR.S $AC0.M, $AX0.L : @$R02, $AC0.M +0846 1408 LSL $ACC0, #0x08 +0847 3400 ANDR $AC0.M, $AX0.H +0848 6032 MOVR.S $AC0.M, $AX0.L : @$R02, $AC0.M +0849 140a LSL $ACC0, #0x0a +084a 3400 ANDR $AC0.M, $AX0.H +084b 6032 MOVR.S $AC0.M, $AX0.L : @$R02, $AC0.M +084c 140c LSL $ACC0, #0x0c +084d 3400 ANDR $AC0.M, $AX0.H +084e 6032 MOVR.S $AC0.M, $AX0.L : @$R02, $AC0.M +084f 140e LSL $ACC0, #0x0e +0850 3400 ANDR $AC0.M, $AX0.H +0851 1b5e SRRI @$R02, $AC0.M +0852 8f00 S16 +0853 1f7f MRR $AX1.H, $AC1.M +0854 2066 LRS $AX0.L, @0x0066 +0855 2767 LRS $AC1.M, @0x0067 +0856 193a LRRI $AX0.H, @$R01 +0857 1939 LRRI $AX1.L, @$R01 +0858 0080 0364 LRI $R00, #0x0364 +085a 1c80 MRR $R04, $R00 +085b a000 MULX $AX0.L, $AX1.L +085c ea70 MADDC.L $AC1.M, $AX1.L : $AC0.M, @$R00 +085d 1108 0866 BLOOPI #0x08, 0x0866 +085f 3a93 ORR.SL $AC0.M, $AX1.H : $AC1.M, $AX1.L +0860 a478 MULXAC.L $AX0.L, $AX1.L, $AC0.M : $AC1.M, @$R00 +0861 1485 ASL $ACC0, #0x05 +0862 e833 MADDC.S $AC0.M, $AX1.L : @$R03, $AC0.M +0863 3b92 ORR.SL $AC1.M, $AX1.H : $AC0.M, $AX1.L +0864 a570 MULXAC.L $AX0.L, $AX1.L, $AC1.M : $AC0.M, @$R00 +0865 1585 ASL $ACC1, #0x05 +0866 ea3b MADDC.S $AC1.M, $AX1.L : @$R03, $AC1.M +0867 2f67 SRS @0x0067, $AC1.M +0868 8e00 S40 +0869 1ff8 MRR $AC1.M, $AX0.L +086a 2f66 SRS @0x0066, $AC1.M +086b 8900 CLR $AC1.M +086c 00df 0360 LR $AC1.M, @0x0360 +086e 02df RET + + +086f b100 TST $AC0.M +0870 02d5 RETEQ +0871 04fe ADDIS $ACC0, #0xfe +0872 1f1e MRR $AX0.L, $AC0.M +0873 191e LRRI $AC0.M, @$R00 +0874 0291 087a JX1 0x087a +0876 191a LRRI $AX0.H, @$R00 +0877 0058 LOOP $AX0.L +0878 64a0 MOVR.LS $AC0.M, $AX0.H : $AX0.H, $AC0.M +0879 6433 MOVR.S $AC0.M, $AX0.H : @$R03, $AC0.M +087a 1b7e SRRI @$R03, $AC0.M +087b 02df RET + + +// Another jump table dispatcher. Not sure what it is. +087c 8100 CLR $AC0.M +087d 1f5e MRR $AX0.H, $AC0.M +087e 00d8 0402 LR $AX0.L, @0x0402 +0880 00dc 0430 LR $AC0.L, @0x0430 +0882 0080 0520 LRI $R00, #0x0520 +0884 00df 0480 LR $AC1.M, @0x0480 +0886 1501 LSL $ACC1, #0x01 +0887 0340 007e ANDI $ACC1, #0x007e +0889 0300 0891 ADDI $ACC1, #0x0891 +088b 1c5f MRR $R02, $AC1.M +088c 175f CALLR $R02 +088d 00fc 0430 SR @0x0430, $AC0.L +088f 029f 02d8 JMP 0x02d8 // 0 +0891 029f 08b2 JMP 0x08b2 // 1 +0893 029f 08ed JMP 0x08ed // 2 +0895 029f 08d5 JMP 0x08d5 // 3 +0897 029f 08c2 JMP 0x08c2 // 4 +0899 029f 08fb JMP 0x08fb // 5 +089b 029f 08b1 JMP 0x08b1 // 6 +089d 029f 0919 JMP 0x0919 // 7 +089f 029f 091c JMP 0x091c // 8 +08a1 029f 08b1 JMP 0x08b1 // 9 +08a3 029f 08b1 JMP 0x08b1 // 10 +08a5 029f 093a JMP 0x093a // 11 +08a7 029f 08f3 JMP 0x08f3 // 12 +08a9 029f 08f7 JMP 0x08f7 // 13 +08ab 029f 08b1 JMP 0x08b1 // 14 +08ad 029f 08b1 JMP 0x08b1 // 15 +08af 029f 08b1 JMP 0x08b1 // 16 (huh? one too much) + +// 88c Call targets 6, 9, 10, 14, 15, 16. (Nop) +08b1 02df RET + +// Could this stuff be some zany audio decompression? +// CT1 seems to unpack the bits of ac0 and write either +// 0xc000 or 0x4000 to the output depending on 1 bit of acc0. +// CT4 does the same but depends on 2 bits of acc0. +// CT3 is similar but also seems to accumulate some value. +// CT2 just stores a ramp. +// Not sure what CT5 does. +// CT12 and CT13 are variants of CT5. +// CT7 is just a memset. +// + +// 88c Call target 1. +08b2 1401 LSL $ACC0, #0x01 +08b3 009b c000 LRI $AX1.H, #0xc000 +08b5 0099 4000 LRI $AX1.L, #0x4000 +08b7 1150 08bf BLOOPI #0x50, 0x08bf +08b9 02c0 0001 ANDF $AC0.M, #0x0001 +08bb 027c IF_R +08bc 1b1b SRRI @$R00, $AX1.H +08bd 027d IF_Z +08be 1b19 SRRI @$R00, $AX1.L +08bf 4800 ADDAX $AC0.M, $AX0.L +08c0 147f LSR $ACC0, #0x3f +08c1 02df RET + +// 88c Call target 4. +08c2 1402 LSL $ACC0, #0x02 +08c3 8900 CLR $AC1.M +08c4 1fb8 MRR $AC1.L, $AX0.L +08c5 1501 LSL $ACC1, #0x01 +08c6 009b c000 LRI $AX1.H, #0xc000 +08c8 0099 4000 LRI $AX1.L, #0x4000 +08ca 1150 08d2 BLOOPI #0x50, 0x08d2 +08cc 02c0 0003 ANDF $AC0.M, #0x0003 +08ce 027c IF_R +08cf 1b1b SRRI @$R00, $AX1.H +08d0 027d IF_Z +08d1 1b19 SRRI @$R00, $AX1.L +08d2 4c00 ADD $AC0.M, $AC1.M +08d3 147e LSR $ACC0, #0x3e +08d4 02df RET + +// 88c Call target 3. +08d5 1401 LSL $ACC0, #0x01 +08d6 0081 0ca0 LRI $R01, #0x0ca0 +08d8 009b c000 LRI $AX1.H, #0xc000 +08da 0099 4000 LRI $AX1.L, #0x4000 +08dc 8900 CLR $AC1.M +08dd 0082 0000 LRI $R02, #0x0000 +08df 1150 08ea BLOOPI #0x50, 0x08ea +08e1 02c0 0001 ANDF $AC0.M, #0x0001 +08e3 027c IF_R +08e4 1b1b SRRI @$R00, $AX1.H +08e5 027d IF_Z +08e6 1b19 SRRI @$R00, $AX1.L +08e7 183d LRR $AC1.L, @$R01 +08e8 4900 ADDAX $AC1.M, $AX0.L +08e9 1fe2 MRR $AC1.M, $R02 +08ea 4c39 ADD.S $AC0.M, $AC1.M : @$R01, $AC1.M +08eb 147f LSR $ACC0, #0x3f +08ec 02df RET + +// 88c Call target 2. +08ed 8900 CLR $AC1.M +08ee 1fb8 MRR $AC1.L, $AX0.L +08ef 157f LSR $ACC1, #0x3f +08f0 1050 LOOPI #0x50 +08f1 4c20 ADD.S $AC0.M, $AC1.M : @$R00, $AC0.L +08f2 02df RET + +// 88c Call target 12. +08f3 0082 0180 LRI $R02, #0x0180 +08f5 029f 08fd JMP 0x08fd + +// 88c Call target 13. +08f7 0082 01c0 LRI $R02, #0x01c0 +08f9 029f 08fd JMP 0x08fd + +// 88c Call target 5. +08fb 0082 0140 LRI $R02, #0x0140 +// 88c targets 12 and 13 forward here with different R02 value. +08fd 008a 003f LRI $R10, #0x003f +08ff 0086 0000 LRI $R06, #0x0000 +0901 1406 LSL $ACC0, #0x06 +0902 8900 CLR $AC1.M +0903 1fb8 MRR $AC1.L, $AX0.L +0904 1505 LSL $ACC1, #0x05 +0905 009b 003f LRI $AX1.H, #0x003f +0907 009a 0000 LRI $AX0.H, #0x0000 +0909 3600 ANDR $AC0.M, $AX1.H +090a 1cde MRR $R06, $AC0.M +090b 001a CW 0x001a ; *** UNKNOWN OPCODE *** +090c 3400 ANDR $AC0.M, $AX0.H +090d 1150 0913 BLOOPI #0x50, 0x0913 +090f 4c4a ADD.L $AC0.M, $AC1.M : $AX1.L, @$R02 +0910 3606 ANDR.DR $AC0.M, $AX1.H : $R02 +0911 1cde MRR $R06, $AC0.M +0912 340e ANDR.NR $AC0.M, $AX0.H : $R02 +0913 1b19 SRRI @$R00, $AX1.L +0914 1fc2 MRR $AC0.M, $R02 +0915 147a LSR $ACC0, #0x3a +0916 008a ffff LRI $R10, #0xffff +0918 02df RET + +// 88c Call target 7. +0919 1050 LOOPI #0x50 +091a 1b18 SRRI @$R00, $AX0.L +091b 02df RET + +// 88c Call target 8. +091c 0082 0100 LRI $R02, #0x0100 +091e 008a 003f LRI $R10, #0x003f +0920 0086 0000 LRI $R06, #0x0000 +0922 1406 LSL $ACC0, #0x06 +0923 8900 CLR $AC1.M +0924 1fb8 MRR $AC1.L, $AX0.L +0925 1505 LSL $ACC1, #0x05 +0926 009b 003f LRI $AX1.H, #0x003f +0928 009a 0000 LRI $AX0.H, #0x0000 +092a 3600 ANDR $AC0.M, $AX1.H +092b 1cde MRR $R06, $AC0.M +092c 001a CW 0x001a ; *** UNKNOWN OPCODE *** +092d 3400 ANDR $AC0.M, $AX0.H +092e 1150 0934 BLOOPI #0x50, 0x0934 +0930 4c4a ADD.L $AC0.M, $AC1.M : $AX1.L, @$R02 +0931 3606 ANDR.DR $AC0.M, $AX1.H : $R02 +0932 1cde MRR $R06, $AC0.M +0933 340e ANDR.NR $AC0.M, $AX0.H : $R02 +0934 1b19 SRRI @$R00, $AX1.L +0935 1fc2 MRR $AC0.M, $R02 +0936 147a LSR $ACC0, #0x3a +0937 008a ffff LRI $R10, #0xffff +0939 02df RET + + +// 88c Call target 11. +093a 0082 0100 LRI $R02, #0x0100 +093c 008a 003f LRI $R10, #0x003f +093e 0086 0000 LRI $R06, #0x0000 +0940 0081 0ca0 LRI $R01, #0x0ca0 +0942 1406 LSL $ACC0, #0x06 +0943 8900 CLR $AC1.M +0944 1fb8 MRR $AC1.L, $AX0.L +0945 1505 LSL $ACC1, #0x05 +0946 009b 003f LRI $AX1.H, #0x003f +0948 009a 0000 LRI $AX0.H, #0x0000 +094a 3600 ANDR $AC0.M, $AX1.H +094b 1cde MRR $R06, $AC0.M +094c 001a CW 0x001a ; *** UNKNOWN OPCODE *** +094d 3400 ANDR $AC0.M, $AX0.H +094e 1150 0959 BLOOPI #0x50, 0x0959 +0950 1939 LRRI $AX1.L, @$R01 +0951 a000 MULX $AX0.L, $AX1.L +0952 140a LSL $ACC0, #0x0a +0953 4e00 ADDP $AC0.M +0954 1476 LSR $ACC0, #0x36 +0955 4c4a ADD.L $AC0.M, $AC1.M : $AX1.L, @$R02 +0956 3606 ANDR.DR $AC0.M, $AX1.H : $R02 +0957 1cde MRR $R06, $AC0.M +0958 340e ANDR.NR $AC0.M, $AX0.H : $R02 +0959 1b19 SRRI @$R00, $AX1.L +095a 1fc2 MRR $AC0.M, $R02 +095b 147a LSR $ACC0, #0x3a +095c 008a ffff LRI $R10, #0xffff +095e 02df RET + + +// recalculate some 020-sized table? +095f 0080 01be LRI $R00, #0x01be +0961 1918 LRRI $AX0.L, @$R00 +0962 191a LRRI $AX0.H, @$R00 +0963 0080 0180 LRI $R00, #0x0180 +0965 0083 0180 LRI $R03, #0x0180 +0967 9070 MUL.L $AX0.L, $AX0.H : $AC0.M, @$R00 +0968 1ffe MRR $AC1.M, $AC0.M +0969 1120 0970 BLOOPI #0x20, 0x0970 +096b 7c00 NEG $AC0.M +096c d450 MULCAC.L $AX0.H, $AC1.M, $AC0.M : $AX0.H, @$R00 +096d 6533 MOVR.S $AC1.M, $AX0.H : @$R03, $AC0.M +096e c550 MULCAC.L $AX0.H, $AC0.M, $AC1.M : $AX0.H, @$R00 +096f 1501 LSL $ACC1, #0x01 +0970 643b MOVR.S $AC0.M, $AX0.H : @$R03, $AC1.M +0971 0080 01fe LRI $R00, #0x01fe +0973 191a LRRI $AX0.H, @$R00 +0974 1918 LRRI $AX0.L, @$R00 +0975 0080 01c0 LRI $R00, #0x01c0 +0977 0083 01c0 LRI $R03, #0x01c0 +0979 1ff8 MRR $AC1.M, $AX0.L +097a 9070 MUL.L $AX0.L, $AX0.H : $AC0.M, @$R00 +097b f800 ADDPAXZ $AC0.M, $AX0.H +097c 0240 01ff ANDI $ACC0, #0x01ff +097e 0260 2000 ORI $ACC0, #0x2000 +0980 02bf 0983 CALL 0x0983 +0982 02df RET + + + +0983 b900 TST $AC1.M +0984 0272 IF_2 +0985 7c00 NEG $AC0.M +0986 1f7e MRR $AX1.H, $AC0.M +0987 4700 ADDR $AC1.M, $AX1.H +0988 1110 098d BLOOPI #0x10, 0x098d +098a 473b ADDR.S $AC1.M, $AX1.H : @$R03, $AC1.M +098b 473b ADDR.S $AC1.M, $AX1.H : @$R03, $AC1.M +098c 473b ADDR.S $AC1.M, $AX1.H : @$R03, $AC1.M +098d 473b ADDR.S $AC1.M, $AX1.H : @$R03, $AC1.M +098e 02df RET + + + +098f 0092 0004 LRI $CR, #0x0004 +0991 2002 LRS $AX0.L, @0x0002 +0992 8100 CLR $AC0.M +0993 8900 CLR $AC1.M +0994 2430 LRS $AC0.L, @0x0030 +0995 8d00 SET15 +0996 0950 LRIS $AX1.L, #0x50 +0997 a000 MULX $AX0.L, $AX1.L +0998 a400 MULXAC $AX0.L, $AX1.L, $AC0.M +0999 1404 LSL $ACC0, #0x04 +099a 8c00 CLR15 +099b 1ffe MRR $AC1.M, $AC0.M +099c 0083 0580 LRI $R03, #0x0580 +099e 2201 LRS $AX0.H, @0x0001 +099f 8600 TSTAXH $AX0.H +09a0 0294 09b1 JNE 0x09b1 +09a2 2204 LRS $AX0.H, @0x0004 +09a3 8600 TSTAXH $AX0.H +09a4 02b4 09f9 CALLNE 0x09f9 +09a6 8100 CLR $AC0.M +09a7 2605 LRS $AC0.M, @0x0005 +09a8 b100 TST $AC0.M +09a9 0295 09be JEQ 0x09be +09ab 8100 CLR $AC0.M +09ac 2e05 SRS @0x0005, $AC0.M +09ad 2281 LRS $AX0.H, @0xff81 +09ae 8600 TSTAXH $AX0.H +09af 0294 09b8 JNE 0x09b8 +09b1 8100 CLR $AC0.M +09b2 005f LOOP $AC1.M +09b3 1b7e SRRI @$R03, $AC0.M +09b4 7400 INCM $AC0.M +09b5 2e01 SRS @0x0001, $AC0.M +09b6 029f 09f2 JMP 0x09f2 + + +// called from 9af above. +09b8 2688 LRS $AC0.M, @0xff88 +09b9 2489 LRS $AC0.L, @0xff89 +09ba 2e34 SRS @0x0034, $AC0.M +09bb 2c35 SRS @0x0035, $AC0.L +09bc 02bf 09f9 CALL 0x09f9 +09be 00ff 0360 SR @0x0360, $AC1.M +09c0 2638 LRS $AC0.M, @0x0038 +09c1 2439 LRS $AC0.L, @0x0039 +09c2 0f05 LRIS $AC1.M, #0x05 +09c3 02bf 05ad CALL 0x05ad +09c5 00df 0360 LR $AC1.M, @0x0360 +09c7 8100 CLR $AC0.M +09c8 263a LRS $AC0.M, @0x003a +09c9 b100 TST $AC0.M +09ca 0294 09d9 JNE 0x09d9 +09cc 263b LRS $AC0.M, @0x003b +09cd 5c00 SUB $AC0.M, $AC1.M +09ce 0290 09d9 JX0 0x09d9 +09d0 223b LRS $AX0.H, @0x003b +09d1 02bf 0a0a CALL 0x0a0a // weird little loop. count = ax0.h +09d3 5500 SUBR $AC1.M, $AX0.H +09d4 0a01 LRIS $AX0.H, #0x01 +09d5 00fa 0405 SR @0x0405, $AX0.H +09d7 029f 09ab JMP 0x09ab + + + +09d9 1f5f MRR $AX0.H, $AC1.M +09da 02bf 0a0a CALL 0x0a0a // weird little loop. count = ax0.h +09dc 00fa 0362 SR @0x0362, $AX0.H +09de 8100 CLR $AC0.M +09df 263a LRS $AC0.M, @0x003a +09e0 243b LRS $AC0.L, @0x003b +09e1 1570 LSR $ACC1, #0x30 +09e2 0a01 LRIS $AX0.H, #0x01 +09e3 0081 0405 LRI $R01, #0x0405 +09e5 5c00 SUB $AC0.M, $AC1.M +09e6 b100 TST $AC0.M +09e7 0275 IF_Q +09e8 1a3a SRR @$R01, $AX0.H +09e9 2e3a SRS @0x003a, $AC0.M +09ea 2c3b SRS @0x003b, $AC0.L +09eb 2638 LRS $AC0.M, @0x0038 +09ec 2439 LRS $AC0.L, @0x0039 +09ed 00d8 0362 LR $AX0.L, @0x0362 +09ef 7000 ADDAXL $AC0.M, $AX0.L +09f0 2c39 SRS @0x0039, $AC0.L +09f1 2e38 SRS @0x0038, $AC0.M +09f2 0092 00ff LRI $CR, #0x00ff +09f4 029f 02d0 JMP 0x02d0 + + +// Nobody every calls 9f6... probably 3 lines of dead code. +09f6 8100 CLR $AC0.M +09f7 2e34 SRS @0x0034, $AC0.M +09f8 2e35 SRS @0x0035, $AC0.M + + +//.. entry point here from 9a4, 9bc. Looks kind of like a 32-bit butterfly computation? +09f9 2334 LRS $AX1.H, @0x0034 +09fa 2135 LRS $AX1.L, @0x0035 +09fb 268a LRS $AC0.M, @0xff8a +09fc 248b LRS $AC0.L, @0xff8b +09fd 5a00 SUBAX $AC0.M, $AX1.L +09fe 2e3a SRS @0x003a, $AC0.M +09ff 2c3b SRS @0x003b, $AC0.L +0a00 2634 LRS $AC0.M, @0x0034 +0a01 2435 LRS $AC0.L, @0x0035 +0a02 238c LRS $AX1.H, @0xff8c +0a03 218d LRS $AX1.L, @0xff8d +0a04 4a00 ADDAX $AC0.M, $AX1.L +0a05 2e38 SRS @0x0038, $AC0.M +0a06 2c39 SRS @0x0039, $AC0.L +0a07 8100 CLR $AC0.M +0a08 2e05 SRS @0x0005, $AC0.M +0a09 02df RET + + +// weird little loop. out[i] = in[i] << 8; ? +0a0a 0080 ffd3 LRI $R00, #0xffd3 +0a0c 0084 0000 LRI $R04, #0x0000 +0a0e 007a 0a12 BLOOP $AX0.H, 0x0a12 +0a10 199e LRRN $AC0.M, @$R00 +0a11 1488 ASL $ACC0, #0x08 +0a12 1b7e SRRI @$R03, $AC0.M +0a13 02df RET + + +0a14 0092 0004 LRI $CR, #0x0004 +0a16 2002 LRS $AX0.L, @0x0002 +0a17 8100 CLR $AC0.M +0a18 8900 CLR $AC1.M +0a19 2430 LRS $AC0.L, @0x0030 +0a1a 8d00 SET15 +0a1b 0950 LRIS $AX1.L, #0x50 +0a1c a000 MULX $AX0.L, $AX1.L +0a1d a400 MULXAC $AX0.L, $AX1.L, $AC0.M +0a1e 1404 LSL $ACC0, #0x04 +0a1f 8c00 CLR15 +0a20 1ffe MRR $AC1.M, $AC0.M +0a21 0083 0580 LRI $R03, #0x0580 +0a23 2201 LRS $AX0.H, @0x0001 +0a24 8600 TSTAXH $AX0.H +0a25 0294 0a36 JNE 0x0a36 +0a27 2204 LRS $AX0.H, @0x0004 +0a28 8600 TSTAXH $AX0.H +0a29 02b4 0a7f CALLNE 0x0a7f +0a2b 8100 CLR $AC0.M +0a2c 2605 LRS $AC0.M, @0x0005 +0a2d b100 TST $AC0.M +0a2e 0295 0a43 JEQ 0x0a43 +0a30 8100 CLR $AC0.M // 0x0a5c jumps here. +0a31 2e05 SRS @0x0005, $AC0.M +0a32 2281 LRS $AX0.H, @0xff81 +0a33 8600 TSTAXH $AX0.H +0a34 0294 0a3d JNE 0x0a3d +0a36 8100 CLR $AC0.M +0a37 005f LOOP $AC1.M +0a38 1b7e SRRI @$R03, $AC0.M +0a39 7400 INCM $AC0.M +0a3a 2e01 SRS @0x0001, $AC0.M +0a3b 029f 0a78 JMP 0x0a78 + + +// VERY similar to 9b8, just a different call. +0a3d 2688 LRS $AC0.M, @0xff88 +0a3e 2489 LRS $AC0.L, @0xff89 +0a3f 2e34 SRS @0x0034, $AC0.M +0a40 2c35 SRS @0x0035, $AC0.L +0a41 02bf 0a7f CALL 0x0a7f +0a43 00ff 0360 SR @0x0360, $AC1.M +0a45 2638 LRS $AC0.M, @0x0038 +0a46 2439 LRS $AC0.L, @0x0039 +0a47 0f06 LRIS $AC1.M, #0x06 +0a48 02bf 05ad CALL 0x05ad +0a4a 00df 0360 LR $AC1.M, @0x0360 +0a4c 8100 CLR $AC0.M +0a4d 263a LRS $AC0.M, @0x003a +0a4e b100 TST $AC0.M +0a4f 0294 0a5e JNE 0x0a5e +0a51 263b LRS $AC0.M, @0x003b +0a52 5c00 SUB $AC0.M, $AC1.M +0a53 0290 0a5e JX0 0x0a5e +0a55 223b LRS $AX0.H, @0x003b +0a56 02bf 0a91 CALL 0x0a91 +0a58 5500 SUBR $AC1.M, $AX0.H +0a59 0a01 LRIS $AX0.H, #0x01 +0a5a 00fa 0405 SR @0x0405, $AX0.H +0a5c 029f 0a30 JMP 0x0a30 + + +// Identical to 9d9 except an extra ADDAXL. +0a5e 1f5f MRR $AX0.H, $AC1.M +0a5f 02bf 0a91 CALL 0x0a91 +0a61 00fa 0362 SR @0x0362, $AX0.H +0a63 8100 CLR $AC0.M +0a64 263a LRS $AC0.M, @0x003a +0a65 243b LRS $AC0.L, @0x003b +0a66 1570 LSR $ACC1, #0x30 +0a67 0a01 LRIS $AX0.H, #0x01 +0a68 0081 0405 LRI $R01, #0x0405 +0a6a 5c00 SUB $AC0.M, $AC1.M +0a6b b100 TST $AC0.M +0a6c 0275 IF_Q +0a6d 1a3a SRR @$R01, $AX0.H +0a6e 2e3a SRS @0x003a, $AC0.M +0a6f 2c3b SRS @0x003b, $AC0.L +0a70 2638 LRS $AC0.M, @0x0038 +0a71 2439 LRS $AC0.L, @0x0039 +0a72 00d8 0362 LR $AX0.L, @0x0362 +0a74 7000 ADDAXL $AC0.M, $AX0.L +0a75 7000 ADDAXL $AC0.M, $AX0.L +0a76 2c39 SRS @0x0039, $AC0.L +0a77 2e38 SRS @0x0038, $AC0.M +0a78 0092 00ff LRI $CR, #0x00ff +0a7a 029f 02d0 JMP 0x02d0 + + + +0a7c 8100 CLR $AC0.M +0a7d 2e34 SRS @0x0034, $AC0.M +0a7e 2e35 SRS @0x0035, $AC0.M +0a7f 2334 LRS $AX1.H, @0x0034 +0a80 2135 LRS $AX1.L, @0x0035 +0a81 268a LRS $AC0.M, @0xff8a +0a82 248b LRS $AC0.L, @0xff8b +0a83 5a00 SUBAX $AC0.M, $AX1.L +0a84 2e3a SRS @0x003a, $AC0.M +0a85 2c3b SRS @0x003b, $AC0.L +0a86 2634 LRS $AC0.M, @0x0034 +0a87 2435 LRS $AC0.L, @0x0035 +0a88 1401 LSL $ACC0, #0x01 +0a89 238c LRS $AX1.H, @0xff8c +0a8a 218d LRS $AX1.L, @0xff8d +0a8b 4a00 ADDAX $AC0.M, $AX1.L +0a8c 2e38 SRS @0x0038, $AC0.M +0a8d 2c39 SRS @0x0039, $AC0.L +0a8e 8100 CLR $AC0.M +0a8f 2e05 SRS @0x0005, $AC0.M +0a90 02df RET + + + + +0a91 0080 ffd3 LRI $R00, #0xffd3 +0a93 0084 0000 LRI $R04, #0x0000 +0a95 007a 0a98 BLOOP $AX0.H, 0x0a98 +0a97 199e LRRN $AC0.M, @$R00 +0a98 1b7e SRRI @$R03, $AC0.M +0a99 02df RET + + + +0a9a 8900 CLR $AC1.M +0a9b 0f50 LRIS $AC1.M, #0x50 +0a9c 0083 0520 LRI $R03, #0x0520 +0a9e 02bf 0ab3 CALL 0x0ab3 +0aa0 029f 02d8 JMP 0x02d8 + + + +0aa2 00d8 0402 LR $AX0.L, @0x0402 +0aa4 8100 CLR $AC0.M +0aa5 8900 CLR $AC1.M +0aa6 00dc 0430 LR $AC0.L, @0x0430 +0aa8 0a50 LRIS $AX0.H, #0x50 +0aa9 9000 MUL $AX0.L, $AX0.H +0aaa 9400 MULAC $AX0.L, $AX0.H, $AC0.M +0aab 1404 LSL $ACC0, #0x04 +0aac 1ffe MRR $AC1.M, $AC0.M +0aad 0083 0580 LRI $R03, #0x0580 +0aaf 02bf 0ab3 CALL 0x0ab3 +0ab1 029f 02d0 JMP 0x02d0 + + + +0ab3 0092 0004 LRI $CR, #0x0004 +0ab5 8100 CLR $AC0.M +0ab6 263a LRS $AC0.M, @0x003a +0ab7 243b LRS $AC0.L, @0x003b +0ab8 1f1f MRR $AX0.L, $AC1.M +0ab9 0a00 LRIS $AX0.H, #0x00 +0aba 5800 SUBAX $AC0.M, $AX0.L +0abb 0292 0ad1 JX2 0x0ad1 +0abd 8900 CLR $AC1.M +0abe 00c0 043b LR $R00, @0x043b +0ac0 02bf 0af6 CALL 0x0af6 +0ac2 8100 CLR $AC0.M +0ac3 1fd8 MRR $AC0.M, $AX0.L +0ac4 223b LRS $AX0.H, @0x003b +0ac5 5400 SUBR $AC0.M, $AX0.H +0ac6 0007 DAR $R03 +0ac7 1979 LRRI $AX1.L, @$R03 +0ac8 005e LOOP $AC0.M +0ac9 1b79 SRRI @$R03, $AX1.L +0aca 0f01 LRIS $AC1.M, #0x01 +0acb 2f01 SRS @0x0001, $AC1.M +0acc 8900 CLR $AC1.M +0acd 2f3b SRS @0x003b, $AC1.M +0ace 0092 00ff LRI $CR, #0x00ff +0ad0 02df RET + + + +0ad1 2e3a SRS @0x003a, $AC0.M +0ad2 2c3b SRS @0x003b, $AC0.L +0ad3 8100 CLR $AC0.M +0ad4 8900 CLR $AC1.M +0ad5 268a LRS $AC0.M, @0xff8a +0ad6 2734 LRS $AC1.M, @0x0034 +0ad7 5c00 SUB $AC0.M, $AC1.M +0ad8 2e36 SRS @0x0036, $AC0.M +0ad9 5000 SUBR $AC0.M, $AX0.L +0ada 0290 0af0 JX0 0x0af0 +0adc 00c0 0436 LR $R00, @0x0436 +0ade 02bf 0af6 CALL 0x0af6 +0ae0 8100 CLR $AC0.M +0ae1 1fd8 MRR $AC0.M, $AX0.L +0ae2 2236 LRS $AX0.H, @0x0036 +0ae3 5400 SUBR $AC0.M, $AX0.H +0ae4 1c1e MRR $R00, $AC0.M +0ae5 8100 CLR $AC0.M +0ae6 2e34 SRS @0x0034, $AC0.M +0ae7 2688 LRS $AC0.M, @0xff88 +0ae8 2489 LRS $AC0.L, @0xff89 +0ae9 2e8c SRS @0xff8c, $AC0.M +0aea 2c8d SRS @0xff8d, $AC0.L +0aeb 02bf 0af6 CALL 0x0af6 +0aed 0092 00ff LRI $CR, #0x00ff +0aef 02df RET + + + +0af0 1c18 MRR $R00, $AX0.L +0af1 02bf 0af6 CALL 0x0af6 +0af3 0092 00ff LRI $CR, #0x00ff +0af5 02df RET +0af6 8100 CLR $AC0.M +0af7 1fc0 MRR $AC0.M, $R00 +0af8 b100 TST $AC0.M +0af9 02d5 RETEQ +0afa 8900 CLR $AC1.M +0afb 2734 LRS $AC1.M, @0x0034 +0afc 0340 0001 ANDI $ACC1, #0x0001 +0afe 0b00 LRIS $AX1.H, #0x00 +0aff 1f3f MRR $AX1.L, $AC1.M +0b00 268c LRS $AC0.M, @0xff8c +0b01 248d LRS $AC0.L, @0xff8d +0b02 8900 CLR $AC1.M +0b03 2534 LRS $AC1.L, @0x0034 +0b04 1501 LSL $ACC1, #0x01 +0b05 4c00 ADD $AC0.M, $AC1.M +0b06 5a00 SUBAX $AC0.M, $AX1.L +0b07 5a00 SUBAX $AC0.M, $AX1.L +0b08 1c20 MRR $R01, $R00 +0b09 1fe0 MRR $AC1.M, $R00 +0b0a 0502 ADDIS $ACC1, #0x02 +0b0b 1c1f MRR $R00, $AC1.M +0b0c 009f 0b00 LRI $AC1.M, #0x0b00 +0b0e 0092 00ff LRI $CR, #0x00ff +0b10 02bf 0525 CALL 0x0525 // RAMtoDMEM(DMEM=$AC1.M, AC0=MEMADDR, R00=Len) +0b12 0092 0004 LRI $CR, #0x0004 +0b14 2734 LRS $AC1.M, @0x0034 +0b15 1f61 MRR $AX1.H, $R01 +0b16 4700 ADDR $AC1.M, $AX1.H +0b17 2f34 SRS @0x0034, $AC1.M +0b18 0080 0b00 LRI $R00, #0x0b00 +0b1a 8900 CLR $AC1.M +0b1b 1ff9 MRR $AC1.M, $AX1.L +0b1c b900 TST $AC1.M +0b1d 0274 IF_E +0b1e 0008 IAR $R00 +0b1f 8900 CLR $AC1.M +0b20 1fe1 MRR $AC1.M, $R01 +0b21 191e LRRI $AC0.M, @$R00 +0b22 0701 CMPIS $ACC1, #0x01 +0b23 0293 0b2c JX3 0x0b2c +0b25 191a LRRI $AX0.H, @$R00 +0b26 05fe ADDIS $ACC1, #0xfe +0b27 005f LOOP $AC1.M +0b28 64a0 MOVR.LS $AC0.M, $AX0.H : $AX0.H, $AC0.M +0b29 1b7e SRRI @$R03, $AC0.M +0b2a 1b7a SRRI @$R03, $AX0.H +0b2b 02df RET + + + +0b2c 1b7e SRRI @$R03, $AC0.M +0b2d 02df RET + + + +0b2e 8a00 M2 +0b2f 0083 03e8 LRI $R03, #0x03e8 +0b31 191e LRRI $AC0.M, @$R00 +0b32 191a LRRI $AX0.H, @$R00 +0b33 1006 LOOPI #0x06 +0b34 64a0 MOVR.LS $AC0.M, $AX0.H : $AX0.H, $AC0.M +0b35 1b7e SRRI @$R03, $AC0.M +0b36 1b7a SRRI @$R03, $AX0.H +0b37 0080 03e8 LRI $R00, #0x03e8 +0b39 0088 0007 LRI $R08, #0x0007 +0b3b 1150 0b48 BLOOPI #0x50, 0x0b48 +0b3d 1c61 MRR $R03, $R01 +0b3e 84c3 CLRP.LD : $AX0.L, $AX1.L, @$R03 +0b3f f2c3 MADD.LD $AX0.L, $AX0.H : $AX0.L, $AX1.L, @$R03 +0b40 f2c3 MADD.LD $AX0.L, $AX0.H : $AX0.L, $AX1.L, @$R03 +0b41 f2c3 MADD.LD $AX0.L, $AX0.H : $AX0.L, $AX1.L, @$R03 +0b42 f2c3 MADD.LD $AX0.L, $AX0.H : $AX0.L, $AX1.L, @$R03 +0b43 f2c3 MADD.LD $AX0.L, $AX0.H : $AX0.L, $AX1.L, @$R03 +0b44 f2c3 MADD.LD $AX0.L, $AX0.H : $AX0.L, $AX1.L, @$R03 +0b45 f2c3 MADD.LD $AX0.L, $AX0.H : $AX0.L, $AX1.L, @$R03 +0b46 f200 MADD $AX0.L, $AX0.H +0b47 fe00 MOVPZ $AC0.M +0b48 1b3e SRRI @$R01, $AC0.M +0b49 0088 ffff LRI $R08, #0xffff +0b4b 8b00 M0 +0b4c 02df RET + + + +0b4d 8a00 M2 +0b4e 05fe ADDIS $ACC1, #0xfe +0b4f 0083 03e8 LRI $R03, #0x03e8 +0b51 191e LRRI $AC0.M, @$R00 +0b52 191a LRRI $AX0.H, @$R00 +0b53 005f LOOP $AC1.M +0b54 64a0 MOVR.LS $AC0.M, $AX0.H : $AX0.H, $AC0.M +0b55 1b7e SRRI @$R03, $AC0.M +0b56 1b7a SRRI @$R03, $AX0.H +0b57 0080 03e8 LRI $R00, #0x03e8 +0b59 0501 ADDIS $ACC1, #0x01 +0b5a 1d1f MRR $R08, $AC1.M +0b5b 1150 0b63 BLOOPI #0x50, 0x0b63 +0b5d 1c61 MRR $R03, $R01 +0b5e 84c3 CLRP.LD : $AX0.L, $AX1.L, @$R03 +0b5f 005f LOOP $AC1.M +0b60 f2c3 MADD.LD $AX0.L, $AX0.H : $AX0.L, $AX1.L, @$R03 +0b61 f200 MADD $AX0.L, $AX0.H +0b62 fe00 MOVPZ $AC0.M +0b63 1b3e SRRI @$R01, $AC0.M +0b64 0088 ffff LRI $R08, #0xffff +0b66 8b00 M0 +0b67 02df RET + + + +0b68 0083 03e8 LRI $R03, #0x03e8 +0b6a 191e LRRI $AC0.M, @$R00 +0b6b 191a LRRI $AX0.H, @$R00 +0b6c 64a0 MOVR.LS $AC0.M, $AX0.H : $AX0.H, $AC0.M +0b6d 64a0 MOVR.LS $AC0.M, $AX0.H : $AX0.H, $AC0.M +0b6e 1b7e SRRI @$R03, $AC0.M +0b6f 1b7a SRRI @$R03, $AX0.H +0b70 0080 03e8 LRI $R00, #0x03e8 +0b72 0088 0003 LRI $R08, #0x0003 +0b74 0085 0000 LRI $R05, #0x0000 +0b76 0087 0000 LRI $R07, #0x0000 +0b78 1fc2 MRR $AC0.M, $R02 +0b79 195b LRRI $AX1.H, @$R02 +0b7a 1959 LRRI $AX1.L, @$R02 +0b7b 195f LRRI $AC1.M, @$R02 +0b7c 195a LRRI $AX0.H, @$R02 +0b7d 1c5e MRR $R02, $AC0.M +0b7e 1fda MRR $AC0.M, $AX0.H +0b7f 1c61 MRR $R03, $R01 +0b80 8a00 M2 +0b81 8f00 S16 +0b82 191a LRRI $AX0.H, @$R00 +0b83 b850 MULX.L $AX0.H, $AX1.H : $AX0.H, @$R00 +0b84 e250 MADDX.L $AX0.H, $AX1.L : $AX0.H, @$R00 +0b85 ea50 MADDC.L $AC1.M, $AX1.L : $AX0.H, @$R00 +0b86 e8e8 MADDC.LDXM $AC0.M, $AX1.L : $AX0.L, $AX0.H, @$R01 +0b87 b650 MULXMV.L $AX0.H, $AX1.L, $AC0.M : $AX0.H, @$R00 +0b88 1127 0b93 BLOOPI #0x27, 0x0b93 +0b8a e3a8 MADDX.LSM $AX0.H, $AX1.H : $AX0.H, $AC0.M +0b8b 197e LRRI $AC0.M, @$R03 +0b8c e850 MADDC.L $AC0.M, $AX1.L : $AX0.H, @$R00 +0b8d eaf8 MADDC.LDXM $AC1.M, $AX1.L : $AX1.L, $AX1.H, @$R01 +0b8e bf50 MULXMV.L $AX0.H, $AX1.H, $AC1.M : $AX0.H, @$R00 +0b8f e2a9 MADDX.LSM $AX0.H, $AX1.L : $AX0.H, $AC1.M +0b90 197f LRRI $AC1.M, @$R03 +0b91 ea50 MADDC.L $AC1.M, $AX1.L : $AX0.H, @$R00 +0b92 e8e8 MADDC.LDXM $AC0.M, $AX1.L : $AX0.L, $AX0.H, @$R01 +0b93 b650 MULXMV.L $AX0.H, $AX1.L, $AC0.M : $AX0.H, @$R00 +0b94 e3a8 MADDX.LSM $AX0.H, $AX1.H : $AX0.H, $AC0.M +0b95 197e LRRI $AC0.M, @$R03 +0b96 e850 MADDC.L $AC0.M, $AX1.L : $AX0.H, @$R00 +0b97 eaf8 MADDC.LDXM $AC1.M, $AX1.L : $AX1.L, $AX1.H, @$R01 +0b98 bf00 MULXMV $AX0.H, $AX1.H, $AC1.M +0b99 1bff SRRN @$R03, $AC1.M +0b9a 197f LRRI $AC1.M, @$R03 +0b9b 8e00 S40 +0b9c 8b00 M0 +0b9d 0088 ffff LRI $R08, #0xffff +0b9f 1b5b SRRI @$R02, $AX1.H +0ba0 1b59 SRRI @$R02, $AX1.L +0ba1 1b5f SRRI @$R02, $AC1.M +0ba2 1b5e SRRI @$R02, $AC0.M +0ba3 02df RET + + + +0ba4 0083 03e8 LRI $R03, #0x03e8 +0ba6 191e LRRI $AC0.M, @$R00 +0ba7 191a LRRI $AX0.H, @$R00 +0ba8 64a0 MOVR.LS $AC0.M, $AX0.H : $AX0.H, $AC0.M +0ba9 64a0 MOVR.LS $AC0.M, $AX0.H : $AX0.H, $AC0.M +0baa 1b7e SRRI @$R03, $AC0.M +0bab 1b7a SRRI @$R03, $AX0.H +0bac 0080 03e8 LRI $R00, #0x03e8 +0bae 0088 0003 LRI $R08, #0x0003 +0bb0 0085 0000 LRI $R05, #0x0000 +0bb2 0087 0000 LRI $R07, #0x0000 +0bb4 1fc2 MRR $AC0.M, $R02 +0bb5 195b LRRI $AX1.H, @$R02 +0bb6 1959 LRRI $AX1.L, @$R02 +0bb7 195f LRRI $AC1.M, @$R02 +0bb8 195a LRRI $AX0.H, @$R02 +0bb9 1c5e MRR $R02, $AC0.M +0bba 1fda MRR $AC0.M, $AX0.H +0bbb 1c61 MRR $R03, $R01 +0bbc 8a00 M2 +0bbd 8f00 S16 +0bbe 191a LRRI $AX0.H, @$R00 +0bbf b800 MULX $AX0.H, $AX1.H +0bc0 e350 MADDX.L $AX0.H, $AX1.H : $AX0.H, @$R00 +0bc1 e250 MADDX.L $AX0.H, $AX1.L : $AX0.H, @$R00 +0bc2 ea00 MADDC $AC1.M, $AX1.L +0bc3 ea50 MADDC.L $AC1.M, $AX1.L : $AX0.H, @$R00 +0bc4 e877 MADDC.LN $AC0.M, $AX1.L : $AC0.M, @$R03 +0bc5 ece8 MSUBC.LDXM $AC0.M, $AX1.L : $AX0.L, $AX0.H, @$R01 +0bc6 b200 MULXMVZ $AX0.H, $AX1.L, $AC0.M +0bc7 1127 0bd8 BLOOPI #0x27, 0x0bd8 +0bc9 e250 MADDX.L $AX0.H, $AX1.L : $AX0.H, @$R00 +0bca e3a8 MADDX.LSM $AX0.H, $AX1.H : $AX0.H, $AC0.M +0bcb 197e LRRI $AC0.M, @$R03 +0bcc e800 MADDC $AC0.M, $AX1.L +0bcd e850 MADDC.L $AC0.M, $AX1.L : $AX0.H, @$R00 +0bce ea7f MADDC.LN $AC1.M, $AX1.L : $AC1.M, @$R03 +0bcf eef8 MSUBC.LDXM $AC1.M, $AX1.L : $AX1.L, $AX1.H, @$R01 +0bd0 bb00 MULXMVZ $AX0.H, $AX1.H, $AC1.M +0bd1 e350 MADDX.L $AX0.H, $AX1.H : $AX0.H, @$R00 +0bd2 e2a9 MADDX.LSM $AX0.H, $AX1.L : $AX0.H, $AC1.M +0bd3 197f LRRI $AC1.M, @$R03 +0bd4 ea00 MADDC $AC1.M, $AX1.L +0bd5 ea50 MADDC.L $AC1.M, $AX1.L : $AX0.H, @$R00 +0bd6 e877 MADDC.LN $AC0.M, $AX1.L : $AC0.M, @$R03 +0bd7 ece8 MSUBC.LDXM $AC0.M, $AX1.L : $AX0.L, $AX0.H, @$R01 +0bd8 b200 MULXMVZ $AX0.H, $AX1.L, $AC0.M +0bd9 e250 MADDX.L $AX0.H, $AX1.L : $AX0.H, @$R00 +0bda e3a8 MADDX.LSM $AX0.H, $AX1.H : $AX0.H, $AC0.M +0bdb 197e LRRI $AC0.M, @$R03 +0bdc e800 MADDC $AC0.M, $AX1.L +0bdd e850 MADDC.L $AC0.M, $AX1.L : $AX0.H, @$R00 +0bde ea7f MADDC.LN $AC1.M, $AX1.L : $AC1.M, @$R03 +0bdf eef8 MSUBC.LDXM $AC1.M, $AX1.L : $AX1.L, $AX1.H, @$R01 +0be0 bb00 MULXMVZ $AX0.H, $AX1.H, $AC1.M +0be1 1bff SRRN @$R03, $AC1.M +0be2 197f LRRI $AC1.M, @$R03 +0be3 8e00 S40 +0be4 8b00 M0 +0be5 0088 ffff LRI $R08, #0xffff +0be7 1b5b SRRI @$R02, $AX1.H +0be8 1b59 SRRI @$R02, $AX1.L +0be9 1b5f SRRI @$R02, $AC1.M +0bea 1b5e SRRI @$R02, $AC0.M +0beb 02df RET + + + +0bec 0eff LRIS $AC0.M, #0xff +0bed 00fe 03f2 SR @0x03f2, $AC0.M +0bef 8100 CLR $AC0.M +0bf0 00fe 03f0 SR @0x03f0, $AC0.M +0bf2 00fe 03f6 SR @0x03f6, $AC0.M +0bf4 009e 0100 LRI $AC0.M, #0x0100 +0bf6 00fe 03f7 SR @0x03f7, $AC0.M +0bf8 00da 03f7 LR $AX0.H, @0x03f7 +0bfa 009e 8000 LRI $AC0.M, #0x8000 +0bfc 5400 SUBR $AC0.M, $AX0.H +0bfd 00fe 03f5 SR @0x03f5, $AC0.M +0bff 0e30 LRIS $AC0.M, #0x30 +0c00 00fe 03f3 SR @0x03f3, $AC0.M +0c02 0e10 LRIS $AC0.M, #0x10 +0c03 00fe 03f4 SR @0x03f4, $AC0.M +0c05 009e 0096 LRI $AC0.M, #0x0096 +0c07 00fe 03f1 SR @0x03f1, $AC0.M +0c09 02df RET + + + +0c0a 0080 0a00 LRI $R00, #0x0a00 +0c0c 8100 CLR $AC0.M +0c0d 00de 03f0 LR $AC0.M, @0x03f0 +0c0f 8900 CLR $AC1.M +0c10 b100 TST $AC0.M +0c11 0275 IF_Q +0c12 0550 ADDIS $ACC1, #0x50 +0c13 00ff 03f0 SR @0x03f0, $AC1.M +0c15 0200 0a60 ADDI $ACC0, #0x0a60 +0c17 1c7e MRR $R03, $AC0.M +0c18 0f4e LRIS $AC1.M, #0x4e +0c19 02bf 00da CALL 0x00da // CopyMemory(LEN=$AC1.M, *R00=SRC, *R03=DEST) +0c1b 02df RET + + + +0c1c 00de 03f1 LR $AC0.M, @0x03f1 +0c1e 0200 0a60 ADDI $ACC0, #0x0a60 +0c20 1c7e MRR $R03, $AC0.M +0c21 8100 CLR $AC0.M +0c22 8900 CLR $AC1.M +0c23 009f 00a0 LRI $AC1.M, #0x00a0 +0c25 00de 03f1 LR $AC0.M, @0x03f1 +0c27 5d00 SUB $AC1.M, $AC0.M +0c28 0e50 LRIS $AC0.M, #0x50 +0c29 0750 CMPIS $ACC1, #0x50 +0c2a 0270 IF_0 +0c2b 5d00 SUB $AC1.M, $AC0.M +0c2c 00da 03f2 LR $AX0.H, @0x03f2 +0c2e 8600 TSTAXH $AX0.H +0c2f 0290 0c4d JX0 0x0c4d +0c31 00de 03f3 LR $AC0.M, @0x03f3 +0c33 5c00 SUB $AC0.M, $AC1.M +0c34 0293 0c38 JX3 0x0c38 +0c36 029f 0c52 JMP 0x0c52 +0c38 00db 03f7 LR $AX1.H, @0x03f7 +0c3a 009e 8000 LRI $AC0.M, #0x8000 +0c3c 4600 ADDR $AC0.M, $AX1.H +0c3d 029f 0c44 JMP 0x0c44 +0c3f 00db 03f7 LR $AX1.H, @0x03f7 +0c41 009e 8000 LRI $AC0.M, #0x8000 +0c43 5600 SUBR $AC0.M, $AX1.H +0c44 00fe 03f5 SR @0x03f5, $AC0.M +0c46 1fda MRR $AC0.M, $AX0.H +0c47 7c00 NEG $AC0.M +0c48 1f5e MRR $AX0.H, $AC0.M +0c49 00fe 03f2 SR @0x03f2, $AC0.M +0c4b 029f 0c52 JMP 0x0c52 +0c4d 00de 03f4 LR $AC0.M, @0x03f4 +0c4f 5d00 SUB $AC1.M, $AC0.M +0c50 0293 0c3f JX3 0x0c3f +0c52 8900 CLR $AC1.M +0c53 00dd 03f5 LR $AC1.L, @0x03f5 +0c55 1501 LSL $ACC1, #0x01 +0c56 8100 CLR $AC0.M +0c57 00dc 03f6 LR $AC0.L, @0x03f6 +0c59 008b 009f LRI $R11, #0x009f +0c5b 0080 0a00 LRI $R00, #0x0a00 +0c5d 0900 LRIS $AX1.L, #0x00 +0c5e 1150 0c65 BLOOPI #0x50, 0x0c65 +0c60 1878 LRR $AX0.L, @$R03 +0c61 4c00 ADD $AC0.M, $AC1.M +0c62 1cfe MRR $R07, $AC0.M +0c63 001f CW 0x001f ; *** UNKNOWN OPCODE *** +0c64 1fd9 MRR $AC0.M, $AX1.L +0c65 1b18 SRRI @$R00, $AX0.L +0c66 009f 0a60 LRI $AC1.M, #0x0a60 +0c68 1fc3 MRR $AC0.M, $R03 +0c69 5c00 SUB $AC0.M, $AC1.M +0c6a 00fe 03f1 SR @0x03f1, $AC0.M +0c6c 00fc 03f6 SR @0x03f6, $AC0.L +0c6e 008b ffff LRI $R11, #0xffff +0c70 02df RET + + + +0c71 0f50 LRIS $AC1.M, #0x50 +0c72 0080 0a00 LRI $R00, #0x0a00 +0c74 0083 0d60 LRI $R03, #0x0d60 +0c76 0098 3fff LRI $AX0.L, #0x3fff +0c78 02bf 00eb CALL 0x00eb // one of the multiply loops +0c7a 0f50 LRIS $AC1.M, #0x50 +0c7b 0080 0a00 LRI $R00, #0x0a00 +0c7d 0083 0d00 LRI $R03, #0x0d00 +0c7f 0098 3fff LRI $AX0.L, #0x3fff +0c81 02bf 00eb CALL 0x00eb // one of the multiply loops +0c83 02df RET + + + +0c84 8a00 M2 +0c85 8f00 S16 +0c86 8100 CLR $AC0.M +0c87 00de 0404 LR $AC0.M, @0x0404 +0c89 b100 TST $AC0.M +0c8a 0295 0c91 JEQ 0x0c91 +0c8c 8100 CLR $AC0.M +0c8d 00fe 0478 SR @0x0478, $AC0.M +0c8f 00fe 0479 SR @0x0479, $AC0.M +0c91 00df 0479 LR $AC1.M, @0x0479 +0c93 00db 0478 LR $AX1.H, @0x0478 +0c95 0900 LRIS $AX1.L, #0x00 +0c96 0084 0000 LRI $R04, #0x0000 +0c98 1150 0ca1 BLOOPI #0x50, 0x0ca1 +0c9a 199e LRRN $AC0.M, @$R00 +0c9b 5c7c SUB.LN $AC0.M, $AC1.M : $AC1.M, @$R00 +0c9c c000 MULC $AX0.H, $AC0.M +0c9d 6e00 MOVP $AC0.M +0c9e 1488 ASL $ACC0, #0x08 +0c9f 4a00 ADDAX $AC0.M, $AX1.L +0ca0 1b1e SRRI @$R00, $AC0.M +0ca1 1f7e MRR $AX1.H, $AC0.M +0ca2 00fb 0478 SR @0x0478, $AX1.H +0ca4 00ff 0479 SR @0x0479, $AC1.M +0ca6 8b00 M0 +0ca7 8e00 S40 +0ca8 02df RET + + +0ca9 b900 TST $AC1.M +0caa 0294 0caf JNE 0x0caf +0cac 6800 MOVAX $AC0.M, $AX0.L +0cad b100 TST $AC0.M +0cae 02d5 RETEQ +//... +0caf 1c23 MRR $R01, $R03 +0cb0 197e LRRI $AC0.M, @$R03 +0cb1 191b LRRI $AX1.H, @$R00 +0cb2 d858 MULC.L $AX1.H, $AC1.M : $AX1.H, @$R00 +0cb3 1120 0cb9 BLOOPI #0x20, 0x0cb9 +0cb5 dcd3 MULCAC.LD $AX1.H, $AC1.M, $AC0.M : $AX0.L, $AX1.H, @$R03 +0cb6 6231 MOVR.S $AC0.M, $AX1.L : @$R01, $AC0.M +0cb7 dcd3 MULCAC.LD $AX1.H, $AC1.M, $AC0.M : $AX0.L, $AX1.H, @$R03 +0cb8 6231 MOVR.S $AC0.M, $AX1.L : @$R01, $AC0.M +0cb9 4900 ADDAX $AC1.M, $AX0.L +0cba 1108 0cbf BLOOPI #0x08, 0x0cbf +0cbc dcd3 MULCAC.LD $AX1.H, $AC1.M, $AC0.M : $AX0.L, $AX1.H, @$R03 +0cbd 6231 MOVR.S $AC0.M, $AX1.L : @$R01, $AC0.M +0cbe dcd3 MULCAC.LD $AX1.H, $AC1.M, $AC0.M : $AX0.L, $AX1.H, @$R03 +0cbf 6231 MOVR.S $AC0.M, $AX1.L : @$R01, $AC0.M +0cc0 02df RET + + +// Yet another multiply loop. bufsize = 0x28 +0cc1 8f00 S16 +0cc2 8d00 SET15 +0cc3 1c03 MRR $R00, $R03 +0cc4 00d9 038e LR $AX1.L, @0x038e +0cc6 0b04 LRIS $AX1.H, #0x04 +0cc7 197a LRRI $AX0.H, @$R03 +0cc8 b053 MULX.L $AX0.H, $AX1.L : $AX0.H, @$R03 +0cc9 b600 MULXMV $AX0.H, $AX1.L, $AC0.M +0cca 1128 0ccf BLOOPI #0x28, 0x0ccf +0ccc 3ad3 ORR.LD $AC0.M, $AX1.H : $AX0.L, $AX1.H, @$R03 +0ccd b630 MULXMV.S $AX0.H, $AX1.L, $AC0.M : @$R00, $AC0.M +0cce 3ad3 ORR.LD $AC0.M, $AX1.H : $AX0.L, $AX1.H, @$R03 +0ccf b630 MULXMV.S $AX0.H, $AX1.L, $AC0.M : @$R00, $AC0.M +0cd0 8c00 CLR15 +0cd1 8e00 S40 +0cd2 02df RET + + + +0cd3 00da 0485 LR $AX0.H, @0x0485 +0cd5 8600 TSTAXH $AX0.H +0cd6 0295 0ce5 JEQ 0x0ce5 +0cd8 8100 CLR $AC0.M +0cd9 00de 042a LR $AC0.M, @0x042a +0cdb 147f LSR $ACC0, #0x3f +0cdc 00fe 042b SR @0x042b, $AC0.M +0cde b100 TST $AC0.M +0cdf 0294 0ce5 JNE 0x0ce5 +0ce1 009a 0001 LRI $AX0.H, #0x0001 +0ce3 00fa 0401 SR @0x0401, $AX0.H +0ce5 8f00 S16 +0ce6 8100 CLR $AC0.M +0ce7 00de 0428 LR $AC0.M, @0x0428 +0ce9 1478 LSR $ACC0, #0x38 +0cea 00df 0428 LR $AC1.M, @0x0428 +0cec 0340 007f ANDI $ACC1, #0x007f +0cee 1f1e MRR $AX0.L, $AC0.M +0cef 1f5f MRR $AX0.H, $AC1.M +0cf0 0220 007f XORI $ACC0, #0x007f +0cf2 1f3e MRR $AX1.L, $AC0.M +0cf3 0320 007f XORI $ACC1, #0x007f +0cf5 1f7f MRR $AX1.H, $AC1.M +0cf6 8100 CLR $AC0.M +0cf7 8900 CLR $AC1.M +0cf8 009f 0200 LRI $AC1.M, #0x0200 +0cfa 1fd8 MRR $AC0.M, $AX0.L +0cfb 4c00 ADD $AC0.M, $AC1.M +0cfc 1c1e MRR $R00, $AC0.M +0cfd 1818 LRR $AX0.L, @$R00 +0cfe 1fda MRR $AC0.M, $AX0.H +0cff 4c00 ADD $AC0.M, $AC1.M +0d00 1c1e MRR $R00, $AC0.M +0d01 181a LRR $AX0.H, @$R00 +0d02 1fd9 MRR $AC0.M, $AX1.L +0d03 4c00 ADD $AC0.M, $AC1.M +0d04 1c1e MRR $R00, $AC0.M +0d05 1819 LRR $AX1.L, @$R00 +0d06 1fdb MRR $AC0.M, $AX1.H +0d07 4c00 ADD $AC0.M, $AC1.M +0d08 1c1e MRR $R00, $AC0.M +0d09 181b LRR $AX1.H, @$R00 +0d0a 0080 0b00 LRI $R00, #0x0b00 +0d0c 9800 MUL $AX1.L, $AX1.H +0d0d ae00 MULXMV $AX0.L, $AX1.H, $AC0.M +0d0e b630 MULXMV.S $AX0.H, $AX1.L, $AC0.M : @$R00, $AC0.M +0d0f 9630 MULMV.S $AX0.L, $AX0.H, $AC0.M : @$R00, $AC0.M +0d10 6e30 MOVP.S $AC0.M : @$R00, $AC0.M +0d11 1b1e SRRI @$R00, $AC0.M +0d12 0080 0b00 LRI $R00, #0x0b00 +0d14 0081 0b04 LRI $R01, #0x0b04 +0d16 00da 042a LR $AX0.H, @0x042a +0d18 02bf 0d62 CALL 0x0d62 +0d1a 0081 0b08 LRI $R01, #0x0b08 +0d1c 0080 0b04 LRI $R00, #0x0b04 +0d1e 00da 042a LR $AX0.H, @0x042a +0d20 00de 0429 LR $AC0.M, @0x0429 +0d22 c000 MULC $AX0.H, $AC0.M +0d23 6e00 MOVP $AC0.M +0d24 1481 ASL $ACC0, #0x01 +0d25 1f5e MRR $AX0.H, $AC0.M +0d26 02bf 0d62 CALL 0x0d62 +0d28 0080 0b00 LRI $R00, #0x0b00 +0d2a 0081 0b0c LRI $R01, #0x0b0c +0d2c 8100 CLR $AC0.M +0d2d 8900 CLR $AC1.M +0d2e 00de 042b LR $AC0.M, @0x042b +0d30 00df 042a LR $AC1.M, @0x042a +0d32 00fe 042a SR @0x042a, $AC0.M +0d34 5c00 SUB $AC0.M, $AC1.M +0d35 1f5e MRR $AX0.H, $AC0.M +0d36 02bf 0d6b CALL 0x0d6b +0d38 0080 0b0c LRI $R00, #0x0b0c +0d3a 0081 0b10 LRI $R01, #0x0b10 +0d3c 00da 0429 LR $AX0.H, @0x0429 +0d3e 02bf 0d62 CALL 0x0d62 +0d40 0081 0b04 LRI $R01, #0x0b04 +0d42 0082 0b0c LRI $R02, #0x0b0c +0d44 0083 0d77 LRI $R03, #0x0d77 +0d46 1108 0d5f BLOOPI #0x08, 0x0d5f // 8 iterations, = data table size below +0d48 195f LRRI $AC1.M, @$R02 +0d49 15fb ASR $ACC1, #0x7b +0d4a 1f1d MRR $AX0.L, $AC1.L +0d4b 1f5f MRR $AX0.H, $AC1.M +0d4c 193f LRRI $AC1.M, @$R01 +0d4d 00e1 0b24 SR @0x0b24, $R01 +0d4f 00e2 0b25 SR @0x0b25, $R02 +0d51 021b ILRRI $AC0.M, @$R03 // Read from data table at 0d77, increment R03 +0d52 00e3 0b26 SR @0x0b26, $R03 +0d54 1c7e MRR $R03, $AC0.M +0d55 00c0 038f LR $R00, @0x038f +0d57 02bf 0ca9 CALL 0x0ca9 +0d59 00c1 0b24 LR $R01, @0x0b24 +0d5b 00c2 0b25 LR $R02, @0x0b25 +0d5d 00c3 0b26 LR $R03, @0x0b26 +0d5f 0000 NOP // BLOOPI end +0d60 8e00 S40 +0d61 02df RET + + +// Compute something.... load @R00 store @R01 +0d62 191f LRRI $AC1.M, @$R00 +0d63 d078 MULC.L $AX0.H, $AC1.M : $AC1.M, @$R00 +0d64 d678 MULCMV.L $AX0.H, $AC1.M, $AC0.M : $AC1.M, @$R00 +0d65 d631 MULCMV.S $AX0.H, $AC1.M, $AC0.M : @$R01, $AC0.M +0d66 191f LRRI $AC1.M, @$R00 +0d67 d631 MULCMV.S $AX0.H, $AC1.M, $AC0.M : @$R01, $AC0.M +0d68 6e31 MOVP.S $AC0.M : @$R01, $AC0.M +0d69 1b3e SRRI @$R01, $AC0.M +0d6a 02df RET + + +// Compute something... load @R00 store @R01 +// Similar to 0d62 but different register usage. +// Surrounded with SET15/CLR15. +0d6b 8d00 SET15 +0d6c 1f7e MRR $AX1.H, $AC0.M +0d6d 1918 LRRI $AX0.L, @$R00 +0d6e a840 MULX.L $AX0.L, $AX1.H : $AX0.L, @$R00 +0d6f ae40 MULXMV.L $AX0.L, $AX1.H, $AC0.M : $AX0.L, @$R00 +0d70 ae31 MULXMV.S $AX0.L, $AX1.H, $AC0.M : @$R01, $AC0.M +0d71 1918 LRRI $AX0.L, @$R00 +0d72 ae31 MULXMV.S $AX0.L, $AX1.H, $AC0.M : @$R01, $AC0.M +0d73 6e31 MOVP.S $AC0.M : @$R01, $AC0.M +0d74 1b3e SRRI @$R01, $AC0.M +0d75 8c00 CLR15 +0d76 02df RET + + +// This would appear to be a data table. +0d77 0d00 LRIS $AC1.L, #0x00 +0d78 0d60 LRIS $AC1.L, #0x60 +0d79 0f40 LRIS $AC1.M, #0x40 +0d7a 0ca0 LRIS $AC0.L, #0xa0 +0d7b 0e80 LRIS $AC0.M, #0x80 +0d7c 0ee0 LRIS $AC0.M, #0xe0 +0d7d 0c00 LRIS $AC0.L, #0x00 +0d7e 0c50 LRIS $AC0.L, #0x50 + +// Function starts here? 0x28 bufsize. +0d7f 00f9 0361 SR @0x0361, $AX1.L +0d81 1fc0 MRR $AC0.M, $R00 +0d82 0200 fffc ADDI $ACC0, #0xfffc +0d84 1c1e MRR $R00, $AC0.M +0d85 1c5e MRR $R02, $AC0.M +0d86 0083 043c LRI $R03, #0x043c +0d88 197e LRRI $AC0.M, @$R03 +0d89 197f LRRI $AC1.M, @$R03 +0d8a 80a2 NX.SL : $AC0.M, $AX0.H +0d8b 64a3 MOVR.SL $AC0.M, $AX0.H : $AC1.M, $AX0.H +0d8c 6530 MOVR.S $AC1.M, $AX0.H : @$R00, $AC0.M +0d8d 1b1f SRRI @$R00, $AC1.M +0d8e 1c02 MRR $R00, $R02 +0d8f 8100 CLR $AC0.M +0d90 00de 0402 LR $AC0.M, @0x0402 +0d92 00fe 0362 SR @0x0362, $AC0.M +0d94 1474 LSR $ACC0, #0x34 +0d95 1f7e MRR $AX1.H, $AC0.M +0d96 1f3c MRR $AX1.L, $AC0.L +0d97 8900 CLR $AC1.M +0d98 00dd 0430 LR $AC1.L, @0x0430 +0d9a 1504 LSL $ACC1, #0x04 +0d9b 0604 CMPIS $ACC0, #0x04 +0d9c 0290 0df3 JX0 0x0df3 +0d9e 1fdd MRR $AC0.M, $AC1.L +0d9f 0082 02b0 LRI $R02, #0x02b0 +0da1 1050 LOOPI #0x50 +0da2 4b2a ADDAX.S $AC1.M, $AX1.L : @$R02, $AC1.L +0da3 1fbe MRR $AC1.L, $AC0.M +0da4 00fe 0360 SR @0x0360, $AC0.M +0da6 8900 CLR $AC1.M +0da7 1fbe MRR $AC1.L, $AC0.M +0da8 0af8 LRIS $AX0.H, #0xf8 +0da9 009b 00fc LRI $AX1.H, #0x00fc +0dab 00d8 0361 LR $AX0.L, @0x0361 +0dad 0082 02b0 LRI $R02, #0x02b0 +0daf 0083 02b0 LRI $R03, #0x02b0 +0db1 195e LRRI $AC0.M, @$R02 +0db2 3480 ANDR.LS $AC0.M, $AX0.H : $AX0.L, $AC0.M +0db3 1128 0db8 BLOOPI #0x28, 0x0db8 +0db5 367a ANDR.L $AC0.M, $AX1.H : $AC1.M, @$R02 +0db6 35b3 ANDR.SL $AC1.M, $AX0.H : $AC1.M, $AX1.H +0db7 3772 ANDR.L $AC1.M, $AX1.H : $AC0.M, @$R02 +0db8 34bb ANDR.SLM $AC0.M, $AX0.H : $AC1.M, $AX1.H +0db9 8a00 M2 +0dba 0082 02b0 LRI $R02, #0x02b0 +0dbc 00dd 0430 LR $AC1.L, @0x0430 +0dbe 1504 LSL $ACC1, #0x04 +0dbf 1fe0 MRR $AC1.M, $R00 +0dc0 8100 CLR $AC0.M +0dc1 00de 0362 LR $AC0.M, @0x0362 +0dc3 1474 LSR $ACC0, #0x34 +0dc4 1f7e MRR $AX1.H, $AC0.M +0dc5 1f3c MRR $AX1.L, $AC0.L +0dc6 8f00 S16 +0dc7 1943 LRRI $R03, @$R02 +0dc8 4bc3 ADDAX.LD $AC1.M, $AX1.L : $AX0.L, $AX1.L, @$R03 +0dc9 90c3 MUL.LD $AX0.L, $AX0.H : $AX0.L, $AX1.L, @$R03 +0dca f2c3 MADD.LD $AX0.L, $AX0.H : $AX0.L, $AX1.L, @$R03 +0dcb f2c3 MADD.LD $AX0.L, $AX0.H : $AX0.L, $AX1.L, @$R03 +0dcc f200 MADD $AX0.L, $AX0.H +0dcd fe00 MOVPZ $AC0.M +0dce 1c1f MRR $R00, $AC1.M +0dcf 1943 LRRI $R03, @$R02 +0dd0 4bc3 ADDAX.LD $AC1.M, $AX1.L : $AX0.L, $AX1.L, @$R03 +0dd1 90c3 MUL.LD $AX0.L, $AX0.H : $AX0.L, $AX1.L, @$R03 +0dd2 114e 0dda BLOOPI #0x4e, 0x0dda +0dd4 f2c3 MADD.LD $AX0.L, $AX0.H : $AX0.L, $AX1.L, @$R03 +0dd5 f2c3 MADD.LD $AX0.L, $AX0.H : $AX0.L, $AX1.L, @$R03 +0dd6 f231 MADD.S $AX0.L, $AX0.H : @$R01, $AC0.M +0dd7 1c1f MRR $R00, $AC1.M +0dd8 1943 LRRI $R03, @$R02 +0dd9 4bc3 ADDAX.LD $AC1.M, $AX1.L : $AX0.L, $AX1.L, @$R03 +0dda 92c3 MULMVZ.LD $AX0.L, $AX0.H, $AC0.M : $AX0.L, $AX1.L, @$R03 +0ddb f2c3 MADD.LD $AX0.L, $AX0.H : $AX0.L, $AX1.L, @$R03 +0ddc f2c3 MADD.LD $AX0.L, $AX0.H : $AX0.L, $AX1.L, @$R03 +0ddd f231 MADD.S $AX0.L, $AX0.H : @$R01, $AC0.M +0dde fe00 MOVPZ $AC0.M +0ddf 1b3e SRRI @$R01, $AC0.M +0de0 8b00 M0 +0de1 8e00 S40 +0de2 00fe 0433 SR @0x0433, $AC0.M +0de4 1c1f MRR $R00, $AC1.M +0de5 150c LSL $ACC1, #0x0c +0de6 0340 0fff ANDI $ACC1, #0x0fff +0de8 00ff 0430 SR @0x0430, $AC1.M +0dea 0083 043c LRI $R03, #0x043c +0dec 191e LRRI $AC0.M, @$R00 +0ded 191f LRRI $AC1.M, @$R00 +0dee 80a0 NX.LS : $AX0.H, $AC0.M +0def 64a1 MOVR.LS $AC0.M, $AX0.H : $AX0.H, $AC1.M +0df0 6533 MOVR.S $AC1.M, $AX0.H : @$R03, $AC0.M +0df1 1b7f SRRI @$R03, $AC1.M +0df2 02df RET + + + +// bufsize = 0x28 +0df3 1fe0 MRR $AC1.M, $R00 +0df4 1c1f MRR $R00, $AC1.M +0df5 1128 0dfc BLOOPI #0x28, 0x0dfc +0df7 4b70 ADDAX.L $AC1.M, $AX1.L : $AC0.M, @$R00 +0df8 1b3e SRRI @$R01, $AC0.M +0df9 1c1f MRR $R00, $AC1.M +0dfa 4b70 ADDAX.L $AC1.M, $AX1.L : $AC0.M, @$R00 +0dfb 1b3e SRRI @$R01, $AC0.M +0dfc 1c1f MRR $R00, $AC1.M +0dfd 029f 0de2 JMP 0x0de2 +0dff 0083 0520 LRI $R03, #0x0520 +0e01 00de 0433 LR $AC0.M, @0x0433 +0e03 1050 LOOPI #0x50 +0e04 1b7e SRRI @$R03, $AC0.M +0e05 029f 02d8 JMP 0x02d8 +0e07 1c20 MRR $R01, $R00 +0e08 185f LRR $AC1.M, @$R02 +0e09 1f7f MRR $AX1.H, $AC1.M +0e0a 193a LRRI $AX0.H, @$R01 +0e0b 6400 MOVR $AC0.M, $AX0.H +0e0c 0078 0e11 BLOOP $AX0.L, 0x0e11 +0e0e 5659 SUBR.L $AC0.M, $AX1.H : $AX1.H, @$R01 +0e0f 6730 MOVR.S $AC1.M, $AX1.H : @$R00, $AC0.M +0e10 5551 SUBR.L $AC1.M, $AX0.H : $AX0.H, @$R01 +0e11 6438 MOVR.S $AC0.M, $AX0.H : @$R00, $AC1.M +0e12 1a5b SRR @$R02, $AX1.H +0e13 02df RET + + + +// called by init code +{ + a_04e8[0]=0x8240; + a_04e8[1]=0x7fff; + a_04e8[2]=0x7dbf; + a_04e8[3]=0x843f; + a_04f0[0]=0xb23b; + a_04f0[1]=0x7fff; + a_04f0[2]=0x4dc4; + a_04f0[3]=0xd808; + a_04ec[0]=a_04ec[1]=a_04ec[2]=a_04ec[3]=0; + a_04f4[0]=a_04f4[1]=a_04f4[2]=a_04f4[3]=0; +} +0e14 0098 8240 LRI $AX0.L, #0x8240 +0e16 00f8 04e8 SR @0x04e8, $AX0.L +0e18 0098 7fff LRI $AX0.L, #0x7fff +0e1a 00f8 04e9 SR @0x04e9, $AX0.L +0e1c 0098 7dbf LRI $AX0.L, #0x7dbf +0e1e 00f8 04ea SR @0x04ea, $AX0.L +0e20 0098 843f LRI $AX0.L, #0x843f +0e22 00f8 04eb SR @0x04eb, $AX0.L +0e24 0098 b23b LRI $AX0.L, #0xb23b +0e26 00f8 04f0 SR @0x04f0, $AX0.L +0e28 0098 7fff LRI $AX0.L, #0x7fff +0e2a 00f8 04f1 SR @0x04f1, $AX0.L +0e2c 0098 4dc4 LRI $AX0.L, #0x4dc4 +0e2e 00f8 04f2 SR @0x04f2, $AX0.L +0e30 0098 d808 LRI $AX0.L, #0xd808 +0e32 00f8 04f3 SR @0x04f3, $AX0.L +0e34 0098 0000 LRI $AX0.L, #0x0000 +0e36 0080 04ec LRI $R00, #0x04ec +0e38 1004 LOOPI #0x04 +0e39 1b18 SRRI @$R00, $AX0.L +0e3a 0080 04f4 LRI $R00, #0x04f4 +0e3c 1004 LOOPI #0x04 +0e3d 1b18 SRRI @$R00, $AX0.L +0e3e 02df RET + + +// Main Stereo (or dolby) Mixer? +// Is the source sample at 0x0b00? +// 0x50 seems to be a buffer size. Strange one. +0e3f 0080 0f40 LRI $R00, #0x0f40 +0e41 0083 0b00 LRI $R03, #0x0b00 +0e43 8900 CLR $AC1.M +0e44 0f50 LRIS $AC1.M, #0x50 +0e45 0098 6784 LRI $AX0.L, #0x6784 +0e47 02bf 00fa CALL 0x00fa // multiply loop +0e49 0080 04e8 LRI $R00, #0x04e8 +0e4b 0082 04ec LRI $R02, #0x04ec +0e4d 0081 0b00 LRI $R01, #0x0b00 +0e4f 02bf 0ba4 CALL 0x0ba4 // complex multiply loop +0e51 8900 CLR $AC1.M +0e52 0f50 LRIS $AC1.M, #0x50 +0e53 0080 0b00 LRI $R00, #0x0b00 +0e55 0083 0d00 LRI $R03, #0x0d00 +0e57 0098 7fff LRI $AX0.L, #0x7fff +0e59 02bf 00eb CALL 0x00eb // one of the multiply loops +0e5b 8900 CLR $AC1.M +0e5c 0f50 LRIS $AC1.M, #0x50 +0e5d 0080 0b00 LRI $R00, #0x0b00 +0e5f 0083 0d60 LRI $R03, #0x0d60 +0e61 0098 b820 LRI $AX0.L, #0xb820 +0e63 02bf 00eb CALL 0x00eb // one of the multiply loops +// Stereo mixer? (cont'd, other channel starts here?) +0e65 0080 0ca0 LRI $R00, #0x0ca0 +0e67 0083 0b00 LRI $R03, #0x0b00 +0e69 8900 CLR $AC1.M +0e6a 0f50 LRIS $AC1.M, #0x50 +0e6b 0098 6784 LRI $AX0.L, #0x6784 +0e6d 02bf 00fa CALL 0x00fa // multiply loop +0e6f 0080 04e8 LRI $R00, #0x04e8 +0e71 0082 04f4 LRI $R02, #0x04f4 +0e73 0081 0b00 LRI $R01, #0x0b00 +0e75 02bf 0ba4 CALL 0x0ba4 // complex multiply loop +0e77 8900 CLR $AC1.M +0e78 0f50 LRIS $AC1.M, #0x50 +0e79 0080 0b00 LRI $R00, #0x0b00 +0e7b 0083 0d00 LRI $R03, #0x0d00 +0e7d 0098 47e0 LRI $AX0.L, #0x47e0 +0e7f 02bf 00eb CALL 0x00eb // one of the multiply loops +0e81 8900 CLR $AC1.M +0e82 0f50 LRIS $AC1.M, #0x50 +0e83 0080 0b00 LRI $R00, #0x0b00 +0e85 0083 0d60 LRI $R03, #0x0d60 +0e87 0098 8001 LRI $AX0.L, #0x8001 +0e89 02bf 00eb CALL 0x00eb // one of the multiply loops +0e8b 02df RET +0e8c 0000 NOP +0e8d 0000 NOP +0e8e 0000 NOP +0e8f 0000 NOP diff --git a/docs/DSP/GC DSP.pdf b/docs/DSP/GC DSP.pdf new file mode 100644 index 0000000000..472a5dc4a8 Binary files /dev/null and b/docs/DSP/GC DSP.pdf differ diff --git a/docs/DSP/SrcSelect_.c b/docs/DSP/SrcSelect_.c new file mode 100644 index 0000000000..c15997c4f4 --- /dev/null +++ b/docs/DSP/SrcSelect_.c @@ -0,0 +1,226 @@ + +// Init Hardware PCM decoder + + /* + 06a3 0082 0bb8 LRI $R02, #0x0bb8 + 06a5 195e LRRI $AC0.M, @$R02 + 06a6 2ed1 SRS @SampleFormat, $AC0.M + 06a7 195e LRRI $AC0.M, @$R02 + 06a8 2ed4 SRS @ACSAH, $AC0.M + 06a9 195e LRRI $AC0.M, @$R02 + 06aa 2ed5 SRS @ACSAL, $AC0.M + 06ab 195e LRRI $AC0.M, @$R02 + 06ac 2ed6 SRS @ACEAH, $AC0.M + 06ad 195e LRRI $AC0.M, @$R02 + 06ae 2ed7 SRS @ACEAL, $AC0.M + 06af 195e LRRI $AC0.M, @$R02 + 06b0 2ed8 SRS @ACCAH, $AC0.M + 06b1 195e LRRI $AC0.M, @$R02 + 06b2 2ed9 SRS @ACCAL, $AC0.M + 06b3 195e LRRI $AC0.M, @$R02 + 06b4 2ea0 SRS @COEF_A1_0, $AC0.M + 06b5 195e LRRI $AC0.M, @$R02 + 06b6 2ea1 SRS @COEF_A2_0, $AC0.M + 06b7 195e LRRI $AC0.M, @$R02 + 06b8 2ea2 SRS @COEF_A1_1, $AC0.M + 06b9 195e LRRI $AC0.M, @$R02 + 06ba 2ea3 SRS @COEF_A2_1, $AC0.M + 06bb 195e LRRI $AC0.M, @$R02 + 06bc 2ea4 SRS @COEF_A1_2, $AC0.M + 06bd 195e LRRI $AC0.M, @$R02 + 06be 2ea5 SRS @COEF_A2_2, $AC0.M + 06bf 195e LRRI $AC0.M, @$R02 + 06c0 2ea6 SRS @COEF_A1_3, $AC0.M + 06c1 195e LRRI $AC0.M, @$R02 + 06c2 2ea7 SRS @COEF_A2_3, $AC0.M + 06c3 195e LRRI $AC0.M, @$R02 + 06c4 2ea8 SRS @COEF_A1_4, $AC0.M + 06c5 195e LRRI $AC0.M, @$R02 + 06c6 2ea9 SRS @COEF_A2_4, $AC0.M + 06c7 195e LRRI $AC0.M, @$R02 + 06c8 2eaa SRS @COEF_A1_5, $AC0.M + 06c9 195e LRRI $AC0.M, @$R02 + 06ca 2eab SRS @COEF_A2_5, $AC0.M + 06cb 195e LRRI $AC0.M, @$R02 + 06cc 2eac SRS @COEF_A1_6, $AC0.M + 06cd 195e LRRI $AC0.M, @$R02 + 06ce 2ead SRS @COEF_A2_6, $AC0.M + 06cf 195e LRRI $AC0.M, @$R02 + 06d0 2eae SRS @COEF_A1_7, $AC0.M + 06d1 195e LRRI $AC0.M, @$R02 + 06d2 2eaf SRS @COEF_A2_7, $AC0.M + 06d3 195e LRRI $AC0.M, @$R02 + 06d4 2ede SRS @GAIN, $AC0.M + 06d5 195e LRRI $AC0.M, @$R02 + 06d6 2eda SRS @pred_scale, $AC0.M + 06d7 195e LRRI $AC0.M, @$R02 + 06d8 2edb SRS @yn1, $AC0.M + 06d9 195e LRRI $AC0.M, @$R02 + 06da 2edc SRS @yn2, $AC0.M + */ + +/// hmmmmmm +/* + 06db 8c00 CLR15 + 06dc 8a00 M2 + 06dd 8e00 S40 +*/ + +/// + + AX0.L = *0xe16 + AX1.H = ratioHi // sample ratio from AXPBSRC + AX1.L = ratioLo // sample ratio from AXPBSRC + + AC0 = 0 + AC0.L = currentAddressFrac // AXPBSRC + + *0x0e48 = last_samples[0] + *0x0e49 = last_samples[1] + *0x0e4A = last_samples[2] + *0x0e4B = last_samples[3] + + AC1.M = AX1.L + ACC = ACC >> 0x05 + AC1 = AC1 + AC0 + + R04 = AC1.M + R05 = AC1.L + + AC1 = AC1 + 0xe0 // ?????? AC1 = AC1 - 2097152 (because 0xe0 is converted to signed and shift << 16) + AC1 = AC1 >> 16 + AC1 = -AC1 + + R06 = -AC1 + +////////////// + AC1 = 0 + AC1.L = R05 + AC1 = AC1 << 2 + R05 = AC1.M + + +// 0x06fc + + AX.0 = 0x1fc + AC0 = 0xe48 + R01 = 0xFFDD + R03 = 0x0D80 + +// 0x0704 + for (i=0; i0;ac1.m--) mem[ac0.m++]=0; /* clear all vars */ + fcn_0688(); /* init some vars */ + fcn_04c0(); /* set something up related to the accelerator at a_0b00 */ + fcn_0e14(); /* set up a table */ + fcn_066a(0); /* send a message */ + fcn_0674(0x1111); /* send a message */ + v_034e=0; + SBSET(5); /* enable interrupts? */ + + /* jump to 0x06c5 */ +mainloop: + while (v_0352) ; /* while no messages pending */ + + SBCLR(5); /* do not distrub */ + v_0352--; /* important that this be atomic */ + SBSET(5); + + t=v_0351; + size=mem[t++]; + if (!(size&0x8000)) { /* size > 0x7fff invalid */ + if (size==0) { /* die on message of length 0? */ + /* jump to 0x06f5 */ + /* jump to 0x05f0 */ + + /* TODO: analysis of HALT */ + HALT(); + } + for (i=size,j=0;i>0;i--) { + a_0356[j++]=mem[t++]; + a_0356[j++]=mem[t++]; + } + v_0351=t; + + /* jump to 0x002f */ + /* actual command handling */ + v_0345=a_0356[1]; + v_0344=a_0356[0]&0x00ff; + v_0343=(a_0346[0]>>7)&0x7e; + + /* jump table at 0x75 used here */ + switch (v_0343>>1) { + + // 0x43 + case 0: + case 10: + case 11: + case 12: + case 14: + case 15: + /* invalid command? */ + config=0x00ff; + fcn_066a(0x04); /* send off a message */ + fcn_0674(a_0356[0]); /* send first word of command as a message */ + goto mainloop; + break; + case 1: + /* jmp 0x0095 */ + break; + + case 2: + /* jmp 0x0243 */ + sub_0243(); + break; + + case 3: + /* jmp 0x0073 */ + break; + + case 4: + /* jmp 0x580 */ + break; + + case 5: + /* jmp 0x592 */ + break; + + case 6: + /* jmp 0x469 */ + break; + + case 7: + /* jmp 0x41d */ + break; + + case 8: /* mix */ + /* jmp 0x0485 */ + fcn_0067(fcn_0067(0x0346)); /* read message twice? */ + /* take in the two buffers to mix */ + fcn_0525(mem[0x344],mem[0x346],mem[0x347],0x400); /* size, addrH, addrL, dsp addr */ + fcn_0525(mem[0x344],mem[0x348],mem[0x349],0x800); + S16(); /* saturate all adds, multiplies to 16 bits? */ + + i=mem[0x0344]; + src1=0x400; + src2=0x800; + scale=mem[0x345]; + + prod=scale*mem[src2++]; + val2=mem[src2++]; + do { + val1=mem[src1]; + val1+=prod; + prod=scale*val2; + mem[src1]=val1; + val2=mem[src2]; + src1++; + src2++; + } while (--i); + + S40(); + + /* dma out mixed buf */ + fcn_0523(mem[0x344],mem[0x346],mem[0x347],0x400); + + break; + + case 9: + /* jmp 0x44d */ + break; + + case 13: + /* jmp 0x00b2 */ + break; + } + } + + v_0351=t; + + goto mainloop; +} + +/* message in MBOX exception vector? 0x000e */ +void exception() { + /* JMP 0x05b8 */ + + SBCLR(5); + S40(); + /* save ax0.h,ac0.h,ac0.m, and ac0.l */ + + if ((tH=register_fffe)&0x8000) { /* CPU mailbox H */ + if (!(tsize=register_ffff)) { /* CPU mailbox L */ + /* empty message? */ + while (!((tH=register_fffe)&0x8000)) ; + tH&=0xf; + v_034e=(tH+1)<<4; + a_04fc[tH]=register_ffff; + } else { /* nonempty message? */ + /* jump to 0x0692 */ + /* save ar0, r08 */ + t=v_0350; + mem[t++]=tsize; + + do { + while (!((tH=register_fffe)&0x8000)) ; + mem[t++]=tH; + mem[t++]=register_ffff; + } while (--tsize); + + v_0350=t; + v_0352++; + /* restore ar0, r08 */ + + /* jump to 0x05e6 */ + } + } else { /* interrupt without message? */ + /* jump to 0x06b9 */ + /* save ar0, r08 */ + mem[v_0350]=0; /* empty message */ + /* jump to 0x06ab */ + v_0350++; + v_0352++; + /* restore ar0, r08 */ + + /* jump to 0x05e6 */ + } + + /* 0x05e6 */ + + /* restore ax0.h,ac0.h,ac0.m, and ac0.l */ + SBSET(5); + /* RTI */ +} + +/* set up some registers */ +void fcn_0057() { + SBCLR(2); + SBCLR(3); + SBCLR(4); + SBCLR(6); + S40(); /* 40-bit mode */ + CLR15(); + M0(); /* don't multiply result by 2 */ + r08=-1; + r09=-1; + r0a=-1; + r0b=-1; + config=0xff; +} + +void fcn_0688() { + v_0350=0x0280; + v_0351=0x0280; + v_0352=0; +} + +void fcn_04c0() { + config=0xff; + for(i=0xff,ar0=0xb00;i>0;i--) mem[ar0++]=0; + mem[ar0++]=0; /* get the last one */ + fcn_0573(0x0b00,0x0100,0); +} + +/* a=an address in ac1.m, l=a length in ar0, v=a value? in ac0.m */ +void fcn_0573(short a, short l, short v) { + fcn_0561(a,l,0x0001); +} + +/* a=an address in ac1.m, l=a length in ar0, v=a value? in ac0.m, f is a flag? in ac0.h */ +/* return is in ax0.h */ +short fcn_0561(short a, short l, short v, short f) { + register_ffd1=0x0a; /* unknown reg, accel? */ + register_ffd6=-1; /* accel end addr H */ + register_ffd7=-1; /* accel end addr L */ + register_ffd8=v>>1; /* + register_ffd9=?; /* has a value from way back? */ + + return f; +} + +/* initializes some tables that look useful... */ +void fcn_0e14() { + a_04e8[0]=0x8240; + a_04e8[1]=0x7fff; + a_04e8[2]=0x7dbf; + a_04e8[3]=0x843f; + a_04f0[0]=0xb23b; + a_04f0[1]=0x7fff; + a_04f0[2]=0x4dc4; + a_04f0[3]=0xd808; + a_04ec[0]=a_04ec[1]=a_04ec[2]=a_04ec[3]=0; + a_04f4[0]=a_04f4[1]=a_04f4[2]=a_04f4[3]=0; +} + +/* send a message via DSP MBOX */ +void fcn_066a(short m) { + fcn_0682(); /* wait for empty mbox */ + register_fffc=0xdcd1; + register_fffd=m; + register_fffb=1; /* IRQ */ + fcn_0682(); +} + +/* wait for dsp mbox empty */ +void fcn_0682() { + while (register_fffc&0x8000); +} + +void fcn_0674(short m) { + fcn_0682(); + register_fffc=0xf355; + register_fffd=m; + fcn_0682(); +} + +/* a=address in ar0 */ +/* fetch a message body (up to zero)? */ +short fcn_0067(short a) { + i=0x0357; + j=a; + do { + mem[j++]=mem[i++]; + mem[j++]=mem[i]; + } while (mem[i++]); + return a; +} + +/* dma in, I assume */ +/* size=words to transfer in ar0, addrL=low word of RAM address in ac0.l, addrH=high word of RAM address in ac0.m, dspaddr=dsp address in ac1.m */ +void fcn_0525(short size, short addrH, short addrL, short dspaddr) { + register_ffcd=dspaddr; /* dsp address */ + register_ffc9=0; /* direction: ram->dsp */ + register_ffce=addrH; /* memory address H */ + register_ffcf=addrL; /* memory address L */ + register_ffcb=size<<1; /* bytes to transfer (size must be in words) */ + fcn_0536(); /* dma wait */ +} + +/* dma wait? */ +void fcn_0536() { + while (!(register_ffc9&4)); +} + +/* dma out, I assume */ +/* size=words to transfer in ar0, addrL=low word of RAM address is ac0.l, addrH=high word of RAM address in ac0.m, dspaddr=dsp address in ac1.m */ +/* shares code with fcn_0525 */ +void fcn_0523(short size, short addrH, short addrL, shot dspaddr) { + register_ffcd=dspaddr; + /* jump back into 0525 */ + register_ffc9=1; /* direction dsp->ram */ + register_ffce=addrH; + register_ffcf=addrL; + register_ffcb=size<<1; + fcn_0536(); +} + +/* huge subroutine, op #2 */ +void sub_0243() { + fcn_0067(0x0388); /* called in an indirect manner... */ + v_0341=v_0344; /* low byte first word of message */ + v_038e=v_0345; + v_0355=0; + fcn_022a(); /* get stuffs */ + fcn_05a4(); /* write to accel */ + + for (i=v_0341;i>0i--) { + fcn_0102(); + + } +} + +void fcn_022a() { + /* something else must set 386, 387 */ + fcn_0525(0x0040,v_0386,v_0387,0x03a8); +} + +void fcn_05a4() { + register_ffd4=-1; + register_ffd5=-1; + register_ffd6=-1; + register_ffd7=-1; +} + +void fcn_0102() { + for (i=0;i<0x50;i++) a_0d00[i]=0; + for (i=0;i<0x50;i++) a_0d60[i]=0; + fcn_0e3f(); + for (i=0;i<0x50;i++) a_0ca0[i]=0; + for (i=0;i<0x50;i++) a_0f40[i]=0; + for (i=0;i<0x50;i++) a_0fa0[i]=0; + for (i=0;i<0x50;i++) a_0a00[i]=0; + for (i=0;i<0x50;i++) a_09a0[i]=0; +} + +void fcn_0e3f() { + fcn_00fa(0x0f40,0x0b00,0x50,0x6784); + fcn_0ba4(0x04e8,0x0b00,0x04ec); +} + +/* addr1=address in ar0, addr2=address in ar3, size=size of table at addr1 in ac1.m, val=in ax0.l */ +void fcn_00fa(short addr1, short addr2, short size, short val) { + M2(); /* all multiplications 2x */ + + tmp=mem[addr1++]; + prod=val*tmp*2; + tmp=mem[addr1++]; + ac0.m=prod; + prod=val*tmp*2; + tmp=mem[addr1++]; + + do { + ac0.m=prod; + prod=val*tmp*2; + mem[addr2]=ac0.m; + tmp=mem[addr1]; + addr1++; + addr2++; + } while (--size); + + M0(); +} + +/* addr1=address in ar0 (source 4 element table?), addr2=address in ar1 (accelerator?), addr3=address in ar2 (destination 4 element table?) */ +void fcn_00ba4(short addr1, short addr2, short addr3) { + +} \ No newline at end of file diff --git a/docs/DSP/zeldaNotes.txt b/docs/DSP/zeldaNotes.txt new file mode 100644 index 0000000000..984e1961fa --- /dev/null +++ b/docs/DSP/zeldaNotes.txt @@ -0,0 +1,34 @@ +DSP startup sequence: + +DspBoot called with (JASystem::TAudioThread::syncDSP()) as a parameter. +DSP lib initialized +A Dsp task is created: + init callback = DspHandShake() + req callback = JASystem::TAudioThread::syncDSP() +Task is pushed as first task and executed + +DSP send DSP_INIT command (0xDCD10003) +__DSPHandler receive the command + +task's init callback (DspHandShake) is called +1 mail is read from dsp (and discarded) +DSP flag is set as running + +AIRegisterDMACallback(JASystem::TAudioThread::syncAudio((void)) +AIStartDMA() to initialize dma in AI module + +----------------------------------- + +DSP run sequence: + +__DSPHandler receive command DSP_RESUME +callback JASystem::TAudioThread::syncDSP called and pull 1 mail +A message is send by OSSendMessage(1) + +JASystem::TAudioThread::audioproc receive OSMessage: + 0=update dac + 1=update dsp + 2=nop ? + 3=exit thread + +dsp is updated \ No newline at end of file diff --git a/DSP_UC_SuperMarioGalaxy.txt b/docs/DSP_UC_SuperMarioGalaxy.txt similarity index 100% rename from DSP_UC_SuperMarioGalaxy.txt rename to docs/DSP_UC_SuperMarioGalaxy.txt diff --git a/docs/WiiMote/Dumps/WiiMote_AttribTree_0x10000.bin b/docs/WiiMote/Dumps/WiiMote_AttribTree_0x10000.bin new file mode 100644 index 0000000000..d407362439 Binary files /dev/null and b/docs/WiiMote/Dumps/WiiMote_AttribTree_0x10000.bin differ diff --git a/docs/WiiMote/Dumps/WiiMote_AttribTree_0x10000.txt b/docs/WiiMote/Dumps/WiiMote_AttribTree_0x10000.txt new file mode 100644 index 0000000000..0d1fc93b8c --- /dev/null +++ b/docs/WiiMote/Dumps/WiiMote_AttribTree_0x10000.txt @@ -0,0 +1,200 @@ +chaoscode@chaoscode-desktop:~$ sudo hcidump -x -p 1 -R -w rawdump4.bin +[sudo] password for chaoscode: +HCI sniffer - Bluetooth packet analyzer ver 1.40 +device: hci0 snap_len: 1028 filter: 0x0 + +chaoscode@chaoscode-desktop:~$ hcidump -r rawdump4.bin -X +HCI sniffer - Bluetooth packet analyzer ver 1.40 +< HCI Command: Create Connection (0x01|0x0005) plen 13 + 0000: d7 c8 d9 47 21 00 18 cc 02 00 00 00 01 ...G!........ +> HCI Event: Command Status (0x0f) plen 4 + 0000: 00 01 05 04 .... +> HCI Event: Connect Complete (0x03) plen 11 + 0000: 00 0c 00 d7 c8 d9 47 21 00 01 00 ......G!... +< ACL data: handle 12 flags 0x02 dlen 10 + L2CAP(s): Info req: type 2 +< HCI Command: Read Remote Supported Features (0x01|0x001b) plen 2 + 0000: 0c 00 .. +> HCI Event: Command Status (0x0f) plen 4 + 0000: 00 01 1b 04 .... +< HCI Command: Write Link Policy Settings (0x02|0x000d) plen 4 + 0000: 0c 00 0f 00 .... +> HCI Event: Read Remote Supported Features (0x0b) plen 11 + 0000: 00 0c 00 bc 02 04 38 08 00 00 00 ......8.... +> HCI Event: Command Complete (0x0e) plen 6 + 0000: 01 0d 08 00 0c 00 ...... +< HCI Command: Remote Name Request (0x01|0x0019) plen 10 + 0000: d7 c8 d9 47 21 00 02 00 00 00 ...G!..... +> HCI Event: Command Status (0x0f) plen 4 + 0000: 00 01 19 04 .... +> ACL data: handle 12 flags 0x02 dlen 16 + L2CAP(s): Info rsp: type 2 result 0 + Extended feature mask 0x0004 +< ACL data: handle 12 flags 0x02 dlen 12 + L2CAP(s): Connect req: psm 1 scid 0x0040 +> ACL data: handle 12 flags 0x02 dlen 16 + L2CAP(s): Connect rsp: dcid 0x0051 scid 0x0040 result 0 status 0 + Connection successful +< ACL data: handle 12 flags 0x02 dlen 12 + L2CAP(s): Config req: dcid 0x0051 flags 0x00 clen 0 +> ACL data: handle 12 flags 0x02 dlen 18 + L2CAP(s): Config rsp: scid 0x0040 flags 0x00 result 0 clen 4 + Success + MTU 185 +> ACL data: handle 12 flags 0x02 dlen 16 + L2CAP(s): Config req: dcid 0x0040 flags 0x00 clen 4 + MTU 185 +< ACL data: handle 12 flags 0x02 dlen 18 + L2CAP(s): Config rsp: scid 0x0051 flags 0x00 result 0 clen 4 + Success + MTU 185 +< ACL data: handle 12 flags 0x02 dlen 23 + L2CAP(d): cid 0x0051 len 19 [psm 1] + SDP SA Req: tid 0x0 len 0xe + handle 0x10000 + max 65535 + aid(s) 0x0000 - 0xffff + cont 00 +> HCI Event: Remote Name Req Complete (0x07) plen 255 + 0000: 00 d7 c8 d9 47 21 00 4e 69 6e 74 65 6e 64 6f 20 ....G!.Nintendo + 0010: 52 56 4c 2d 43 4e 54 2d 30 31 00 00 00 00 00 00 RVL-CNT-01...... + 0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ + 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ + 0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ + 0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ + 0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ + 0070: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ + 0080: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ + 0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ + 00a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ + 00b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ + 00c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ + 00d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ + 00e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ + 00f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ............... +> HCI Event: Number of Completed Packets (0x13) plen 5 + 0000: 01 0c 00 04 00 ..... +> ACL data: handle 12 flags 0x02 dlen 27 +> ACL data: handle 12 flags 0x01 dlen 27 +> ACL data: handle 12 flags 0x01 dlen 27 +> ACL data: handle 12 flags 0x01 dlen 27 +> ACL data: handle 12 flags 0x01 dlen 24 + L2CAP(d): cid 0x0040 len 128 [psm 1] + SDP SA Rsp: tid 0x0 len 0x7b + count 118 + cont 02 00 76 +< ACL data: handle 12 flags 0x02 dlen 25 + L2CAP(d): cid 0x0051 len 21 [psm 1] + SDP SA Req: tid 0x1 len 0x10 + handle 0x10000 + max 65535 + aid(s) 0x0000 - 0xffff + cont 02 00 76 +> ACL data: handle 12 flags 0x02 dlen 27 +> ACL data: handle 12 flags 0x01 dlen 27 +> ACL data: handle 12 flags 0x01 dlen 27 +> ACL data: handle 12 flags 0x01 dlen 27 +> ACL data: handle 12 flags 0x01 dlen 24 + L2CAP(d): cid 0x0040 len 128 [psm 1] + SDP SA Rsp: tid 0x1 len 0x7b + count 118 + cont 02 00 EC +< ACL data: handle 12 flags 0x02 dlen 25 + L2CAP(d): cid 0x0051 len 21 [psm 1] + SDP SA Req: tid 0x2 len 0x10 + handle 0x10000 + max 65535 + aid(s) 0x0000 - 0xffff + cont 02 00 EC +> ACL data: handle 12 flags 0x02 dlen 27 +> ACL data: handle 12 flags 0x01 dlen 27 +> ACL data: handle 12 flags 0x01 dlen 27 +> ACL data: handle 12 flags 0x01 dlen 27 +> ACL data: handle 12 flags 0x01 dlen 24 + L2CAP(d): cid 0x0040 len 128 [psm 1] + SDP SA Rsp: tid 0x2 len 0x7b + count 118 + cont 02 01 62 +< ACL data: handle 12 flags 0x02 dlen 25 + L2CAP(d): cid 0x0051 len 21 [psm 1] + SDP SA Req: tid 0x3 len 0x10 + handle 0x10000 + max 65535 + aid(s) 0x0000 - 0xffff + cont 02 01 62 +> HCI Event: Number of Completed Packets (0x13) plen 5 + 0000: 01 0c 00 04 00 ..... +> ACL data: handle 12 flags 0x02 dlen 27 +> ACL data: handle 12 flags 0x01 dlen 27 +> ACL data: handle 12 flags 0x01 dlen 27 +> ACL data: handle 12 flags 0x01 dlen 27 +> ACL data: handle 12 flags 0x01 dlen 13 + L2CAP(d): cid 0x0040 len 117 [psm 1] + SDP SA Rsp: tid 0x3 len 0x70 + count 109 + aid 0x0000 (SrvRecHndl) + uint 0x10000 + aid 0x0001 (SrvClassIDList) + < uuid-16 0x1124 (HID) > + aid 0x0004 (ProtocolDescList) + < < uuid-16 0x0100 (L2CAP) uint 0x11 > < + uuid-16 0x0011 (HIDP) > > + aid 0x0005 (BrwGrpList) + < uuid-16 0x1002 (PubBrwsGrp) > + aid 0x0006 (LangBaseAttrIDList) + < uint 0x656e uint 0x6a uint 0x100 > + aid 0x0009 (BTProfileDescList) + < < uuid-16 0x1124 (HID) uint 0x100 > > + aid 0x000d (IconURL) + < < < uuid-16 0x0100 (L2CAP) uint 0x13 > < uuid-16 0x0011 (HIDP) > > > + aid 0x0100 (SrvName) + str "Nintendo RVL-CNT-01" + aid 0x0101 (SrvDesc) + str "Nintendo RVL-CNT-01" + aid 0x0102 (ProviderName) + str "Nintendo" + aid 0x0200 (VersionNumList) + uint 0x100 + aid 0x0201 (SrvDBState) + uint 0x111 + aid 0x0202 (unknown) + uint 0x4 + aid 0x0203 (unknown) + uint 0x33 + aid 0x0204 (unknown) + bool 0x0 + aid 0x0205 (unknown) + bool 0x1 + aid 0x0206 (unknown) + < < uint 0x22 str 05 01 09 05 a1 01 85 10 15 00 26 ff 00 75 08 95 01 06 00 ff 09 01 91 00 85 11 95 01 09 01 91 00 85 12 95 02 09 01 91 00 85 13 95 01 09 01 91 00 85 14 95 01 09 01 91 00 85 15 95 01 09 01 91 00 85 16 95 15 09 01 91 00 85 17 95 06 09 01 91 00 85 18 95 15 09 01 91 00 85 19 95 01 09 01 91 00 85 1a 95 01 09 01 91 00 85 20 95 06 09 01 81 00 85 21 95 15 09 01 81 00 85 22 95 04 09 01 81 00 85 30 95 02 09 01 81 00 85 31 95 05 09 01 81 00 85 32 95 0a 09 01 81 00 85 33 95 11 09 01 81 00 85 34 95 15 09 01 81 00 85 35 95 15 09 01 81 00 85 36 95 15 09 01 81 00 85 37 95 15 09 01 81 00 85 3d 95 15 09 01 81 00 85 3e 95 15 09 01 81 00 85 3f 95 15 09 01 81 00 c0 > > + aid 0x0207 (unknown) + < < uint 0x409 uint 0x100 > > + aid 0x0208 (unknown) + bool 0x0 + aid 0x0209 (unknown) + bool 0x1 + aid 0x020a (unknown) + bool 0x1 + aid 0x020b (unknown) + uint 0x100 + aid 0x020c (unknown) + uint 0xc80 + aid 0x020d (unknown) + bool 0x0 + aid 0x020e (unknown) + bool 0x0 + cont 00 +< ACL data: handle 12 flags 0x02 dlen 12 + L2CAP(s): Disconn req: dcid 0x0051 scid 0x0040 +> ACL data: handle 12 flags 0x02 dlen 12 + L2CAP(s): Disconn rsp: dcid 0x0051 scid 0x0040 +> HCI Event: Number of Completed Packets (0x13) plen 5 + 0000: 01 0c 00 01 00 ..... +< HCI Command: Disconnect (0x01|0x0006) plen 3 + 0000: 0c 00 13 ... +> HCI Event: Command Status (0x0f) plen 4 + 0000: 00 01 06 04 .... +> HCI Event: Disconn Complete (0x05) plen 4 + 0000: 00 0c 00 16 .... +chaoscode@chaoscode-desktop:~$ + diff --git a/docs/WiiMote/Dumps/WiiMote_AttribTree_0x10000_strip.bin b/docs/WiiMote/Dumps/WiiMote_AttribTree_0x10000_strip.bin new file mode 100644 index 0000000000..ce6d66198d Binary files /dev/null and b/docs/WiiMote/Dumps/WiiMote_AttribTree_0x10000_strip.bin differ diff --git a/docs/WiiMote/Dumps/WiiMote_AttribTree_0x10001.bin b/docs/WiiMote/Dumps/WiiMote_AttribTree_0x10001.bin new file mode 100644 index 0000000000..3c381679ff Binary files /dev/null and b/docs/WiiMote/Dumps/WiiMote_AttribTree_0x10001.bin differ diff --git a/docs/WiiMote/Dumps/WiiMote_AttribTree_0x10001.txt b/docs/WiiMote/Dumps/WiiMote_AttribTree_0x10001.txt new file mode 100644 index 0000000000..1af4a3c23b --- /dev/null +++ b/docs/WiiMote/Dumps/WiiMote_AttribTree_0x10001.txt @@ -0,0 +1,176 @@ +HCI sniffer - Bluetooth packet analyzer ver 1.40 +> ACL data: handle 12 flags 0x02 dlen 8 + L2CAP(d): cid 0x0041 len 4 [psm 0] + 0000: a1 30 00 10 .0.. +> ACL data: handle 12 flags 0x02 dlen 8 + L2CAP(d): cid 0x0041 len 4 [psm 0] + 0000: a1 30 00 00 .0.. +< HCI Command: Inquiry (0x01|0x0001) plen 5 + lap 0x9e8b33 len 8 num 0 +> HCI Event: Command Status (0x0f) plen 4 + Inquiry (0x01|0x0001) status 0x00 ncmd 1 +< HCI Command: Inquiry Cancel (0x01|0x0002) plen 0 +> HCI Event: Command Complete (0x0e) plen 4 + Inquiry Cancel (0x01|0x0002) ncmd 1 + status 0x00 +> ACL data: handle 12 flags 0x02 dlen 8 + L2CAP(d): cid 0x0041 len 4 [psm 0] + 0000: a1 30 00 10 .0.. +> ACL data: handle 12 flags 0x02 dlen 8 + L2CAP(d): cid 0x0041 len 4 [psm 0] + 0000: a1 30 00 00 .0.. +> ACL data: handle 12 flags 0x02 dlen 8 + L2CAP(d): cid 0x0041 len 4 [psm 0] + 0000: a1 30 00 10 .0.. +> ACL data: handle 12 flags 0x02 dlen 8 + L2CAP(d): cid 0x0041 len 4 [psm 0] + 0000: a1 30 00 00 .0.. +< HCI Command: Inquiry (0x01|0x0001) plen 5 + lap 0x9e8b33 len 8 num 0 +> HCI Event: Command Status (0x0f) plen 4 + Inquiry (0x01|0x0001) status 0x00 ncmd 1 +> ACL data: handle 12 flags 0x02 dlen 8 + L2CAP(d): cid 0x0041 len 4 [psm 0] + 0000: a1 30 00 10 .0.. +> ACL data: handle 12 flags 0x02 dlen 8 + L2CAP(d): cid 0x0041 len 4 [psm 0] + 0000: a1 30 00 00 .0.. +> ACL data: handle 12 flags 0x02 dlen 8 + L2CAP(d): cid 0x0041 len 4 [psm 0] + 0000: a1 30 00 10 .0.. +> ACL data: handle 12 flags 0x02 dlen 8 + L2CAP(d): cid 0x0041 len 4 [psm 0] + 0000: a1 30 00 00 .0.. +> ACL data: handle 12 flags 0x02 dlen 8 + L2CAP(d): cid 0x0041 len 4 [psm 0] + 0000: a1 30 00 10 .0.. +> ACL data: handle 12 flags 0x02 dlen 8 + L2CAP(d): cid 0x0041 len 4 [psm 0] + 0000: a1 30 00 00 .0.. +> ACL data: handle 12 flags 0x02 dlen 8 + L2CAP(d): cid 0x0041 len 4 [psm 0] + 0000: a1 30 10 00 .0.. +> HCI Event: Inquiry Complete (0x01) plen 1 + status 0x00 +> ACL data: handle 12 flags 0x02 dlen 8 + L2CAP(d): cid 0x0041 len 4 [psm 0] + 0000: a1 30 00 00 .0.. +> ACL data: handle 12 flags 0x02 dlen 8 + L2CAP(d): cid 0x0041 len 4 [psm 0] + 0000: a1 30 10 00 .0.. +> ACL data: handle 12 flags 0x02 dlen 8 + L2CAP(d): cid 0x0041 len 4 [psm 0] + 0000: a1 30 00 00 .0.. +< HCI Command: Create Connection (0x01|0x0005) plen 13 + bdaddr 00:1F:C5:36:2B:32 ptype 0xcc18 rswitch 0x01 clkoffset 0x0000 + Packet type: DM1 DM3 DM5 DH1 DH3 DH5 +> HCI Event: Command Status (0x0f) plen 4 + Create Connection (0x01|0x0005) status 0x00 ncmd 1 +< HCI Command: Create Connection Cancel (0x01|0x0008) plen 6 + bdaddr 00:1F:C5:36:2B:32 +> HCI Event: Command Complete (0x0e) plen 10 + Create Connection Cancel (0x01|0x0008) ncmd 1 + status 0x00 bdaddr 00:1F:C5:36:2B:32 +> HCI Event: Connect Complete (0x03) plen 11 + status 0x02 handle 12 bdaddr 00:1F:C5:36:2B:32 type ACL encrypt 0x00 + Error: Unknown Connection Identifier +< HCI Command: Create Connection (0x01|0x0005) plen 13 + bdaddr 00:1F:C5:36:2B:32 ptype 0xcc18 rswitch 0x01 clkoffset 0x0000 + Packet type: DM1 DM3 DM5 DH1 DH3 DH5 +> HCI Event: Command Status (0x0f) plen 4 + Create Connection (0x01|0x0005) status 0x00 ncmd 1 +> HCI Event: Connect Complete (0x03) plen 11 + status 0x00 handle 12 bdaddr 00:1F:C5:36:2B:32 type ACL encrypt 0x00 +< ACL data: handle 12 flags 0x02 dlen 12 + L2CAP(s): Connect req: psm 1 scid 0x0040 +< HCI Command: Read Remote Supported Features (0x01|0x001b) plen 2 + handle 12 +> HCI Event: Command Status (0x0f) plen 4 + Read Remote Supported Features (0x01|0x001b) status 0x00 ncmd 1 +< HCI Command: Write Link Policy Settings (0x02|0x000d) plen 4 + handle 12 policy 0x0f + Link policy: RSWITCH HOLD SNIFF PARK +> HCI Event: Read Remote Supported Features (0x0b) plen 11 + status 0x00 handle 12 + Features: 0xbc 0x02 0x04 0x38 0x08 0x00 0x00 0x00 +> HCI Event: Command Complete (0x0e) plen 6 + Write Link Policy Settings (0x02|0x000d) ncmd 1 + status 0x00 handle 12 +< HCI Command: Remote Name Request (0x01|0x0019) plen 10 + bdaddr 00:1F:C5:36:2B:32 mode 2 clkoffset 0x0000 +> HCI Event: Command Status (0x0f) plen 4 + Remote Name Request (0x01|0x0019) status 0x00 ncmd 1 +> ACL data: handle 12 flags 0x02 dlen 16 + L2CAP(s): Connect rsp: dcid 0x0043 scid 0x0040 result 0 status 0 + Connection successful +< ACL data: handle 12 flags 0x02 dlen 12 + L2CAP(s): Config req: dcid 0x0043 flags 0x00 clen 0 +> HCI Event: Number of Completed Packets (0x13) plen 5 + handle 12 packets 2 +> ACL data: handle 12 flags 0x02 dlen 18 + L2CAP(s): Config rsp: scid 0x0040 flags 0x00 result 0 clen 4 + Success + MTU 185 +> ACL data: handle 12 flags 0x02 dlen 16 + L2CAP(s): Config req: dcid 0x0040 flags 0x00 clen 4 + MTU 185 +< ACL data: handle 12 flags 0x02 dlen 18 + L2CAP(s): Config rsp: scid 0x0043 flags 0x00 result 0 clen 4 + Success + MTU 185 +< ACL data: handle 12 flags 0x02 dlen 23 + L2CAP(d): cid 0x0043 len 19 [psm 1] + SDP SA Req: tid 0x0 len 0xe + handle 0x10001 + max 65535 + aid(s) 0x0000 - 0xffff + cont 00 +> HCI Event: Remote Name Req Complete (0x07) plen 255 + status 0x00 bdaddr 00:1F:C5:36:2B:32 name 'Nintendo RVL-CNT-01' +> HCI Event: Number of Completed Packets (0x13) plen 5 + handle 12 packets 2 +> ACL data: handle 12 flags 0x02 dlen 27 +> ACL data: handle 12 flags 0x01 dlen 27 +> ACL data: handle 12 flags 0x01 dlen 27 +> ACL data: handle 12 flags 0x01 dlen 24 + L2CAP(d): cid 0x0040 len 101 [psm 1] + SDP SA Rsp: tid 0x0 len 0x60 + count 93 + aid 0x0000 (SrvRecHndl) + uint 0x10001 + aid 0x0001 (SrvClassIDList) + < uuid-16 0x1200 (PNPInfo) > + aid 0x0004 (ProtocolDescList) + < < uuid-16 0x0100 (L2CAP) uint 0x1 > < + uuid-16 0x0001 (SDP) > > + aid 0x0005 (BrwGrpList) + < uuid-16 0x1002 (PubBrwsGrp) > + aid 0x0009 (BTProfileDescList) + < < uuid-16 0x1200 (PNPInfo) uint 0x100 > > + aid 0x0200 (VersionNumList) + uint 0x100 + aid 0x0201 (SrvDBState) + uint 0x57e + aid 0x0202 (unknown) + uint 0x306 + aid 0x0203 (unknown) + uint 0x600 + aid 0x0204 (unknown) + bool 0x1 + aid 0x0205 (unknown) + uint 0x2 + cont 00 +< ACL data: handle 12 flags 0x02 dlen 12 + L2CAP(s): Disconn req: dcid 0x0043 scid 0x0040 +> ACL data: handle 12 flags 0x02 dlen 12 + L2CAP(s): Disconn rsp: dcid 0x0043 scid 0x0040 +> HCI Event: Number of Completed Packets (0x13) plen 5 + handle 12 packets 1 +< HCI Command: Disconnect (0x01|0x0006) plen 3 + handle 12 reason 0x13 + Reason: Remote User Terminated Connection +> HCI Event: Command Status (0x0f) plen 4 + Disconnect (0x01|0x0006) status 0x00 ncmd 1 +> HCI Event: Disconn Complete (0x05) plen 4 + status 0x00 handle 12 reason 0x16 + Reason: Connection Terminated by Local Host diff --git a/docs/WiiMote/Dumps/WiiMote_AttribTree_0x10001_strip.bin b/docs/WiiMote/Dumps/WiiMote_AttribTree_0x10001_strip.bin new file mode 100644 index 0000000000..ecdd7e46e6 Binary files /dev/null and b/docs/WiiMote/Dumps/WiiMote_AttribTree_0x10001_strip.bin differ diff --git a/docs/WiiMote/Dumps/WiiMote_ServiceScan.bin b/docs/WiiMote/Dumps/WiiMote_ServiceScan.bin new file mode 100644 index 0000000000..517d256b01 Binary files /dev/null and b/docs/WiiMote/Dumps/WiiMote_ServiceScan.bin differ diff --git a/docs/WiiMote/Dumps/WiiMote_ServiceScan.txt b/docs/WiiMote/Dumps/WiiMote_ServiceScan.txt new file mode 100644 index 0000000000..26ef7de6f2 --- /dev/null +++ b/docs/WiiMote/Dumps/WiiMote_ServiceScan.txt @@ -0,0 +1,356 @@ +HCI sniffer - Bluetooth packet analyzer ver 1.40 +> ACL data: handle 12 flags 0x02 dlen 8 + L2CAP(d): cid 0x0041 len 4 [psm 0] + 0000: a1 30 00 10 .0.. +> ACL data: handle 12 flags 0x02 dlen 8 + L2CAP(d): cid 0x0041 len 4 [psm 0] + 0000: a1 30 00 00 .0.. +< HCI Command: Inquiry (0x01|0x0001) plen 5 + lap 0x9e8b33 len 8 num 0 +> HCI Event: Command Status (0x0f) plen 4 + Inquiry (0x01|0x0001) status 0x00 ncmd 1 +< HCI Command: Inquiry Cancel (0x01|0x0002) plen 0 +> HCI Event: Command Complete (0x0e) plen 4 + Inquiry Cancel (0x01|0x0002) ncmd 1 + status 0x00 +> ACL data: handle 12 flags 0x02 dlen 8 + L2CAP(d): cid 0x0041 len 4 [psm 0] + 0000: a1 30 00 10 .0.. +> ACL data: handle 12 flags 0x02 dlen 8 + L2CAP(d): cid 0x0041 len 4 [psm 0] + 0000: a1 30 00 00 .0.. +> ACL data: handle 12 flags 0x02 dlen 8 + L2CAP(d): cid 0x0041 len 4 [psm 0] + 0000: a1 30 00 10 .0.. +> ACL data: handle 12 flags 0x02 dlen 8 + L2CAP(d): cid 0x0041 len 4 [psm 0] + 0000: a1 30 00 00 .0.. +< HCI Command: Inquiry (0x01|0x0001) plen 5 + lap 0x9e8b33 len 8 num 0 +> HCI Event: Command Status (0x0f) plen 4 + Inquiry (0x01|0x0001) status 0x00 ncmd 1 +> ACL data: handle 12 flags 0x02 dlen 8 + L2CAP(d): cid 0x0041 len 4 [psm 0] + 0000: a1 30 00 10 .0.. +> ACL data: handle 12 flags 0x02 dlen 8 + L2CAP(d): cid 0x0041 len 4 [psm 0] + 0000: a1 30 00 00 .0.. +> ACL data: handle 12 flags 0x02 dlen 8 + L2CAP(d): cid 0x0041 len 4 [psm 0] + 0000: a1 30 00 10 .0.. +> ACL data: handle 12 flags 0x02 dlen 8 + L2CAP(d): cid 0x0041 len 4 [psm 0] + 0000: a1 30 00 00 .0.. +> ACL data: handle 12 flags 0x02 dlen 8 + L2CAP(d): cid 0x0041 len 4 [psm 0] + 0000: a1 30 00 10 .0.. +> ACL data: handle 12 flags 0x02 dlen 8 + L2CAP(d): cid 0x0041 len 4 [psm 0] + 0000: a1 30 00 00 .0.. +> ACL data: handle 12 flags 0x02 dlen 8 + L2CAP(d): cid 0x0041 len 4 [psm 0] + 0000: a1 30 10 00 .0.. +> HCI Event: Inquiry Complete (0x01) plen 1 + status 0x00 +> ACL data: handle 12 flags 0x02 dlen 8 + L2CAP(d): cid 0x0041 len 4 [psm 0] + 0000: a1 30 00 00 .0.. +> ACL data: handle 12 flags 0x02 dlen 8 + L2CAP(d): cid 0x0041 len 4 [psm 0] + 0000: a1 30 10 00 .0.. +> ACL data: handle 12 flags 0x02 dlen 8 + L2CAP(d): cid 0x0041 len 4 [psm 0] + 0000: a1 30 00 00 .0.. +< HCI Command: Create Connection (0x01|0x0005) plen 13 + bdaddr 00:1F:C5:36:2B:32 ptype 0xcc18 rswitch 0x01 clkoffset 0x0000 + Packet type: DM1 DM3 DM5 DH1 DH3 DH5 +> HCI Event: Command Status (0x0f) plen 4 + Create Connection (0x01|0x0005) status 0x00 ncmd 1 +< HCI Command: Create Connection Cancel (0x01|0x0008) plen 6 + bdaddr 00:1F:C5:36:2B:32 +> HCI Event: Command Complete (0x0e) plen 10 + Create Connection Cancel (0x01|0x0008) ncmd 1 + status 0x00 bdaddr 00:1F:C5:36:2B:32 +> HCI Event: Connect Complete (0x03) plen 11 + status 0x02 handle 12 bdaddr 00:1F:C5:36:2B:32 type ACL encrypt 0x00 + Error: Unknown Connection Identifier +< HCI Command: Create Connection (0x01|0x0005) plen 13 + bdaddr 00:1F:C5:36:2B:32 ptype 0xcc18 rswitch 0x01 clkoffset 0x0000 + Packet type: DM1 DM3 DM5 DH1 DH3 DH5 +> HCI Event: Command Status (0x0f) plen 4 + Create Connection (0x01|0x0005) status 0x00 ncmd 1 +> HCI Event: Connect Complete (0x03) plen 11 + status 0x00 handle 12 bdaddr 00:1F:C5:36:2B:32 type ACL encrypt 0x00 +< ACL data: handle 12 flags 0x02 dlen 12 + L2CAP(s): Connect req: psm 1 scid 0x0040 +< HCI Command: Read Remote Supported Features (0x01|0x001b) plen 2 + handle 12 +> HCI Event: Command Status (0x0f) plen 4 + Read Remote Supported Features (0x01|0x001b) status 0x00 ncmd 1 +< HCI Command: Write Link Policy Settings (0x02|0x000d) plen 4 + handle 12 policy 0x0f + Link policy: RSWITCH HOLD SNIFF PARK +> HCI Event: Read Remote Supported Features (0x0b) plen 11 + status 0x00 handle 12 + Features: 0xbc 0x02 0x04 0x38 0x08 0x00 0x00 0x00 +> HCI Event: Command Complete (0x0e) plen 6 + Write Link Policy Settings (0x02|0x000d) ncmd 1 + status 0x00 handle 12 +< HCI Command: Remote Name Request (0x01|0x0019) plen 10 + bdaddr 00:1F:C5:36:2B:32 mode 2 clkoffset 0x0000 +> HCI Event: Command Status (0x0f) plen 4 + Remote Name Request (0x01|0x0019) status 0x00 ncmd 1 +> ACL data: handle 12 flags 0x02 dlen 16 + L2CAP(s): Connect rsp: dcid 0x0043 scid 0x0040 result 0 status 0 + Connection successful +< ACL data: handle 12 flags 0x02 dlen 12 + L2CAP(s): Config req: dcid 0x0043 flags 0x00 clen 0 +> HCI Event: Number of Completed Packets (0x13) plen 5 + handle 12 packets 2 +> ACL data: handle 12 flags 0x02 dlen 18 + L2CAP(s): Config rsp: scid 0x0040 flags 0x00 result 0 clen 4 + Success + MTU 185 +> ACL data: handle 12 flags 0x02 dlen 16 + L2CAP(s): Config req: dcid 0x0040 flags 0x00 clen 4 + MTU 185 +< ACL data: handle 12 flags 0x02 dlen 18 + L2CAP(s): Config rsp: scid 0x0043 flags 0x00 result 0 clen 4 + Success + MTU 185 +< ACL data: handle 12 flags 0x02 dlen 23 + L2CAP(d): cid 0x0043 len 19 [psm 1] + SDP SA Req: tid 0x0 len 0xe + handle 0x10001 + max 65535 + aid(s) 0x0000 - 0xffff + cont 00 +> HCI Event: Remote Name Req Complete (0x07) plen 255 + status 0x00 bdaddr 00:1F:C5:36:2B:32 name 'Nintendo RVL-CNT-01' +> HCI Event: Number of Completed Packets (0x13) plen 5 + handle 12 packets 2 +> ACL data: handle 12 flags 0x02 dlen 27 +> ACL data: handle 12 flags 0x01 dlen 27 +> ACL data: handle 12 flags 0x01 dlen 27 +> ACL data: handle 12 flags 0x01 dlen 24 + L2CAP(d): cid 0x0040 len 101 [psm 1] + SDP SA Rsp: tid 0x0 len 0x60 + count 93 + aid 0x0000 (SrvRecHndl) + uint 0x10001 + aid 0x0001 (SrvClassIDList) + < uuid-16 0x1200 (PNPInfo) > + aid 0x0004 (ProtocolDescList) + < < uuid-16 0x0100 (L2CAP) uint 0x1 > < + uuid-16 0x0001 (SDP) > > + aid 0x0005 (BrwGrpList) + < uuid-16 0x1002 (PubBrwsGrp) > + aid 0x0009 (BTProfileDescList) + < < uuid-16 0x1200 (PNPInfo) uint 0x100 > > + aid 0x0200 (VersionNumList) + uint 0x100 + aid 0x0201 (SrvDBState) + uint 0x57e + aid 0x0202 (unknown) + uint 0x306 + aid 0x0203 (unknown) + uint 0x600 + aid 0x0204 (unknown) + bool 0x1 + aid 0x0205 (unknown) + uint 0x2 + cont 00 +< ACL data: handle 12 flags 0x02 dlen 12 + L2CAP(s): Disconn req: dcid 0x0043 scid 0x0040 +> ACL data: handle 12 flags 0x02 dlen 12 + L2CAP(s): Disconn rsp: dcid 0x0043 scid 0x0040 +> HCI Event: Number of Completed Packets (0x13) plen 5 + handle 12 packets 1 +< HCI Command: Disconnect (0x01|0x0006) plen 3 + handle 12 reason 0x13 + Reason: Remote User Terminated Connection +> HCI Event: Command Status (0x0f) plen 4 + Disconnect (0x01|0x0006) status 0x00 ncmd 1 +> HCI Event: Disconn Complete (0x05) plen 4 + status 0x00 handle 12 reason 0x16 + Reason: Connection Terminated by Local Host +< HCI Command: Create Connection (0x01|0x0005) plen 13 + bdaddr 00:1F:C5:36:2B:32 ptype 0xcc18 rswitch 0x01 clkoffset 0x0000 + Packet type: DM1 DM3 DM5 DH1 DH3 DH5 +> HCI Event: Command Status (0x0f) plen 4 + Create Connection (0x01|0x0005) status 0x00 ncmd 1 +> HCI Event: Connect Complete (0x03) plen 11 + status 0x00 handle 12 bdaddr 00:1F:C5:36:2B:32 type ACL encrypt 0x00 +< ACL data: handle 12 flags 0x02 dlen 12 + L2CAP(s): Connect req: psm 1 scid 0x0040 +< HCI Command: Read Remote Supported Features (0x01|0x001b) plen 2 + handle 12 +> HCI Event: Command Status (0x0f) plen 4 + Read Remote Supported Features (0x01|0x001b) status 0x00 ncmd 1 +< HCI Command: Write Link Policy Settings (0x02|0x000d) plen 4 + handle 12 policy 0x0f + Link policy: RSWITCH HOLD SNIFF PARK +> HCI Event: Read Remote Supported Features (0x0b) plen 11 + status 0x00 handle 12 + Features: 0xbc 0x02 0x04 0x38 0x08 0x00 0x00 0x00 +> HCI Event: Command Complete (0x0e) plen 6 + Write Link Policy Settings (0x02|0x000d) ncmd 1 + status 0x00 handle 12 +< HCI Command: Remote Name Request (0x01|0x0019) plen 10 + bdaddr 00:1F:C5:36:2B:32 mode 2 clkoffset 0x0000 +> HCI Event: Command Status (0x0f) plen 4 + Remote Name Request (0x01|0x0019) status 0x00 ncmd 1 +> ACL data: handle 12 flags 0x02 dlen 16 + L2CAP(s): Connect rsp: dcid 0x0045 scid 0x0040 result 0 status 0 + Connection successful +< ACL data: handle 12 flags 0x02 dlen 12 + L2CAP(s): Config req: dcid 0x0045 flags 0x00 clen 0 +> HCI Event: Number of Completed Packets (0x13) plen 5 + handle 12 packets 2 +> ACL data: handle 12 flags 0x02 dlen 18 + L2CAP(s): Config rsp: scid 0x0040 flags 0x00 result 0 clen 4 + Success + MTU 185 +> ACL data: handle 12 flags 0x02 dlen 16 + L2CAP(s): Config req: dcid 0x0040 flags 0x00 clen 4 + MTU 185 +< ACL data: handle 12 flags 0x02 dlen 18 + L2CAP(s): Config rsp: scid 0x0045 flags 0x00 result 0 clen 4 + Success + MTU 185 +< ACL data: handle 12 flags 0x02 dlen 24 + L2CAP(d): cid 0x0045 len 20 [psm 1] + SDP SSA Req: tid 0x0 len 0xf + pat uuid-16 0x1124 (HID) + max 65535 + aid(s) 0x0000 - 0xffff + cont 00 +> HCI Event: Remote Name Req Complete (0x07) plen 255 + status 0x00 bdaddr 00:1F:C5:36:2B:32 name 'Nintendo RVL-CNT-01' +> HCI Event: Number of Completed Packets (0x13) plen 5 + handle 12 packets 2 +> ACL data: handle 12 flags 0x02 dlen 27 +> ACL data: handle 12 flags 0x01 dlen 27 +> ACL data: handle 12 flags 0x01 dlen 27 +> ACL data: handle 12 flags 0x01 dlen 27 +> ACL data: handle 12 flags 0x01 dlen 24 + L2CAP(d): cid 0x0040 len 128 [psm 1] + SDP SSA Rsp: tid 0x0 len 0x7b + count 118 + cont 02 00 76 +< ACL data: handle 12 flags 0x02 dlen 26 + L2CAP(d): cid 0x0045 len 22 [psm 1] + SDP SSA Req: tid 0x1 len 0x11 + pat uuid-16 0x1124 (HID) + max 65535 + aid(s) 0x0000 - 0xffff + cont 02 00 76 +> ACL data: handle 12 flags 0x02 dlen 27 +> ACL data: handle 12 flags 0x01 dlen 27 +> ACL data: handle 12 flags 0x01 dlen 27 +> ACL data: handle 12 flags 0x01 dlen 27 +> ACL data: handle 12 flags 0x01 dlen 24 + L2CAP(d): cid 0x0040 len 128 [psm 1] + SDP SSA Rsp: tid 0x1 len 0x7b + count 118 + cont 02 00 EC +< ACL data: handle 12 flags 0x02 dlen 26 + L2CAP(d): cid 0x0045 len 22 [psm 1] + SDP SSA Req: tid 0x2 len 0x11 + pat uuid-16 0x1124 (HID) + max 65535 + aid(s) 0x0000 - 0xffff + cont 02 00 EC +> HCI Event: Number of Completed Packets (0x13) plen 5 + handle 12 packets 2 +> ACL data: handle 12 flags 0x02 dlen 27 +> ACL data: handle 12 flags 0x01 dlen 27 +> ACL data: handle 12 flags 0x01 dlen 27 +> ACL data: handle 12 flags 0x01 dlen 27 +> ACL data: handle 12 flags 0x01 dlen 24 + L2CAP(d): cid 0x0040 len 128 [psm 1] + SDP SSA Rsp: tid 0x2 len 0x7b + count 118 + cont 02 01 62 +< ACL data: handle 12 flags 0x02 dlen 26 + L2CAP(d): cid 0x0045 len 22 [psm 1] + SDP SSA Req: tid 0x3 len 0x11 + pat uuid-16 0x1124 (HID) + max 65535 + aid(s) 0x0000 - 0xffff + cont 02 01 62 +> ACL data: handle 12 flags 0x02 dlen 27 +> ACL data: handle 12 flags 0x01 dlen 27 +> ACL data: handle 12 flags 0x01 dlen 27 +> ACL data: handle 12 flags 0x01 dlen 27 +> ACL data: handle 12 flags 0x01 dlen 16 + L2CAP(d): cid 0x0040 len 120 [psm 1] + SDP SSA Rsp: tid 0x3 len 0x73 + count 112 + record #0 + aid 0x0000 (SrvRecHndl) + uint 0x10000 + aid 0x0001 (SrvClassIDList) + < uuid-16 0x1124 (HID) > + aid 0x0004 (ProtocolDescList) + < < uuid-16 0x0100 (L2CAP) uint 0x11 > < + uuid-16 0x0011 (HIDP) > > + aid 0x0005 (BrwGrpList) + < uuid-16 0x1002 (PubBrwsGrp) > + aid 0x0006 (LangBaseAttrIDList) + < uint 0x656e uint 0x6a uint 0x100 > + aid 0x0009 (BTProfileDescList) + < < uuid-16 0x1124 (HID) uint 0x100 > > + aid 0x000d (IconURL) + < < < uuid-16 0x0100 (L2CAP) uint 0x13 > < uuid-16 0x0011 (HIDP) > > > + aid 0x0100 (SrvName) + str "Nintendo RVL-CNT-01" + aid 0x0101 (SrvDesc) + str "Nintendo RVL-CNT-01" + aid 0x0102 (ProviderName) + str "Nintendo" + aid 0x0200 (VersionNumList) + uint 0x100 + aid 0x0201 (SrvDBState) + uint 0x111 + aid 0x0202 (unknown) + uint 0x4 + aid 0x0203 (unknown) + uint 0x33 + aid 0x0204 (unknown) + bool 0x0 + aid 0x0205 (unknown) + bool 0x1 + aid 0x0206 (unknown) + < < uint 0x22 str 05 01 09 05 a1 01 85 10 15 00 26 ff 00 75 08 95 01 06 00 ff 09 01 91 00 85 11 95 01 09 01 91 00 85 12 95 02 09 01 91 00 85 13 95 01 09 01 91 00 85 14 95 01 09 01 91 00 85 15 95 01 09 01 91 00 85 16 95 15 09 01 91 00 85 17 95 06 09 01 91 00 85 18 95 15 09 01 91 00 85 19 95 01 09 01 91 00 85 1a 95 01 09 01 91 00 85 20 95 06 09 01 81 00 85 21 95 15 09 01 81 00 85 22 95 04 09 01 81 00 85 30 95 02 09 01 81 00 85 31 95 05 09 01 81 00 85 32 95 0a 09 01 81 00 85 33 95 11 09 01 81 00 85 34 95 15 09 01 81 00 85 35 95 15 09 01 81 00 85 36 95 15 09 01 81 00 85 37 95 15 09 01 81 00 85 3d 95 15 09 01 81 00 85 3e 95 15 09 01 81 00 85 3f 95 15 09 01 81 00 c0 > > + aid 0x0207 (unknown) + < < uint 0x409 uint 0x100 > > + aid 0x0208 (unknown) + bool 0x0 + aid 0x0209 (unknown) + bool 0x1 + aid 0x020a (unknown) + bool 0x1 + aid 0x020b (unknown) + uint 0x100 + aid 0x020c (unknown) + uint 0xc80 + aid 0x020d (unknown) + bool 0x0 + aid 0x020e (unknown) + bool 0x0 + cont 00 +< ACL data: handle 12 flags 0x02 dlen 12 + L2CAP(s): Disconn req: dcid 0x0045 scid 0x0040 +> HCI Event: Number of Completed Packets (0x13) plen 5 + handle 12 packets 2 +> ACL data: handle 12 flags 0x02 dlen 12 + L2CAP(s): Disconn rsp: dcid 0x0045 scid 0x0040 +< HCI Command: Disconnect (0x01|0x0006) plen 3 + handle 12 reason 0x13 + Reason: Remote User Terminated Connection +> HCI Event: Command Status (0x0f) plen 4 + Disconnect (0x01|0x0006) status 0x00 ncmd 1 +> HCI Event: Disconn Complete (0x05) plen 4 + status 0x00 handle 12 reason 0x16 + Reason: Connection Terminated by Local Host diff --git a/docs/WiiMote/HID_SPEC_V10.rar b/docs/WiiMote/HID_SPEC_V10.rar new file mode 100644 index 0000000000..f1f10b9ab0 Binary files /dev/null and b/docs/WiiMote/HID_SPEC_V10.rar differ