Merge pull request #754 from FioraAeterna/immediateopt
x64Emitter: optimize immediate sizes
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commit
b8d126c101
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@ -18,6 +18,7 @@ struct NormalOpDef
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u8 toRm8, toRm32, fromRm8, fromRm32, imm8, imm32, simm8, ext;
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u8 toRm8, toRm32, fromRm8, fromRm32, imm8, imm32, simm8, ext;
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};
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};
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// 0xCC is code for invalid combination of immediates
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static const NormalOpDef nops[11] =
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static const NormalOpDef nops[11] =
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{
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{
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{0x00, 0x01, 0x02, 0x03, 0x80, 0x81, 0x83, 0}, //ADD
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{0x00, 0x01, 0x02, 0x03, 0x80, 0x81, 0x83, 0}, //ADD
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@ -1057,8 +1058,20 @@ void OpArg::WriteNormalOp(XEmitter *emit, bool toRM, NormalOp op, const OpArg &o
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(operand.scale == SCALE_IMM32 && bits == 32) ||
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(operand.scale == SCALE_IMM32 && bits == 32) ||
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(operand.scale == SCALE_IMM32 && bits == 64))
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(operand.scale == SCALE_IMM32 && bits == 64))
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{
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{
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emit->Write8(nops[op].imm32);
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// Try to save immediate size if we can, but first check to see
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immToWrite = bits == 16 ? 16 : 32;
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// if the instruction supports simm8.
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if (nops[op].simm8 != 0xCC &&
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((operand.scale == SCALE_IMM16 && (s16)operand.offset == (s8)operand.offset) ||
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(operand.scale == SCALE_IMM32 && (s32)operand.offset == (s8)operand.offset)))
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{
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emit->Write8(nops[op].simm8);
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immToWrite = 8;
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}
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else
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{
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emit->Write8(nops[op].imm32);
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immToWrite = bits == 16 ? 16 : 32;
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}
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}
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}
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else if ((operand.scale == SCALE_IMM8 && bits == 16) ||
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else if ((operand.scale == SCALE_IMM8 && bits == 16) ||
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(operand.scale == SCALE_IMM8 && bits == 32) ||
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(operand.scale == SCALE_IMM8 && bits == 32) ||
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@ -1182,7 +1195,9 @@ void XEmitter::IMUL(int bits, X64Reg regOp, OpArg a1, OpArg a2)
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Write8(0x66);
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Write8(0x66);
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a1.WriteRex(this, bits, bits, regOp);
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a1.WriteRex(this, bits, bits, regOp);
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if (a2.GetImmBits() == 8) {
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if (a2.GetImmBits() == 8 ||
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(a2.GetImmBits() == 16 && (s8)a2.offset == (s16)a2.offset) ||
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(a2.GetImmBits() == 32 && (s8)a2.offset == (s32)a2.offset)) {
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Write8(0x6B);
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Write8(0x6B);
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a1.WriteRest(this, 1, regOp);
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a1.WriteRest(this, 1, regOp);
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Write8((u8)a2.offset);
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Write8((u8)a2.offset);
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