From b8cca8f598b81c9c6976785cc1b81b55f08893ca Mon Sep 17 00:00:00 2001 From: Pokechu22 Date: Tue, 15 Feb 2022 21:05:48 -0800 Subject: [PATCH] ProcessorInterface: Implement PI_FIFO_RESET Fixes unknown opcodes 0x0f and 0xff when resetting titles, e.g. https://bugs.dolphin-emu.org/issues/12492 --- Source/Core/Core/HW/ProcessorInterface.cpp | 6 +++++- Source/Core/Core/HW/ProcessorInterface.h | 2 +- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/Source/Core/Core/HW/ProcessorInterface.cpp b/Source/Core/Core/HW/ProcessorInterface.cpp index 1e49f6e2dc..795a169205 100644 --- a/Source/Core/Core/HW/ProcessorInterface.cpp +++ b/Source/Core/Core/HW/ProcessorInterface.cpp @@ -18,6 +18,7 @@ #include "Core/IOS/IOS.h" #include "Core/IOS/STM/STM.h" #include "Core/PowerPC/PowerPC.h" +#include "VideoCommon/Fifo.h" namespace ProcessorInterface { @@ -111,7 +112,10 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base) mmio->Register(base | PI_FIFO_RESET, MMIO::InvalidRead(), MMIO::ComplexWrite([](u32, u32 val) { - WARN_LOG_FMT(PROCESSORINTERFACE, "Fifo reset ({:08x})", val); + // Used by GXAbortFrame + INFO_LOG_FMT(PROCESSORINTERFACE, "Wrote PI_FIFO_RESET: {:08x}", val); + if ((val & 1) != 0) + Fifo::ResetVideoBuffer(); })); mmio->Register(base | PI_RESET_CODE, MMIO::ComplexRead([](u32) { diff --git a/Source/Core/Core/HW/ProcessorInterface.h b/Source/Core/Core/HW/ProcessorInterface.h index 7b536244e3..0403b6d0a3 100644 --- a/Source/Core/Core/HW/ProcessorInterface.h +++ b/Source/Core/Core/HW/ProcessorInterface.h @@ -46,7 +46,7 @@ enum PI_FIFO_BASE = 0x0C, PI_FIFO_END = 0x10, PI_FIFO_WPTR = 0x14, - PI_FIFO_RESET = 0x18, // ??? - GXAbortFrame writes to it + PI_FIFO_RESET = 0x18, // Used by GXAbortFrame PI_RESET_CODE = 0x24, PI_FLIPPER_REV = 0x2C, PI_FLIPPER_UNK = 0x30 // BS1 writes 0x0245248A to it - prolly some bootstrap thing