DSPCore: Convert defines over to enums
This commit is contained in:
Lioncash
parent
e076de137b
commit
b730ad4406
|
|
@ -14,154 +14,194 @@
|
|||
#include "Core/DSP/DSPCaptureLogger.h"
|
||||
#include "Core/DSP/DSPEmitter.h"
|
||||
|
||||
#define DSP_IRAM_BYTE_SIZE 0x2000
|
||||
#define DSP_IRAM_SIZE 0x1000
|
||||
#define DSP_IRAM_MASK 0x0fff
|
||||
enum : u32
|
||||
{
|
||||
DSP_IRAM_BYTE_SIZE = 0x2000,
|
||||
DSP_IRAM_SIZE = 0x1000,
|
||||
DSP_IRAM_MASK = 0x0fff
|
||||
};
|
||||
|
||||
#define DSP_IROM_BYTE_SIZE 0x2000
|
||||
#define DSP_IROM_SIZE 0x1000
|
||||
#define DSP_IROM_MASK 0x0fff
|
||||
enum : u32
|
||||
{
|
||||
DSP_IROM_BYTE_SIZE = 0x2000,
|
||||
DSP_IROM_SIZE = 0x1000,
|
||||
DSP_IROM_MASK = 0x0fff
|
||||
};
|
||||
|
||||
#define DSP_DRAM_BYTE_SIZE 0x2000
|
||||
#define DSP_DRAM_SIZE 0x1000
|
||||
#define DSP_DRAM_MASK 0x0fff
|
||||
enum : u32
|
||||
{
|
||||
DSP_DRAM_BYTE_SIZE = 0x2000,
|
||||
DSP_DRAM_SIZE = 0x1000,
|
||||
DSP_DRAM_MASK = 0x0fff
|
||||
};
|
||||
|
||||
#define DSP_COEF_BYTE_SIZE 0x1000
|
||||
#define DSP_COEF_SIZE 0x800
|
||||
#define DSP_COEF_MASK 0x7ff
|
||||
enum : u32
|
||||
{
|
||||
DSP_COEF_BYTE_SIZE = 0x1000,
|
||||
DSP_COEF_SIZE = 0x800,
|
||||
DSP_COEF_MASK = 0x7ff
|
||||
};
|
||||
|
||||
#define DSP_RESET_VECTOR 0x8000
|
||||
enum : u16
|
||||
{
|
||||
DSP_RESET_VECTOR = 0x8000
|
||||
};
|
||||
|
||||
#define DSP_STACK_DEPTH 0x20
|
||||
#define DSP_STACK_MASK 0x1f
|
||||
|
||||
#define DSP_CR_IMEM 2
|
||||
#define DSP_CR_DMEM 0
|
||||
#define DSP_CR_TO_CPU 1
|
||||
#define DSP_CR_FROM_CPU 0
|
||||
enum : u8
|
||||
{
|
||||
DSP_STACK_DEPTH = 0x20,
|
||||
DSP_STACK_MASK = 0x1f
|
||||
};
|
||||
|
||||
enum : u32
|
||||
{
|
||||
DSP_CR_IMEM = 2,
|
||||
DSP_CR_DMEM = 0,
|
||||
DSP_CR_TO_CPU = 1,
|
||||
DSP_CR_FROM_CPU = 0
|
||||
};
|
||||
|
||||
// Register table taken from libasnd
|
||||
#define DSP_REG_AR0 0x00 // address registers
|
||||
#define DSP_REG_AR1 0x01
|
||||
#define DSP_REG_AR2 0x02
|
||||
#define DSP_REG_AR3 0x03
|
||||
enum : int
|
||||
{
|
||||
// Address registers
|
||||
DSP_REG_AR0 = 0x00,
|
||||
DSP_REG_AR1 = 0x01,
|
||||
DSP_REG_AR2 = 0x02,
|
||||
DSP_REG_AR3 = 0x03,
|
||||
|
||||
#define DSP_REG_IX0 0x04 // indexing registers (actually, mostly used as increments)
|
||||
#define DSP_REG_IX1 0x05
|
||||
#define DSP_REG_IX2 0x06
|
||||
#define DSP_REG_IX3 0x07
|
||||
// Indexing registers (actually, mostly used as increments)
|
||||
DSP_REG_IX0 = 0x04,
|
||||
DSP_REG_IX1 = 0x05,
|
||||
DSP_REG_IX2 = 0x06,
|
||||
DSP_REG_IX3 = 0x07,
|
||||
|
||||
#define DSP_REG_WR0 0x08 // address wrapping registers. should be initialized to 0xFFFF if not used.
|
||||
#define DSP_REG_WR1 0x09
|
||||
#define DSP_REG_WR2 0x0a
|
||||
#define DSP_REG_WR3 0x0b
|
||||
// Address wrapping registers. should be initialized to 0xFFFF if not used.
|
||||
DSP_REG_WR0 = 0x08,
|
||||
DSP_REG_WR1 = 0x09,
|
||||
DSP_REG_WR2 = 0x0a,
|
||||
DSP_REG_WR3 = 0x0b,
|
||||
|
||||
#define DSP_REG_ST0 0x0c // stacks.
|
||||
#define DSP_REG_ST1 0x0d
|
||||
#define DSP_REG_ST2 0x0e
|
||||
#define DSP_REG_ST3 0x0f
|
||||
// Stacks
|
||||
DSP_REG_ST0 = 0x0c,
|
||||
DSP_REG_ST1 = 0x0d,
|
||||
DSP_REG_ST2 = 0x0e,
|
||||
DSP_REG_ST3 = 0x0f,
|
||||
|
||||
#define DSP_REG_CR 0x12 // Seems to be the top 8 bits of LRS/SRS.
|
||||
#define DSP_REG_SR 0x13
|
||||
// Seems to be the top 8 bits of LRS/SRS.
|
||||
DSP_REG_CR = 0x12,
|
||||
DSP_REG_SR = 0x13,
|
||||
|
||||
#define DSP_REG_PRODL 0x14 // product.
|
||||
#define DSP_REG_PRODM 0x15
|
||||
#define DSP_REG_PRODH 0x16
|
||||
#define DSP_REG_PRODM2 0x17
|
||||
// Product
|
||||
DSP_REG_PRODL = 0x14,
|
||||
DSP_REG_PRODM = 0x15,
|
||||
DSP_REG_PRODH = 0x16,
|
||||
DSP_REG_PRODM2 = 0x17,
|
||||
|
||||
#define DSP_REG_AXL0 0x18
|
||||
#define DSP_REG_AXL1 0x19
|
||||
#define DSP_REG_AXH0 0x1a
|
||||
#define DSP_REG_AXH1 0x1b
|
||||
DSP_REG_AXL0 = 0x18,
|
||||
DSP_REG_AXL1 = 0x19,
|
||||
DSP_REG_AXH0 = 0x1a,
|
||||
DSP_REG_AXH1 = 0x1b,
|
||||
|
||||
#define DSP_REG_ACC0 0x1c // accumulator (global)
|
||||
#define DSP_REG_ACC1 0x1d
|
||||
// Accumulator (global)
|
||||
DSP_REG_ACC0 = 0x1c,
|
||||
DSP_REG_ACC1 = 0x1d,
|
||||
|
||||
#define DSP_REG_ACL0 0x1c // Low accumulator
|
||||
#define DSP_REG_ACL1 0x1d
|
||||
#define DSP_REG_ACM0 0x1e // Mid accumulator
|
||||
#define DSP_REG_ACM1 0x1f
|
||||
#define DSP_REG_ACH0 0x10 // Sign extended 8 bit register 0
|
||||
#define DSP_REG_ACH1 0x11 // Sign extended 8 bit register 1
|
||||
DSP_REG_ACL0 = 0x1c, // Low accumulator
|
||||
DSP_REG_ACL1 = 0x1d,
|
||||
DSP_REG_ACM0 = 0x1e, // Mid accumulator
|
||||
DSP_REG_ACM1 = 0x1f,
|
||||
DSP_REG_ACH0 = 0x10, // Sign extended 8 bit register 0
|
||||
DSP_REG_ACH1 = 0x11 // Sign extended 8 bit register 1
|
||||
};
|
||||
|
||||
// Hardware registers address
|
||||
enum : u32
|
||||
{
|
||||
DSP_COEF_A1_0 = 0xa0,
|
||||
|
||||
#define DSP_COEF_A1_0 0xa0
|
||||
DSP_DSCR = 0xc9, // DSP DMA Control Reg
|
||||
DSP_DSPA = 0xcd, // DSP DMA Address (DSP)
|
||||
DSP_DSBL = 0xcb, // DSP DMA Block Length
|
||||
DSP_DSMAH = 0xce, // DSP DMA Address High (External)
|
||||
DSP_DSMAL = 0xcf, // DSP DMA Address Low (External)
|
||||
|
||||
#define DSP_DSCR 0xc9 // DSP DMA Control Reg
|
||||
#define DSP_DSPA 0xcd // DSP DMA Address (DSP)
|
||||
#define DSP_DSBL 0xcb // DSP DMA Block Length
|
||||
#define DSP_DSMAH 0xce // DSP DMA Address High (External)
|
||||
#define DSP_DSMAL 0xcf // DSP DMA Address Low (External)
|
||||
DSP_FORMAT = 0xd1, // Sample format
|
||||
DSP_ACUNK = 0xd2, // Set to 3 on my dumps
|
||||
DSP_ACDATA1 = 0xd3, // Used only by Zelda ucodes
|
||||
DSP_ACSAH = 0xd4, // Start of loop
|
||||
DSP_ACSAL = 0xd5,
|
||||
DSP_ACEAH = 0xd6, // End of sample (and loop)
|
||||
DSP_ACEAL = 0xd7,
|
||||
DSP_ACCAH = 0xd8, // Current playback position
|
||||
DSP_ACCAL = 0xd9,
|
||||
DSP_PRED_SCALE = 0xda, // ADPCM predictor and scale
|
||||
DSP_YN1 = 0xdb,
|
||||
DSP_YN2 = 0xdc,
|
||||
DSP_ACCELERATOR = 0xdd, // ADPCM accelerator read. Used by AX.
|
||||
DSP_GAIN = 0xde,
|
||||
DSP_ACUNK2 = 0xdf, // Set to 0xc on my dumps
|
||||
|
||||
#define DSP_FORMAT 0xd1 // Sample format
|
||||
#define DSP_ACUNK 0xd2 // Set to 3 on my dumps
|
||||
#define DSP_ACDATA1 0xd3 // used only by Zelda ucodes
|
||||
#define DSP_ACSAH 0xd4 // Start of loop
|
||||
#define DSP_ACSAL 0xd5
|
||||
#define DSP_ACEAH 0xd6 // End of sample (and loop)
|
||||
#define DSP_ACEAL 0xd7
|
||||
#define DSP_ACCAH 0xd8 // Current playback position
|
||||
#define DSP_ACCAL 0xd9
|
||||
#define DSP_PRED_SCALE 0xda // ADPCM predictor and scale
|
||||
#define DSP_YN1 0xdb
|
||||
#define DSP_YN2 0xdc
|
||||
#define DSP_ACCELERATOR 0xdd // ADPCM accelerator read. Used by AX.
|
||||
#define DSP_GAIN 0xde
|
||||
#define DSP_ACUNK2 0xdf // Set to 0xc on my dumps
|
||||
DSP_AMDM = 0xef, // ARAM DMA Request Mask 0: DMA with ARAM unmasked 1: masked
|
||||
|
||||
#define DSP_AMDM 0xef // ARAM DMA Request Mask 0: DMA with ARAM unmasked 1: masked
|
||||
|
||||
#define DSP_DIRQ 0xfb // DSP Irq Rest
|
||||
#define DSP_DMBH 0xfc // DSP Mailbox H
|
||||
#define DSP_DMBL 0xfd // DSP Mailbox L
|
||||
#define DSP_CMBH 0xfe // CPU Mailbox H
|
||||
#define DSP_CMBL 0xff // CPU Mailbox L
|
||||
|
||||
#define DMA_TO_DSP 0
|
||||
#define DMA_TO_CPU 1
|
||||
DSP_DIRQ = 0xfb, // DSP Irq Rest
|
||||
DSP_DMBH = 0xfc, // DSP Mailbox H
|
||||
DSP_DMBL = 0xfd, // DSP Mailbox L
|
||||
DSP_CMBH = 0xfe, // CPU Mailbox H
|
||||
DSP_CMBL = 0xff // CPU Mailbox L
|
||||
};
|
||||
|
||||
// Stacks
|
||||
#define DSP_STACK_C 0
|
||||
#define DSP_STACK_D 1
|
||||
enum : int
|
||||
{
|
||||
DSP_STACK_C,
|
||||
DSP_STACK_D
|
||||
};
|
||||
|
||||
// cr (Not g_dsp.r[CR]) bits
|
||||
// See HW/DSP.cpp.
|
||||
#define CR_EXTERNAL_INT 0x0002
|
||||
#define CR_HALT 0x0004
|
||||
#define CR_INIT 0x0400
|
||||
|
||||
enum : u32
|
||||
{
|
||||
CR_EXTERNAL_INT = 0x0002,
|
||||
CR_HALT = 0x0004,
|
||||
CR_INIT = 0x0400
|
||||
};
|
||||
|
||||
// SR bits
|
||||
#define SR_CARRY 0x0001
|
||||
#define SR_OVERFLOW 0x0002
|
||||
#define SR_ARITH_ZERO 0x0004
|
||||
#define SR_SIGN 0x0008
|
||||
#define SR_OVER_S32 0x0010 // set when there was mod/tst/cmp on accu and result is over s32
|
||||
#define SR_TOP2BITS 0x0020 // if the upper (ac?.m/ax?.h) 2 bits are equal
|
||||
#define SR_LOGIC_ZERO 0x0040
|
||||
#define SR_OVERFLOW_STICKY 0x0080 // set at the same time as 0x2 (under same conditions) - but not cleared the same
|
||||
#define SR_100 0x0100 // unknown
|
||||
#define SR_INT_ENABLE 0x0200 // Not 100% sure but duddie says so. This should replace the hack, if so.
|
||||
#define SR_400 0x0400 // unknown
|
||||
#define SR_EXT_INT_ENABLE 0x0800 // Appears in zelda - seems to disable external interrupts
|
||||
#define SR_1000 0x1000 // unknown
|
||||
#define SR_MUL_MODIFY 0x2000 // 1 = normal. 0 = x2 (M0, M2) (Free mul by 2)
|
||||
#define SR_40_MODE_BIT 0x4000 // 0 = "16", 1 = "40" (SET16, SET40) Controls sign extension when loading mid accums and data saturation for stores from mid accums.
|
||||
#define SR_MUL_UNSIGNED 0x8000 // 0 = normal. 1 = unsigned (CLR15, SET15) If set, treats ax?.l as unsigned (MULX family only).
|
||||
enum : u16
|
||||
{
|
||||
SR_CARRY = 0x0001,
|
||||
SR_OVERFLOW = 0x0002,
|
||||
SR_ARITH_ZERO = 0x0004,
|
||||
SR_SIGN = 0x0008,
|
||||
SR_OVER_S32 = 0x0010, // Set when there was mod/tst/cmp on accu and result is over s32
|
||||
SR_TOP2BITS = 0x0020, // If the upper (ac?.m/ax?.h) 2 bits are equal
|
||||
SR_LOGIC_ZERO = 0x0040,
|
||||
SR_OVERFLOW_STICKY = 0x0080, // Set at the same time as 0x2 (under same conditions) - but not cleared the same
|
||||
SR_100 = 0x0100, // Unknown
|
||||
SR_INT_ENABLE = 0x0200, // Not 100% sure but duddie says so. This should replace the hack, if so.
|
||||
SR_400 = 0x0400, // Unknown
|
||||
SR_EXT_INT_ENABLE = 0x0800, // Appears in zelda - seems to disable external interrupts
|
||||
SR_1000 = 0x1000, // Unknown
|
||||
SR_MUL_MODIFY = 0x2000, // 1 = normal. 0 = x2 (M0, M2) (Free mul by 2)
|
||||
SR_40_MODE_BIT = 0x4000, // 0 = "16", 1 = "40" (SET16, SET40) Controls sign extension when loading mid accums and data saturation for stores from mid accums.
|
||||
SR_MUL_UNSIGNED = 0x8000, // 0 = normal. 1 = unsigned (CLR15, SET15) If set, treats ax?.l as unsigned (MULX family only).
|
||||
|
||||
// This should be the bits affected by CMP. Does not include logic zero.
|
||||
#define SR_CMP_MASK 0x3f
|
||||
// This should be the bits affected by CMP. Does not include logic zero.
|
||||
SR_CMP_MASK = 0x3f
|
||||
};
|
||||
|
||||
// exceptions vector
|
||||
#define EXP_STOVF 1 // 0x0002 stack under/over flow
|
||||
#define EXP_2 2 // 0x0004
|
||||
#define EXP_3 3 // 0x0006
|
||||
#define EXP_4 4 // 0x0008
|
||||
#define EXP_ACCOV 5 // 0x000a accelerator address overflow
|
||||
#define EXP_6 6 // 0x000c
|
||||
#define EXP_INT 7 // 0x000e external int (message from CPU)
|
||||
// Exception vectors
|
||||
enum : int
|
||||
{
|
||||
EXP_STOVF = 1, // 0x0002 stack under/over flow
|
||||
EXP_2 = 2, // 0x0004
|
||||
EXP_3 = 3, // 0x0006
|
||||
EXP_4 = 4, // 0x0008
|
||||
EXP_ACCOV = 5, // 0x000a accelerator address overflow
|
||||
EXP_6 = 6, // 0x000c
|
||||
EXP_INT = 7 // 0x000e external int (message from CPU)
|
||||
};
|
||||
|
||||
struct DSP_Regs
|
||||
{
|
||||
|
|
|
|||
|
|
@ -1331,7 +1331,7 @@ void GetSettings()
|
|||
|
||||
file_irom.ReadArray(irom.data(), DSP_IROM_SIZE);
|
||||
file_irom.Close();
|
||||
for (int i = 0; i < DSP_IROM_SIZE; ++i)
|
||||
for (u32 i = 0; i < DSP_IROM_SIZE; ++i)
|
||||
irom[i] = Common::swap16(irom[i]);
|
||||
|
||||
std::vector<u16> coef(DSP_COEF_SIZE);
|
||||
|
|
@ -1339,7 +1339,7 @@ void GetSettings()
|
|||
|
||||
file_coef.ReadArray(coef.data(), DSP_COEF_SIZE);
|
||||
file_coef.Close();
|
||||
for (int i = 0; i < DSP_COEF_SIZE; ++i)
|
||||
for (u32 i = 0; i < DSP_COEF_SIZE; ++i)
|
||||
coef[i] = Common::swap16(coef[i]);
|
||||
s_DSPiromHash = HashAdler32((u8*)irom.data(), DSP_IROM_BYTE_SIZE);
|
||||
s_DSPcoefHash = HashAdler32((u8*)coef.data(), DSP_COEF_BYTE_SIZE);
|
||||
|
|
|
|||
Loading…
Reference in New Issue