Add BitSet and, as a test, convert some JitRegCache stuff to it.
This is a higher level, more concise wrapper for bitsets which supports efficiently counting and iterating over set bits. It's similar to std::bitset, but the latter does not support efficient iteration (and at least in libc++, the count algorithm is subpar, not that it really matters). The converted uses include both bitsets and, notably, considerably less efficient regular arrays (for in/out registers in PPCAnalyst). Unfortunately, this may slightly pessimize unoptimized builds.
This commit is contained in:
comex
parent
e51676fdf1
commit
b6a7438053
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@ -0,0 +1,156 @@
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// This file is under the public domain.
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#pragma once
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#include <initializer_list>
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#include <type_traits>
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#include "CommonTypes.h"
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// Helper functions:
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#ifdef _WIN32
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template <typename T>
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static inline int CountSetBits(T v)
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{
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// from https://graphics.stanford.edu/~seander/bithacks.html
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// GCC has this built in, but MSVC's intrinsic will only emit the actual
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// POPCNT instruction, which we're not depending on
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v = v - ((v >> 1) & (T)~(T)0/3);
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v = (v & (T)~(T)0/15*3) + ((v >> 2) & (T)~(T)0/15*3);
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v = (v + (v >> 4)) & (T)~(T)0/255*15;
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return (T)(v * ((T)~(T)0/255)) >> (sizeof(T) - 1) * 8;
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}
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static inline int LeastSignificantSetBit(u32 val)
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{
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unsigned long index;
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_BitScanForward(&index, val);
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return (int)index;
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}
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static inline int LeastSignificantSetBit(u64 val)
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{
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unsigned long index;
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_BitScanForward64(&index, val);
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return (int)index;
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}
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#else
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static inline int CountSetBits(u32 val) { return __builtin_popcount(val); }
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static inline int CountSetBits(u64 val) { return __builtin_popcountll(val); }
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static inline int LeastSignificantSetBit(u32 val) { return __builtin_ctz(val); }
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static inline int LeastSignificantSetBit(u64 val) { return __builtin_ctzll(val); }
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#endif
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// Similar to std::bitset, this is a class which encapsulates a bitset, i.e.
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// using the set bits of an integer to represent a set of integers. Like that
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// class, it acts like an array of bools:
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// BitSet32 bs; // use BitSet{32,64} instead of the template directly
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// bs[1] = true;
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// but also like the underlying integer ([0] = least significant bit):
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// BitSet32 bs2 = ...;
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// bs = (bs ^ bs2) & BitSet32(0xffff);
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// The following additional functionality is provided:
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// - Construction using an initializer list.
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// BitSet bs { 1, 2, 4, 8 };
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// - Efficiently iterating through the set bits:
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// for (int i : bs)
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// [i is the *index* of a set bit]
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// (This uses the appropriate CPU instruction to find the next set bit in one
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// operation.)
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// - Counting set bits using .Count() - see comment on that method.
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// TODO: use constexpr when MSVC gets out of the Dark Ages
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template <typename IntTy>
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class BitSet
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{
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static_assert(!std::is_signed<IntTy>::value, "BitSet should not be used with signed types");
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public:
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// A reference to a particular bit, returned from operator[].
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class Ref
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{
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public:
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Ref(Ref&& other) : m_bs(other.m_bs), m_mask(other.m_mask) {}
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Ref(BitSet* bs, IntTy mask) : m_bs(bs), m_mask(mask) {}
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operator bool() const { return (m_bs->m_val & m_mask) != 0; }
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bool operator=(bool set)
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{
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m_bs->m_val = (m_bs->m_val & ~m_mask) | (set ? m_mask : 0);
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return set;
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}
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private:
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BitSet* m_bs;
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IntTy m_mask;
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};
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// A STL-like iterator is required to be able to use range-based for loops.
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class Iterator
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{
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public:
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Iterator(const Iterator& other) : m_val(other.m_val), m_bit(other.m_bit) {}
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Iterator(IntTy val, int bit) : m_val(val), m_bit(bit) {}
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Iterator& operator=(Iterator other) { new (this) Iterator(other); return *this; }
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int operator*() { return m_bit; }
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Iterator& operator++()
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{
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if (m_val == 0)
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{
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m_bit = -1;
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}
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else
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{
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int bit = LeastSignificantSetBit(m_val);
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m_val &= ~(1 << bit);
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m_bit = bit;
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}
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return *this;
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}
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Iterator operator++(int _)
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{
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Iterator other(*this);
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++*this;
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return other;
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}
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bool operator==(Iterator other) const { return m_bit == other.m_bit; }
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bool operator!=(Iterator other) const { return m_bit != other.m_bit; }
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private:
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IntTy m_val;
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int m_bit;
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};
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BitSet() : m_val(0) {}
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explicit BitSet(IntTy val) : m_val(val) {}
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BitSet(std::initializer_list<int> init)
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{
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m_val = 0;
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for (int bit : init)
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m_val |= (IntTy)1 << bit;
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}
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Ref operator[](size_t bit) { return Ref(this, (IntTy)1 << bit); }
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const Ref operator[](size_t bit) const { return (*const_cast<BitSet*>(this))[bit]; }
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bool operator==(BitSet other) const { return m_val == other.m_val; }
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bool operator!=(BitSet other) const { return m_val != other.m_val; }
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BitSet operator|(BitSet other) const { return BitSet(m_val | other.m_val); }
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BitSet operator&(BitSet other) const { return BitSet(m_val & other.m_val); }
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BitSet operator^(BitSet other) const { return BitSet(m_val ^ other.m_val); }
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BitSet operator~() const { return BitSet(~m_val); }
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BitSet& operator|=(BitSet other) { return *this = *this | other; }
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BitSet& operator&=(BitSet other) { return *this = *this & other; }
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BitSet& operator^=(BitSet other) { return *this = *this ^ other; }
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operator u32() = delete;
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operator bool() { return m_val != 0; }
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// Warning: Even though on modern CPUs this is a single fast instruction,
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// Dolphin's official builds do not currently assume POPCNT support on x86,
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// so slower explicit bit twiddling is generated. Still should generally
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// be faster than a loop.
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unsigned int Count() const { return CountSetBits(m_val); }
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Iterator begin() const { Iterator it(m_val, 0); return ++it; }
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Iterator end() const { return Iterator(m_val, -1); }
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IntTy m_val;
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};
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typedef BitSet<u32> BitSet32;
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typedef BitSet<u64> BitSet64;
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@ -39,6 +39,7 @@
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<ClInclude Include="Atomic_GCC.h" />
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<ClInclude Include="Atomic_Win32.h" />
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<ClInclude Include="BitField.h" />
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<ClInclude Include="BitSet.h" />
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<ClInclude Include="BreakPoints.h" />
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<ClInclude Include="CDUtils.h" />
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<ClInclude Include="ChunkFile.h" />
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@ -13,6 +13,7 @@
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<ClInclude Include="Atomic_GCC.h" />
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<ClInclude Include="Atomic_Win32.h" />
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<ClInclude Include="BitField.h" />
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<ClInclude Include="BitSet.h" />
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<ClInclude Include="BreakPoints.h" />
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<ClInclude Include="CDUtils.h" />
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<ClInclude Include="ChunkFile.h" />
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@ -736,29 +736,28 @@ const u8* Jit64::DoJit(u32 em_address, PPCAnalyst::CodeBuffer *code_buf, JitBloc
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// output, which needs to be bound in the actual instruction compilation.
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// TODO: make this smarter in the case that we're actually register-starved, i.e.
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// prioritize the more important registers.
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for (int k = 0; k < 3 && gpr.NumFreeRegisters() >= 2; k++)
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for (int reg : ops[i].regsIn)
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{
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int reg = ops[i].regsIn[k];
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if (reg >= 0 && (ops[i].gprInReg & (1 << reg)) && !gpr.R(reg).IsImm())
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if (gpr.NumFreeRegisters() < 2)
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break;
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if (ops[i].gprInReg[reg] && !gpr.R(reg).IsImm())
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gpr.BindToRegister(reg, true, false);
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}
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for (int k = 0; k < 4 && fpr.NumFreeRegisters() >= 2; k++)
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for (int reg : ops[i].regsOut)
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{
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int reg = ops[i].fregsIn[k];
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if (reg >= 0 && (ops[i].fprInXmm & (1 << reg)))
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fpr.BindToRegister(reg, true, false);
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if (fpr.NumFreeRegisters() < 2)
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break;
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if (ops[i].fprInXmm[reg])
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gpr.BindToRegister(reg, true, false);
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}
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Jit64Tables::CompileInstruction(ops[i]);
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// If we have a register that will never be used again, flush it.
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for (int j = 0; j < 32; j++)
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{
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if (!(ops[i].gprInUse & (1 << j)))
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for (int j : ~ops[i].gprInUse)
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gpr.StoreFromRegister(j);
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if (!(ops[i].fprInUse & (1 << j)))
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for (int j : ~ops[i].fprInUse)
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fpr.StoreFromRegister(j);
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}
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if (js.memcheck && (opinfo->flags & FL_LOADSTORE))
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{
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xreg.locked = false;
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}
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u32 GPRRegCache::GetRegUtilization()
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BitSet32 GPRRegCache::GetRegUtilization()
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{
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return jit->js.op->gprInReg;
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}
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u32 FPURegCache::GetRegUtilization()
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BitSet32 FPURegCache::GetRegUtilization()
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{
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return jit->js.op->gprInReg;
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}
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u32 GPRRegCache::CountRegsIn(size_t preg, u32 lookahead)
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BitSet32 GPRRegCache::CountRegsIn(size_t preg, u32 lookahead)
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{
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u32 regsUsed = 0;
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BitSet32 regsUsed;
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for (u32 i = 1; i < lookahead; i++)
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{
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for (int j = 0; j < 3; j++)
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if (jit->js.op[i].regsIn[j] >= 0)
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regsUsed |= 1 << jit->js.op[i].regsIn[j];
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for (int j = 0; j < 3; j++)
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if ((size_t)jit->js.op[i].regsIn[j] == preg)
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BitSet32 regsIn = jit->js.op[i].regsIn;
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regsUsed |= regsIn;
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if (regsIn[preg])
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return regsUsed;
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}
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return regsUsed;
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}
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u32 FPURegCache::CountRegsIn(size_t preg, u32 lookahead)
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BitSet32 FPURegCache::CountRegsIn(size_t preg, u32 lookahead)
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{
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u32 regsUsed = 0;
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BitSet32 regsUsed;
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for (u32 i = 1; i < lookahead; i++)
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{
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for (int j = 0; j < 4; j++)
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if (jit->js.op[i].fregsIn[j] >= 0)
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regsUsed |= 1 << jit->js.op[i].fregsIn[j];
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for (int j = 0; j < 4; j++)
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if ((size_t)jit->js.op[i].fregsIn[j] == preg)
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BitSet32 regsIn = jit->js.op[i].fregsIn;
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regsUsed |= regsIn;
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if (regsIn[preg])
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return regsUsed;
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}
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return regsUsed;
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@ -151,17 +147,14 @@ float RegCache::ScoreRegister(X64Reg xr)
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// If the register isn't actually needed in a physical register for a later instruction,
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// writing it back to the register file isn't quite as bad.
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if (GetRegUtilization() & (1 << preg))
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if (GetRegUtilization()[preg])
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{
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// Don't look too far ahead; we don't want to have quadratic compilation times for
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// enormous block sizes!
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// This actually improves register allocation a tiny bit; I'm not sure why.
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u32 lookahead = std::min(jit->js.instructionsLeft, 64);
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// Count how many other registers are going to be used before we need this one again.
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u32 regs_in = CountRegsIn(preg, lookahead);
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u32 regs_in_count = 0;
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for (int i = 0; i < 32; i++)
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regs_in_count += !!(regs_in & (1 << i));
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u32 regs_in_count = CountRegsIn(preg, lookahead).Count();
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// Totally ad-hoc heuristic to bias based on how many other registers we'll need
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// before this one gets used again.
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score += 1 + 2 * (5 - log2f(1 + (float)regs_in_count));
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@ -44,8 +44,8 @@ protected:
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virtual const int *GetAllocationOrder(size_t& count) = 0;
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virtual u32 GetRegUtilization() = 0;
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virtual u32 CountRegsIn(size_t preg, u32 lookahead) = 0;
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virtual BitSet32 GetRegUtilization() = 0;
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virtual BitSet32 CountRegsIn(size_t preg, u32 lookahead) = 0;
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Gen::XEmitter *emit;
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@ -137,8 +137,8 @@ public:
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Gen::OpArg GetDefaultLocation(size_t reg) const override;
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const int* GetAllocationOrder(size_t& count) override;
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void SetImmediate32(size_t preg, u32 immValue);
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u32 GetRegUtilization();
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u32 CountRegsIn(size_t preg, u32 lookahead);
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BitSet32 GetRegUtilization() override;
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BitSet32 CountRegsIn(size_t preg, u32 lookahead) override;
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};
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@ -149,6 +149,6 @@ public:
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void LoadRegister(size_t preg, Gen::X64Reg newLoc) override;
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const int* GetAllocationOrder(size_t& count) override;
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Gen::OpArg GetDefaultLocation(size_t reg) const override;
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u32 GetRegUtilization();
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u32 CountRegsIn(size_t preg, u32 lookahead);
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BitSet32 GetRegUtilization() override;
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BitSet32 CountRegsIn(size_t preg, u32 lookahead) override;
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};
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@ -249,21 +249,15 @@ static bool CanSwapAdjacentOps(const CodeOp &a, const CodeOp &b)
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// That is, check that none of b's outputs matches any of a's inputs,
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// and that none of a's outputs matches any of b's inputs.
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// The latter does not apply if a is a cmp, of course, but doesn't hurt to check.
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for (int j = 0; j < 3; j++)
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{
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int regInA = a.regsIn[j];
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int regInB = b.regsIn[j];
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// register collision: b outputs to one of a's inputs
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if (regInA >= 0 && (b.regsOut[0] == regInA || b.regsOut[1] == regInA))
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if (b.regsOut & a.regsIn)
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return false;
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// register collision: a outputs to one of b's inputs
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if (regInB >= 0 && (a.regsOut[0] == regInB || a.regsOut[1] == regInB))
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if (a.regsOut & b.regsIn)
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return false;
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// register collision: b outputs to one of a's outputs (overwriting it)
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for (int k = 0; k < 2; k++)
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if (b.regsOut[k] >= 0 && (b.regsOut[k] == a.regsOut[0] || b.regsOut[k] == a.regsOut[1]))
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if (b.regsOut & a.regsOut)
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return false;
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}
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return true;
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}
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@ -520,42 +514,41 @@ void PPCAnalyzer::SetInstructionStats(CodeBlock *block, CodeOp *code, GekkoOPInf
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if (code->inst.OPCD == 31 && code->inst.SUBOP10 == 467) // mtspr
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code->outputCA = ((code->inst.SPRU << 5) | (code->inst.SPRL & 0x1F)) == SPR_XER;
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int numOut = 0;
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int numIn = 0;
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int numFloatIn = 0;
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code->regsIn = BitSet32(0);
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code->regsOut = BitSet32(0);
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if (opinfo->flags & FL_OUT_A)
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{
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code->regsOut[numOut++] = code->inst.RA;
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code->regsOut[code->inst.RA] = true;
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block->m_gpa->SetOutputRegister(code->inst.RA, index);
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}
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if (opinfo->flags & FL_OUT_D)
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{
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code->regsOut[numOut++] = code->inst.RD;
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code->regsOut[code->inst.RD] = true;
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block->m_gpa->SetOutputRegister(code->inst.RD, index);
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}
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if (opinfo->flags & FL_OUT_S)
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{
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code->regsOut[numOut++] = code->inst.RS;
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code->regsOut[code->inst.RS] = true;
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block->m_gpa->SetOutputRegister(code->inst.RS, index);
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}
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if ((opinfo->flags & FL_IN_A) || ((opinfo->flags & FL_IN_A0) && code->inst.RA != 0))
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{
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code->regsIn[numIn++] = code->inst.RA;
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code->regsIn[code->inst.RA] = true;
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block->m_gpa->SetInputRegister(code->inst.RA, index);
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}
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if (opinfo->flags & FL_IN_B)
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{
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code->regsIn[numIn++] = code->inst.RB;
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code->regsIn[code->inst.RB] = true;
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block->m_gpa->SetInputRegister(code->inst.RB, index);
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}
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if (opinfo->flags & FL_IN_C)
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{
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code->regsIn[numIn++] = code->inst.RC;
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code->regsIn[code->inst.RC] = true;
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block->m_gpa->SetInputRegister(code->inst.RC, index);
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}
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if (opinfo->flags & FL_IN_S)
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{
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code->regsIn[numIn++] = code->inst.RS;
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code->regsIn[code->inst.RS] = true;
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block->m_gpa->SetInputRegister(code->inst.RS, index);
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}
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@ -564,24 +557,17 @@ void PPCAnalyzer::SetInstructionStats(CodeBlock *block, CodeOp *code, GekkoOPInf
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code->fregOut = code->inst.FD;
|
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else if (opinfo->flags & FL_OUT_FLOAT_S)
|
||||
code->fregOut = code->inst.FS;
|
||||
code->fregsIn = BitSet32(0);
|
||||
if (opinfo->flags & FL_IN_FLOAT_A)
|
||||
code->fregsIn[numFloatIn++] = code->inst.FA;
|
||||
code->fregsIn[code->inst.FA] = true;
|
||||
if (opinfo->flags & FL_IN_FLOAT_B)
|
||||
code->fregsIn[numFloatIn++] = code->inst.FB;
|
||||
code->fregsIn[code->inst.FB] = true;
|
||||
if (opinfo->flags & FL_IN_FLOAT_C)
|
||||
code->fregsIn[numFloatIn++] = code->inst.FC;
|
||||
code->fregsIn[code->inst.FC] = true;
|
||||
if (opinfo->flags & FL_IN_FLOAT_D)
|
||||
code->fregsIn[numFloatIn++] = code->inst.FD;
|
||||
code->fregsIn[code->inst.FD] = true;
|
||||
if (opinfo->flags & FL_IN_FLOAT_S)
|
||||
code->fregsIn[numFloatIn++] = code->inst.FS;
|
||||
|
||||
// Set remaining register slots as unused (-1)
|
||||
for (int j = numIn; j < 3; j++)
|
||||
code->regsIn[j] = -1;
|
||||
for (int j = numOut; j < 2; j++)
|
||||
code->regsOut[j] = -1;
|
||||
for (int j = numFloatIn; j < 4; j++)
|
||||
code->fregsIn[j] = -1;
|
||||
code->fregsIn[code->inst.FS] = true;
|
||||
|
||||
switch (opinfo->type)
|
||||
{
|
||||
|
|
@ -797,7 +783,7 @@ u32 PPCAnalyzer::Analyze(u32 address, CodeBlock *block, CodeBuffer *buffer, u32
|
|||
// Scan for flag dependencies; assume the next block (or any branch that can leave the block)
|
||||
// wants flags, to be safe.
|
||||
bool wantsCR0 = true, wantsCR1 = true, wantsFPRF = true, wantsCA = true;
|
||||
u32 fprInUse = 0, gprInUse = 0, gprInReg = 0, fprInXmm = 0;
|
||||
BitSet32 fprInUse, gprInUse, gprInReg, fprInXmm;
|
||||
for (int i = block->m_num_instructions - 1; i >= 0; i--)
|
||||
{
|
||||
bool opWantsCR0 = code[i].wantsCR0;
|
||||
|
|
@ -822,30 +808,20 @@ u32 PPCAnalyzer::Analyze(u32 address, CodeBlock *block, CodeBuffer *buffer, u32
|
|||
code[i].fprInXmm = fprInXmm;
|
||||
// TODO: if there's no possible endblocks or exceptions in between, tell the regcache
|
||||
// we can throw away a register if it's going to be overwritten later.
|
||||
for (int j = 0; j < 3; j++)
|
||||
if (code[i].regsIn[j] >= 0)
|
||||
{
|
||||
gprInUse |= 1 << code[i].regsIn[j];
|
||||
gprInReg |= 1 << code[i].regsIn[j];
|
||||
}
|
||||
for (int j = 0; j < 4; j++)
|
||||
if (code[i].fregsIn[j] >= 0)
|
||||
{
|
||||
fprInUse |= 1 << code[i].fregsIn[j];
|
||||
gprInUse |= code[i].regsIn;
|
||||
gprInReg |= code[i].regsIn;
|
||||
fprInUse |= code[i].fregsIn;
|
||||
if (strncmp(code[i].opinfo->opname, "stfd", 4))
|
||||
fprInXmm |= 1 << code[i].fregsIn[j];
|
||||
}
|
||||
fprInXmm |= code[i].fregsIn;
|
||||
// For now, we need to count output registers as "used" though; otherwise the flush
|
||||
// will result in a redundant store (e.g. store to regcache, then store again to
|
||||
// the same location later).
|
||||
for (int j = 0; j < 2; j++)
|
||||
if (code[i].regsOut[j] >= 0)
|
||||
gprInUse |= 1 << code[i].regsOut[j];
|
||||
gprInUse |= code[i].regsOut;
|
||||
if (code[i].fregOut >= 0)
|
||||
{
|
||||
fprInUse |= 1 << code[i].fregOut;
|
||||
fprInUse[code[i].fregOut] = true;
|
||||
if (strncmp(code[i].opinfo->opname, "stfd", 4))
|
||||
fprInXmm |= 1 << code[i].fregOut;
|
||||
fprInXmm[code[i].fregOut] = true;
|
||||
}
|
||||
}
|
||||
return address;
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@
|
|||
#include <string>
|
||||
#include <vector>
|
||||
|
||||
#include "Common/BitSet.h"
|
||||
#include "Common/CommonTypes.h"
|
||||
#include "Core/PowerPC/PPCTables.h"
|
||||
|
||||
|
|
@ -26,10 +27,10 @@ struct CodeOp //16B
|
|||
u32 address;
|
||||
u32 branchTo; //if 0, not a branch
|
||||
int branchToIndex; //index of target block
|
||||
s8 regsOut[2];
|
||||
s8 regsIn[3];
|
||||
BitSet32 regsOut;
|
||||
BitSet32 regsIn;
|
||||
BitSet32 fregsIn;
|
||||
s8 fregOut;
|
||||
s8 fregsIn[4];
|
||||
bool isBranchTarget;
|
||||
bool wantsCR0;
|
||||
bool wantsCR1;
|
||||
|
|
@ -43,13 +44,13 @@ struct CodeOp //16B
|
|||
bool canEndBlock;
|
||||
bool skip; // followed BL-s for example
|
||||
// which registers are still needed after this instruction in this block
|
||||
u32 fprInUse;
|
||||
u32 gprInUse;
|
||||
BitSet32 fprInUse;
|
||||
BitSet32 gprInUse;
|
||||
// just because a register is in use doesn't mean we actually need or want it in an x86 register.
|
||||
u32 gprInReg;
|
||||
BitSet32 gprInReg;
|
||||
// we do double stores from GPRs, so we don't want to load a PowerPC floating point register into
|
||||
// an XMM only to move it again to a GPR afterwards.
|
||||
u32 fprInXmm;
|
||||
BitSet32 fprInXmm;
|
||||
};
|
||||
|
||||
struct BlockStats
|
||||
|
|
|
|||
Loading…
Reference in New Issue