From b63808a652b4233dc9ebf77603f5a5a719987f01 Mon Sep 17 00:00:00 2001 From: Bram Speeckaert Date: Sat, 4 May 2024 17:38:04 +0200 Subject: [PATCH] JitArm64: rlwimix - Conditionally skip temp reg allocation --- .../Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp index dbcb6370ec..7e5817ac0c 100644 --- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp +++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp @@ -2106,15 +2106,19 @@ void JitArm64::rlwimix(UGeckoInstruction inst) else { gpr.BindToRegister(a, true); + const bool allocate_reg = a == s; + ARM64Reg RA = gpr.R(a); ARM64Reg WA = gpr.GetReg(); - ARM64Reg WB = gpr.GetReg(); + ARM64Reg WB = allocate_reg ? gpr.GetReg() : RA; MOVI2R(WA, mask); - BIC(WB, gpr.R(a), WA); + BIC(WB, RA, WA); AND(WA, WA, gpr.R(s), ArithOption(gpr.R(s), ShiftType::ROR, rot_dist)); - ORR(gpr.R(a), WB, WA); + ORR(RA, WB, WA); - gpr.Unlock(WA, WB); + gpr.Unlock(WA); + if (allocate_reg) + gpr.Unlock(WB); } if (inst.Rc)