diff --git a/Source/Core/Core/PowerPC/Interpreter/Interpreter_LoadStore.cpp b/Source/Core/Core/PowerPC/Interpreter/Interpreter_LoadStore.cpp
index a5cafc01d8..e197fd37a2 100644
--- a/Source/Core/Core/PowerPC/Interpreter/Interpreter_LoadStore.cpp
+++ b/Source/Core/Core/PowerPC/Interpreter/Interpreter_LoadStore.cpp
@@ -316,25 +316,24 @@ void Interpreter::dcba(UGeckoInstruction _inst)
 
 void Interpreter::dcbf(UGeckoInstruction _inst)
 {
-  // This should tell GFX backend to throw out any cached data here
-  // !!! SPEEDUP HACK for OSProtectRange !!!
-  /*	u32 tmp1 = PowerPC::HostRead_U32(PC+4);
-    u32 tmp2 = PowerPC::HostRead_U32(PC+8);
+  // TODO: Implement some sort of L2 emulation.
+  // TODO: Raise DSI if translation fails (except for direct-store segments).
 
-    if ((tmp1 == 0x38630020) &&
-      (tmp2 == 0x4200fff8))
-    {
-      NPC = PC + 12;
-    }*/
+  // Invalidate the JIT cache here as a heuristic to compensate for
+  // the lack of precise L1 icache emulation in the JIT. (Portable software
+  // should use icbi consistently, but games aren't portable.)
   u32 address = Helper_Get_EA_X(_inst);
   JitInterface::InvalidateICache(address & ~0x1f, 32, false);
 }
 
 void Interpreter::dcbi(UGeckoInstruction _inst)
 {
-  // Removes a block from data cache. Since we don't emulate the data cache, we don't need to do
-  // anything to the data cache
-  // However, we invalidate the jit block cache on dcbi
+  // TODO: Implement some sort of L2 emulation.
+  // TODO: Raise DSI if translation fails (except for direct-store segments).
+
+  // Invalidate the JIT cache here as a heuristic to compensate for
+  // the lack of precise L1 icache emulation in the JIT. (Portable software
+  // should use icbi consistently, but games aren't portable.)
   u32 address = Helper_Get_EA_X(_inst);
   JitInterface::InvalidateICache(address & ~0x1f, 32, false);
 
@@ -349,30 +348,33 @@ void Interpreter::dcbi(UGeckoInstruction _inst)
 
 void Interpreter::dcbst(UGeckoInstruction _inst)
 {
-  // Cache line flush. Since we don't emulate the data cache, we don't need to do anything.
-  // Invalidate the jit block cache on dcbst in case new code has been loaded via the data cache
+  // TODO: Implement some sort of L2 emulation.
+  // TODO: Raise DSI if translation fails (except for direct-store segments).
+
+  // Invalidate the JIT cache here as a heuristic to compensate for
+  // the lack of precise L1 icache emulation in the JIT. (Portable software
+  // should use icbi consistently, but games aren't portable.)
   u32 address = Helper_Get_EA_X(_inst);
   JitInterface::InvalidateICache(address & ~0x1f, 32, false);
 }
 
 void Interpreter::dcbt(UGeckoInstruction _inst)
 {
-  // Prefetch. Since we don't emulate the data cache, we don't need to do anything.
+  // TODO: Implement some sort of L2 emulation.
 }
 
 void Interpreter::dcbtst(UGeckoInstruction _inst)
 {
-  // This is just some sort of store "prefetching".
-  // Since we don't emulate the data cache, we don't need to do anything.
+  // TODO: Implement some sort of L2 emulation.
 }
 
 void Interpreter::dcbz(UGeckoInstruction _inst)
 {
-  // HACK but works... we think
+  // TODO: Implement some sort of L2 emulation.
+  // DCBZOFF is a hack to fix certain games which would otherwise require
+  // accurate L2 emulation.
   if (!SConfig::GetInstance().bDCBZOFF)
     PowerPC::ClearCacheLine(Helper_Get_EA_X(_inst) & (~31));
-  if (!JitInterface::GetCore())
-    PowerPC::CheckExceptions();
 }
 
 // eciwx/ecowx technically should access the specified device
@@ -388,8 +390,8 @@ void Interpreter::eciwx(UGeckoInstruction _inst)
   if (EA & 3)
     PowerPC::ppcState.Exceptions |= EXCEPTION_ALIGNMENT;
 
-  // 	_assert_msg_(POWERPC,0,"eciwx - fill r%i with word @ %08x from device %02x",
-  // 		_inst.RS, EA, PowerPC::ppcState.spr[SPR_EAR] & 0x1f);
+  // _assert_msg_(POWERPC,0,"eciwx - fill r%i with word @ %08x from device %02x",
+  //              _inst.RS, EA, PowerPC::ppcState.spr[SPR_EAR] & 0x1f);
 
   rGPR[_inst.RD] = PowerPC::Read_U32(EA);
 }
@@ -405,8 +407,8 @@ void Interpreter::ecowx(UGeckoInstruction _inst)
   if (EA & 3)
     PowerPC::ppcState.Exceptions |= EXCEPTION_ALIGNMENT;
 
-  // 	_assert_msg_(POWERPC,0,"ecowx - send stw request (%08x@%08x) to device %02x",
-  // 		rGPR[_inst.RS], EA, PowerPC::ppcState.spr[SPR_EAR] & 0x1f);
+  // _assert_msg_(POWERPC,0,"ecowx - send stw request (%08x@%08x) to device %02x",
+  //              rGPR[_inst.RS], EA, PowerPC::ppcState.spr[SPR_EAR] & 0x1f);
 
   PowerPC::Write_U32(rGPR[_inst.RS], EA);
 }
@@ -421,6 +423,7 @@ void Interpreter::eieio(UGeckoInstruction _inst)
 
 void Interpreter::icbi(UGeckoInstruction _inst)
 {
+  // TODO: Raise DSI if translation fails (except for direct-store segments).
   u32 address = Helper_Get_EA_X(_inst);
   PowerPC::ppcState.iCache.Invalidate(address);
 }
diff --git a/Source/Core/Core/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp b/Source/Core/Core/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp
index 1a85292923..a1a4b5f683 100644
--- a/Source/Core/Core/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp
+++ b/Source/Core/Core/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp
@@ -34,7 +34,7 @@ static void FPSCRtoFPUSettings(UReg_FPSCR fp)
   if (fp.VE || fp.OE || fp.UE || fp.ZE || fp.XE)
   {
     // PanicAlert("FPSCR - exceptions enabled. Please report. VE=%i OE=%i UE=%i ZE=%i XE=%i",
-    //	fp.VE, fp.OE, fp.UE, fp.ZE, fp.XE);
+    // fp.VE, fp.OE, fp.UE, fp.ZE, fp.XE);
     // Pokemon Colosseum does this. Gah.
   }
 
@@ -413,7 +413,7 @@ void Interpreter::isync(UGeckoInstruction _inst)
 void Interpreter::mcrfs(UGeckoInstruction _inst)
 {
   // if (_inst.CRFS != 3 && _inst.CRFS != 4)
-  //	PanicAlert("msrfs at %x, CRFS = %d, CRFD = %d", PC, (int)_inst.CRFS, (int)_inst.CRFD);
+  //   PanicAlert("msrfs at %x, CRFS = %d, CRFD = %d", PC, (int)_inst.CRFS, (int)_inst.CRFD);
 
   UpdateFPSCR();
   u32 fpflags = ((FPSCR.Hex >> (4 * (7 - _inst.CRFS))) & 0xF);