Merge pull request #4535 from lioncash/regcache
Jit64: Make register caches not rely on the global jit variable
This commit is contained in:
Mat M
GitHub
commit
b10a0de769
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@ -196,6 +196,8 @@ if(_M_X86)
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PowerPC/Jit64IL/IR_X86.cpp
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PowerPC/Jit64IL/JitIL.cpp
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PowerPC/Jit64IL/JitIL_Tables.cpp
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PowerPC/Jit64/FPURegCache.cpp
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PowerPC/Jit64/GPRRegCache.cpp
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PowerPC/Jit64/Jit64_Tables.cpp
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PowerPC/Jit64/JitAsm.cpp
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PowerPC/Jit64/Jit_Branch.cpp
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@ -225,6 +225,8 @@
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<ClCompile Include="PowerPC\Jit64IL\IR_X86.cpp" />
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<ClCompile Include="PowerPC\Jit64IL\JitIL.cpp" />
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<ClCompile Include="PowerPC\Jit64IL\JitIL_Tables.cpp" />
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<ClCompile Include="PowerPC\Jit64\FPURegCache.cpp" />
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<ClCompile Include="PowerPC\Jit64\GPRRegCache.cpp" />
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<ClCompile Include="PowerPC\Jit64\Jit.cpp" />
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<ClCompile Include="PowerPC\Jit64\Jit64_Tables.cpp" />
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<ClCompile Include="PowerPC\Jit64\JitAsm.cpp" />
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@ -427,6 +429,8 @@
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<ClInclude Include="PowerPC\Interpreter\Interpreter_Tables.h" />
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<ClInclude Include="PowerPC\Jit64IL\JitIL.h" />
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<ClInclude Include="PowerPC\Jit64IL\JitIL_Tables.h" />
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<ClInclude Include="PowerPC\Jit64\FPURegCache.h" />
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<ClInclude Include="PowerPC\Jit64\GPRRegCache.h" />
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<ClInclude Include="PowerPC\Jit64\Jit.h" />
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<ClInclude Include="PowerPC\Jit64\Jit64_Tables.h" />
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<ClInclude Include="PowerPC\Jit64\JitAsm.h" />
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@ -666,6 +666,12 @@
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<ClCompile Include="PowerPC\Jit64IL\JitIL_Tables.cpp">
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<Filter>PowerPC\JitIL</Filter>
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</ClCompile>
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<ClCompile Include="PowerPC\Jit64\FPURegCache.cpp">
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<Filter>PowerPC\Jit64</Filter>
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</ClCompile>
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<ClCompile Include="PowerPC\Jit64\GPRRegCache.cpp">
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<Filter>PowerPC\Jit64</Filter>
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</ClCompile>
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<ClCompile Include="PowerPC\Jit64\Jit_Branch.cpp">
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<Filter>PowerPC\Jit64</Filter>
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</ClCompile>
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@ -1262,6 +1268,12 @@
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<ClInclude Include="PowerPC\Jit64IL\JitIL_Tables.h">
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<Filter>PowerPC\JitIL</Filter>
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</ClInclude>
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<ClInclude Include="PowerPC\Jit64\FPURegCache.h">
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<Filter>PowerPC\Jit64</Filter>
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</ClInclude>
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<ClInclude Include="PowerPC\Jit64\GPRRegCache.h">
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<Filter>PowerPC\Jit64</Filter>
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</ClInclude>
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<ClInclude Include="PowerPC\Jit64\JitRegCache.h">
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<Filter>PowerPC\Jit64</Filter>
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</ClInclude>
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@ -0,0 +1,58 @@
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// Copyright 2016 Dolphin Emulator Project
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// Licensed under GPLv2+
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// Refer to the license.txt file included.
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#include "Core/PowerPC/Jit64/FPURegCache.h"
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#include "Core/PowerPC/Jit64/Jit.h"
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#include "Core/PowerPC/Jit64Common/Jit64Base.h"
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#include "Core/PowerPC/Jit64Common/Jit64PowerPCState.h"
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using namespace Gen;
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FPURegCache::FPURegCache(Jit64& jit) : RegCache{jit}
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{
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}
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void FPURegCache::StoreRegister(size_t preg, const OpArg& new_loc)
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{
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m_emitter->MOVAPD(new_loc, m_regs[preg].location.GetSimpleReg());
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}
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void FPURegCache::LoadRegister(size_t preg, X64Reg new_loc)
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{
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m_emitter->MOVAPD(new_loc, m_regs[preg].location);
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}
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const X64Reg* FPURegCache::GetAllocationOrder(size_t* count)
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{
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static const X64Reg allocation_order[] = {XMM6, XMM7, XMM8, XMM9, XMM10, XMM11, XMM12,
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XMM13, XMM14, XMM15, XMM2, XMM3, XMM4, XMM5};
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*count = sizeof(allocation_order) / sizeof(X64Reg);
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return allocation_order;
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}
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OpArg FPURegCache::GetDefaultLocation(size_t reg) const
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{
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return PPCSTATE(ps[reg][0]);
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}
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BitSet32 FPURegCache::GetRegUtilization()
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{
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return m_jit.js.op->gprInReg;
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}
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BitSet32 FPURegCache::CountRegsIn(size_t preg, u32 lookahead)
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{
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BitSet32 regs_used;
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for (u32 i = 1; i < lookahead; i++)
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{
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BitSet32 regs_in = m_jit.js.op[i].fregsIn;
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regs_used |= regs_in;
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if (regs_in[preg])
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return regs_used;
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}
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return regs_used;
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}
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@ -0,0 +1,22 @@
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// Copyright 2016 Dolphin Emulator Project
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// Licensed under GPLv2+
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// Refer to the license.txt file included.
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#pragma once
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#include "Core/PowerPC/Jit64/JitRegCache.h"
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class Jit64;
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class FPURegCache final : public RegCache
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{
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public:
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explicit FPURegCache(Jit64& jit);
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void StoreRegister(size_t preg, const Gen::OpArg& newLoc) override;
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void LoadRegister(size_t preg, Gen::X64Reg newLoc) override;
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const Gen::X64Reg* GetAllocationOrder(size_t* count) override;
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Gen::OpArg GetDefaultLocation(size_t reg) const override;
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BitSet32 GetRegUtilization() override;
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BitSet32 CountRegsIn(size_t preg, u32 lookahead) override;
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};
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@ -0,0 +1,76 @@
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// Copyright 2016 Dolphin Emulator Project
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// Licensed under GPLv2+
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// Refer to the license.txt file included.
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#include "Core/PowerPC/Jit64/GPRRegCache.h"
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#include "Core/PowerPC/Jit64/Jit.h"
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#include "Core/PowerPC/Jit64Common/Jit64Base.h"
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#include "Core/PowerPC/Jit64Common/Jit64PowerPCState.h"
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using namespace Gen;
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GPRRegCache::GPRRegCache(Jit64& jit) : RegCache{jit}
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{
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}
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void GPRRegCache::StoreRegister(size_t preg, const OpArg& new_loc)
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{
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m_emitter->MOV(32, new_loc, m_regs[preg].location);
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}
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void GPRRegCache::LoadRegister(size_t preg, X64Reg new_loc)
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{
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m_emitter->MOV(32, ::Gen::R(new_loc), m_regs[preg].location);
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}
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OpArg GPRRegCache::GetDefaultLocation(size_t reg) const
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{
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return PPCSTATE(gpr[reg]);
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}
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const X64Reg* GPRRegCache::GetAllocationOrder(size_t* count)
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{
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static const X64Reg allocation_order[] = {
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// R12, when used as base register, for example in a LEA, can generate bad code! Need to look into
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// this.
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#ifdef _WIN32
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RSI, RDI, R13, R14, R15, R8,
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R9, R10, R11, R12, RCX
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#else
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R12, R13, R14, R15, RSI, RDI,
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R8, R9, R10, R11, RCX
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#endif
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};
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*count = sizeof(allocation_order) / sizeof(X64Reg);
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return allocation_order;
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}
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void GPRRegCache::SetImmediate32(size_t preg, u32 imm_value, bool dirty)
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{
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// "dirty" can be false to avoid redundantly flushing an immediate when
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// processing speculative constants.
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DiscardRegContentsIfCached(preg);
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m_regs[preg].away |= dirty;
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m_regs[preg].location = Imm32(imm_value);
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}
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BitSet32 GPRRegCache::GetRegUtilization()
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{
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return m_jit.js.op->gprInReg;
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}
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BitSet32 GPRRegCache::CountRegsIn(size_t preg, u32 lookahead)
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{
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BitSet32 regs_used;
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for (u32 i = 1; i < lookahead; i++)
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{
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BitSet32 regs_in = m_jit.js.op[i].regsIn;
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regs_used |= regs_in;
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if (regs_in[preg])
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return regs_used;
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}
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return regs_used;
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}
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@ -0,0 +1,23 @@
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// Copyright 2016 Dolphin Emulator Project
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// Licensed under GPLv2+
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// Refer to the license.txt file included.
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#pragma once
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#include "Core/PowerPC/Jit64/JitRegCache.h"
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class Jit64;
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class GPRRegCache final : public RegCache
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{
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public:
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explicit GPRRegCache(Jit64& jit);
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void StoreRegister(size_t preg, const Gen::OpArg& new_loc) override;
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void LoadRegister(size_t preg, Gen::X64Reg new_loc) override;
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Gen::OpArg GetDefaultLocation(size_t reg) const override;
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const Gen::X64Reg* GetAllocationOrder(size_t* count) override;
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void SetImmediate32(size_t preg, u32 imm_value, bool dirty = true);
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BitSet32 GetRegUtilization() override;
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BitSet32 CountRegsIn(size_t preg, u32 lookahead) override;
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};
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@ -950,7 +950,7 @@ BitSet8 Jit64::ComputeStaticGQRs(const PPCAnalyst::CodeBlock& cb) const
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BitSet32 Jit64::CallerSavedRegistersInUse() const
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{
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BitSet32 result;
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for (int i = 0; i < NUMXREGS; i++)
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for (size_t i = 0; i < RegCache::NUM_XREGS; i++)
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{
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if (!gpr.IsFreeX(i))
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result[i] = true;
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@ -21,6 +21,8 @@
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#include "Common/CommonTypes.h"
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#include "Common/x64ABI.h"
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#include "Common/x64Emitter.h"
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#include "Core/PowerPC/Jit64/FPURegCache.h"
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#include "Core/PowerPC/Jit64/GPRRegCache.h"
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#include "Core/PowerPC/Jit64/JitAsm.h"
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#include "Core/PowerPC/Jit64/JitRegCache.h"
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#include "Core/PowerPC/Jit64Common/Jit64Base.h"
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@ -33,8 +35,8 @@ private:
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void AllocStack();
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void FreeStack();
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GPRRegCache gpr;
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FPURegCache fpr;
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GPRRegCache gpr{*this};
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FPURegCache fpr{*this};
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// The default code buffer. We keep it around to not have to alloc/dealloc a
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// large chunk of memory for each recompiled block.
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@ -14,30 +14,29 @@
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#include "Common/x64Emitter.h"
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#include "Core/PowerPC/Jit64/Jit.h"
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#include "Core/PowerPC/Jit64/JitRegCache.h"
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#include "Core/PowerPC/Jit64Common/Jit64PowerPCState.h"
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#include "Core/PowerPC/PowerPC.h"
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using namespace Gen;
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using namespace PowerPC;
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RegCache::RegCache() : emit(nullptr)
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RegCache::RegCache(Jit64& jit) : m_jit{jit}
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{
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}
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void RegCache::Start()
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{
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for (auto& xreg : xregs)
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for (auto& xreg : m_xregs)
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{
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xreg.free = true;
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xreg.dirty = false;
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xreg.locked = false;
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xreg.ppcReg = INVALID_REG;
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}
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for (size_t i = 0; i < regs.size(); i++)
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for (size_t i = 0; i < m_regs.size(); i++)
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{
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regs[i].location = GetDefaultLocation(i);
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regs[i].away = false;
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regs[i].locked = false;
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m_regs[i].location = GetDefaultLocation(i);
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m_regs[i].away = false;
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m_regs[i].locked = false;
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}
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// todo: sort to find the most popular regs
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@ -57,84 +56,220 @@ void RegCache::Start()
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// But only preload IF written OR reads >= 3
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}
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void RegCache::DiscardRegContentsIfCached(size_t preg)
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{
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if (IsBound(preg))
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{
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X64Reg xr = m_regs[preg].location.GetSimpleReg();
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m_xregs[xr].free = true;
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m_xregs[xr].dirty = false;
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m_xregs[xr].ppcReg = INVALID_REG;
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m_regs[preg].away = false;
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m_regs[preg].location = GetDefaultLocation(preg);
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}
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}
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void RegCache::SetEmitter(XEmitter* emitter)
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{
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m_emitter = emitter;
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}
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void RegCache::Flush(FlushMode mode, BitSet32 regsToFlush)
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{
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for (size_t i = 0; i < m_xregs.size(); i++)
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{
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if (m_xregs[i].locked)
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PanicAlert("Someone forgot to unlock X64 reg %zu", i);
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}
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for (unsigned int i : regsToFlush)
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{
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if (m_regs[i].locked)
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{
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PanicAlert("Someone forgot to unlock PPC reg %u (X64 reg %i).", i, RX(i));
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}
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if (m_regs[i].away)
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{
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if (m_regs[i].location.IsSimpleReg() || m_regs[i].location.IsImm())
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{
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StoreFromRegister(i, mode);
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}
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else
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{
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_assert_msg_(DYNA_REC, 0, "Jit64 - Flush unhandled case, reg %u PC: %08x", i, PC);
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}
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}
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}
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}
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void RegCache::FlushR(X64Reg reg)
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{
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if (reg >= m_xregs.size())
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PanicAlert("Flushing non existent reg");
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if (!m_xregs[reg].free)
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{
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StoreFromRegister(m_xregs[reg].ppcReg);
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}
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}
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void RegCache::FlushR(X64Reg reg, X64Reg reg2)
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{
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FlushR(reg);
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FlushR(reg2);
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}
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void RegCache::FlushLockX(X64Reg reg)
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{
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FlushR(reg);
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LockX(reg);
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}
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void RegCache::FlushLockX(X64Reg reg1, X64Reg reg2)
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{
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FlushR(reg1);
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FlushR(reg2);
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LockX(reg1);
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LockX(reg2);
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}
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int RegCache::SanityCheck() const
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{
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for (size_t i = 0; i < m_regs.size(); i++)
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{
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if (m_regs[i].away)
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{
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if (m_regs[i].location.IsSimpleReg())
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{
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Gen::X64Reg simple = m_regs[i].location.GetSimpleReg();
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if (m_xregs[simple].locked)
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return 1;
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if (m_xregs[simple].ppcReg != i)
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return 2;
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}
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else if (m_regs[i].location.IsImm())
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{
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return 3;
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}
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}
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}
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return 0;
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}
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void RegCache::KillImmediate(size_t preg, bool doLoad, bool makeDirty)
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{
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if (m_regs[preg].away)
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{
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if (m_regs[preg].location.IsImm())
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BindToRegister(preg, doLoad, makeDirty);
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else if (m_regs[preg].location.IsSimpleReg())
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m_xregs[RX(preg)].dirty |= makeDirty;
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}
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}
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void RegCache::BindToRegister(size_t i, bool doLoad, bool makeDirty)
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{
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if (!m_regs[i].away || m_regs[i].location.IsImm())
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{
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X64Reg xr = GetFreeXReg();
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if (m_xregs[xr].dirty)
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PanicAlert("Xreg already dirty");
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if (m_xregs[xr].locked)
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PanicAlert("GetFreeXReg returned locked register");
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m_xregs[xr].free = false;
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m_xregs[xr].ppcReg = i;
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m_xregs[xr].dirty = makeDirty || m_regs[i].away;
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if (doLoad)
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LoadRegister(i, xr);
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for (size_t j = 0; j < m_regs.size(); j++)
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{
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if (i != j && m_regs[j].location.IsSimpleReg(xr))
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{
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Crash();
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}
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}
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m_regs[i].away = true;
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m_regs[i].location = ::Gen::R(xr);
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}
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else
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{
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// reg location must be simplereg; memory locations
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// and immediates are taken care of above.
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m_xregs[RX(i)].dirty |= makeDirty;
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}
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|
||||
if (m_xregs[RX(i)].locked)
|
||||
{
|
||||
PanicAlert("Seriously WTF, this reg should have been flushed");
|
||||
}
|
||||
}
|
||||
|
||||
void RegCache::StoreFromRegister(size_t i, FlushMode mode)
|
||||
{
|
||||
if (m_regs[i].away)
|
||||
{
|
||||
bool doStore;
|
||||
if (m_regs[i].location.IsSimpleReg())
|
||||
{
|
||||
X64Reg xr = RX(i);
|
||||
doStore = m_xregs[xr].dirty;
|
||||
if (mode == FLUSH_ALL)
|
||||
{
|
||||
m_xregs[xr].free = true;
|
||||
m_xregs[xr].ppcReg = INVALID_REG;
|
||||
m_xregs[xr].dirty = false;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
// must be immediate - do nothing
|
||||
doStore = true;
|
||||
}
|
||||
OpArg newLoc = GetDefaultLocation(i);
|
||||
if (doStore)
|
||||
StoreRegister(i, newLoc);
|
||||
if (mode == FLUSH_ALL)
|
||||
{
|
||||
m_regs[i].location = newLoc;
|
||||
m_regs[i].away = false;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
const OpArg& RegCache::R(size_t preg) const
|
||||
{
|
||||
return m_regs[preg].location;
|
||||
}
|
||||
|
||||
X64Reg RegCache::RX(size_t preg) const
|
||||
{
|
||||
if (IsBound(preg))
|
||||
return m_regs[preg].location.GetSimpleReg();
|
||||
|
||||
PanicAlert("Unbound register - %zu", preg);
|
||||
return Gen::INVALID_REG;
|
||||
}
|
||||
|
||||
void RegCache::UnlockAll()
|
||||
{
|
||||
for (auto& reg : regs)
|
||||
for (auto& reg : m_regs)
|
||||
reg.locked = false;
|
||||
}
|
||||
|
||||
void RegCache::UnlockAllX()
|
||||
{
|
||||
for (auto& xreg : xregs)
|
||||
for (auto& xreg : m_xregs)
|
||||
xreg.locked = false;
|
||||
}
|
||||
|
||||
BitSet32 GPRRegCache::GetRegUtilization()
|
||||
bool RegCache::IsFreeX(size_t xreg) const
|
||||
{
|
||||
return jit->js.op->gprInReg;
|
||||
return m_xregs[xreg].free && !m_xregs[xreg].locked;
|
||||
}
|
||||
|
||||
BitSet32 FPURegCache::GetRegUtilization()
|
||||
bool RegCache::IsBound(size_t preg) const
|
||||
{
|
||||
return jit->js.op->gprInReg;
|
||||
}
|
||||
|
||||
BitSet32 GPRRegCache::CountRegsIn(size_t preg, u32 lookahead)
|
||||
{
|
||||
BitSet32 regsUsed;
|
||||
for (u32 i = 1; i < lookahead; i++)
|
||||
{
|
||||
BitSet32 regsIn = jit->js.op[i].regsIn;
|
||||
regsUsed |= regsIn;
|
||||
if (regsIn[preg])
|
||||
return regsUsed;
|
||||
}
|
||||
return regsUsed;
|
||||
}
|
||||
|
||||
BitSet32 FPURegCache::CountRegsIn(size_t preg, u32 lookahead)
|
||||
{
|
||||
BitSet32 regsUsed;
|
||||
for (u32 i = 1; i < lookahead; i++)
|
||||
{
|
||||
BitSet32 regsIn = jit->js.op[i].fregsIn;
|
||||
regsUsed |= regsIn;
|
||||
if (regsIn[preg])
|
||||
return regsUsed;
|
||||
}
|
||||
return regsUsed;
|
||||
}
|
||||
|
||||
// Estimate roughly how bad it would be to de-allocate this register. Higher score
|
||||
// means more bad.
|
||||
float RegCache::ScoreRegister(X64Reg xr)
|
||||
{
|
||||
size_t preg = xregs[xr].ppcReg;
|
||||
float score = 0;
|
||||
|
||||
// If it's not dirty, we don't need a store to write it back to the register file, so
|
||||
// bias a bit against dirty registers. Testing shows that a bias of 2 seems roughly
|
||||
// right: 3 causes too many extra clobbers, while 1 saves very few clobbers relative
|
||||
// to the number of extra stores it causes.
|
||||
if (xregs[xr].dirty)
|
||||
score += 2;
|
||||
|
||||
// If the register isn't actually needed in a physical register for a later instruction,
|
||||
// writing it back to the register file isn't quite as bad.
|
||||
if (GetRegUtilization()[preg])
|
||||
{
|
||||
// Don't look too far ahead; we don't want to have quadratic compilation times for
|
||||
// enormous block sizes!
|
||||
// This actually improves register allocation a tiny bit; I'm not sure why.
|
||||
u32 lookahead = std::min(jit->js.instructionsLeft, 64);
|
||||
// Count how many other registers are going to be used before we need this one again.
|
||||
u32 regs_in_count = CountRegsIn(preg, lookahead).Count();
|
||||
// Totally ad-hoc heuristic to bias based on how many other registers we'll need
|
||||
// before this one gets used again.
|
||||
score += 1 + 2 * (5 - log2f(1 + (float)regs_in_count));
|
||||
}
|
||||
|
||||
return score;
|
||||
return m_regs[preg].away && m_regs[preg].location.IsSimpleReg();
|
||||
}
|
||||
|
||||
X64Reg RegCache::GetFreeXReg()
|
||||
|
|
@ -144,7 +279,7 @@ X64Reg RegCache::GetFreeXReg()
|
|||
for (size_t i = 0; i < aCount; i++)
|
||||
{
|
||||
X64Reg xr = aOrder[i];
|
||||
if (!xregs[xr].locked && xregs[xr].free)
|
||||
if (!m_xregs[xr].locked && m_xregs[xr].free)
|
||||
{
|
||||
return xr;
|
||||
}
|
||||
|
|
@ -158,8 +293,8 @@ X64Reg RegCache::GetFreeXReg()
|
|||
for (size_t i = 0; i < aCount; i++)
|
||||
{
|
||||
X64Reg xreg = (X64Reg)aOrder[i];
|
||||
size_t preg = xregs[xreg].ppcReg;
|
||||
if (xregs[xreg].locked || regs[preg].locked)
|
||||
size_t preg = m_xregs[xreg].ppcReg;
|
||||
if (m_xregs[xreg].locked || m_regs[preg].locked)
|
||||
continue;
|
||||
float score = ScoreRegister(xreg);
|
||||
if (score < min_score)
|
||||
|
|
@ -181,232 +316,45 @@ X64Reg RegCache::GetFreeXReg()
|
|||
return INVALID_REG;
|
||||
}
|
||||
|
||||
void RegCache::FlushR(X64Reg reg)
|
||||
{
|
||||
if (reg >= xregs.size())
|
||||
PanicAlert("Flushing non existent reg");
|
||||
if (!xregs[reg].free)
|
||||
{
|
||||
StoreFromRegister(xregs[reg].ppcReg);
|
||||
}
|
||||
}
|
||||
|
||||
int RegCache::SanityCheck() const
|
||||
{
|
||||
for (size_t i = 0; i < regs.size(); i++)
|
||||
{
|
||||
if (regs[i].away)
|
||||
{
|
||||
if (regs[i].location.IsSimpleReg())
|
||||
{
|
||||
Gen::X64Reg simple = regs[i].location.GetSimpleReg();
|
||||
if (xregs[simple].locked)
|
||||
return 1;
|
||||
if (xregs[simple].ppcReg != i)
|
||||
return 2;
|
||||
}
|
||||
else if (regs[i].location.IsImm())
|
||||
{
|
||||
return 3;
|
||||
}
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
void RegCache::DiscardRegContentsIfCached(size_t preg)
|
||||
{
|
||||
if (IsBound(preg))
|
||||
{
|
||||
X64Reg xr = regs[preg].location.GetSimpleReg();
|
||||
xregs[xr].free = true;
|
||||
xregs[xr].dirty = false;
|
||||
xregs[xr].ppcReg = INVALID_REG;
|
||||
regs[preg].away = false;
|
||||
regs[preg].location = GetDefaultLocation(preg);
|
||||
}
|
||||
}
|
||||
|
||||
void GPRRegCache::SetImmediate32(size_t preg, u32 immValue, bool dirty)
|
||||
{
|
||||
// "dirty" can be false to avoid redundantly flushing an immediate when
|
||||
// processing speculative constants.
|
||||
DiscardRegContentsIfCached(preg);
|
||||
regs[preg].away |= dirty;
|
||||
regs[preg].location = Imm32(immValue);
|
||||
}
|
||||
|
||||
const X64Reg* GPRRegCache::GetAllocationOrder(size_t* count)
|
||||
{
|
||||
static const X64Reg allocationOrder[] = {
|
||||
// R12, when used as base register, for example in a LEA, can generate bad code! Need to look into
|
||||
// this.
|
||||
#ifdef _WIN32
|
||||
RSI, RDI, R13, R14, R15, R8,
|
||||
R9, R10, R11, R12, RCX
|
||||
#else
|
||||
R12, R13, R14, R15, RSI, RDI,
|
||||
R8, R9, R10, R11, RCX
|
||||
#endif
|
||||
};
|
||||
*count = sizeof(allocationOrder) / sizeof(X64Reg);
|
||||
return allocationOrder;
|
||||
}
|
||||
|
||||
const X64Reg* FPURegCache::GetAllocationOrder(size_t* count)
|
||||
{
|
||||
static const X64Reg allocationOrder[] = {XMM6, XMM7, XMM8, XMM9, XMM10, XMM11, XMM12,
|
||||
XMM13, XMM14, XMM15, XMM2, XMM3, XMM4, XMM5};
|
||||
*count = sizeof(allocationOrder) / sizeof(X64Reg);
|
||||
return allocationOrder;
|
||||
}
|
||||
|
||||
OpArg GPRRegCache::GetDefaultLocation(size_t reg) const
|
||||
{
|
||||
return PPCSTATE(gpr[reg]);
|
||||
}
|
||||
|
||||
OpArg FPURegCache::GetDefaultLocation(size_t reg) const
|
||||
{
|
||||
return PPCSTATE(ps[reg][0]);
|
||||
}
|
||||
|
||||
void RegCache::KillImmediate(size_t preg, bool doLoad, bool makeDirty)
|
||||
{
|
||||
if (regs[preg].away)
|
||||
{
|
||||
if (regs[preg].location.IsImm())
|
||||
BindToRegister(preg, doLoad, makeDirty);
|
||||
else if (regs[preg].location.IsSimpleReg())
|
||||
xregs[RX(preg)].dirty |= makeDirty;
|
||||
}
|
||||
}
|
||||
|
||||
void RegCache::BindToRegister(size_t i, bool doLoad, bool makeDirty)
|
||||
{
|
||||
if (!regs[i].away || regs[i].location.IsImm())
|
||||
{
|
||||
X64Reg xr = GetFreeXReg();
|
||||
if (xregs[xr].dirty)
|
||||
PanicAlert("Xreg already dirty");
|
||||
if (xregs[xr].locked)
|
||||
PanicAlert("GetFreeXReg returned locked register");
|
||||
xregs[xr].free = false;
|
||||
xregs[xr].ppcReg = i;
|
||||
xregs[xr].dirty = makeDirty || regs[i].away;
|
||||
if (doLoad)
|
||||
LoadRegister(i, xr);
|
||||
for (size_t j = 0; j < regs.size(); j++)
|
||||
{
|
||||
if (i != j && regs[j].location.IsSimpleReg(xr))
|
||||
{
|
||||
Crash();
|
||||
}
|
||||
}
|
||||
regs[i].away = true;
|
||||
regs[i].location = ::Gen::R(xr);
|
||||
}
|
||||
else
|
||||
{
|
||||
// reg location must be simplereg; memory locations
|
||||
// and immediates are taken care of above.
|
||||
xregs[RX(i)].dirty |= makeDirty;
|
||||
}
|
||||
|
||||
if (xregs[RX(i)].locked)
|
||||
{
|
||||
PanicAlert("Seriously WTF, this reg should have been flushed");
|
||||
}
|
||||
}
|
||||
|
||||
void RegCache::StoreFromRegister(size_t i, FlushMode mode)
|
||||
{
|
||||
if (regs[i].away)
|
||||
{
|
||||
bool doStore;
|
||||
if (regs[i].location.IsSimpleReg())
|
||||
{
|
||||
X64Reg xr = RX(i);
|
||||
doStore = xregs[xr].dirty;
|
||||
if (mode == FLUSH_ALL)
|
||||
{
|
||||
xregs[xr].free = true;
|
||||
xregs[xr].ppcReg = INVALID_REG;
|
||||
xregs[xr].dirty = false;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
// must be immediate - do nothing
|
||||
doStore = true;
|
||||
}
|
||||
OpArg newLoc = GetDefaultLocation(i);
|
||||
if (doStore)
|
||||
StoreRegister(i, newLoc);
|
||||
if (mode == FLUSH_ALL)
|
||||
{
|
||||
regs[i].location = newLoc;
|
||||
regs[i].away = false;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void GPRRegCache::LoadRegister(size_t preg, X64Reg newLoc)
|
||||
{
|
||||
emit->MOV(32, ::Gen::R(newLoc), regs[preg].location);
|
||||
}
|
||||
|
||||
void GPRRegCache::StoreRegister(size_t preg, const OpArg& newLoc)
|
||||
{
|
||||
emit->MOV(32, newLoc, regs[preg].location);
|
||||
}
|
||||
|
||||
void FPURegCache::LoadRegister(size_t preg, X64Reg newLoc)
|
||||
{
|
||||
emit->MOVAPD(newLoc, regs[preg].location);
|
||||
}
|
||||
|
||||
void FPURegCache::StoreRegister(size_t preg, const OpArg& newLoc)
|
||||
{
|
||||
emit->MOVAPD(newLoc, regs[preg].location.GetSimpleReg());
|
||||
}
|
||||
|
||||
void RegCache::Flush(FlushMode mode, BitSet32 regsToFlush)
|
||||
{
|
||||
for (size_t i = 0; i < xregs.size(); i++)
|
||||
{
|
||||
if (xregs[i].locked)
|
||||
PanicAlert("Someone forgot to unlock X64 reg %zu", i);
|
||||
}
|
||||
|
||||
for (unsigned int i : regsToFlush)
|
||||
{
|
||||
if (regs[i].locked)
|
||||
{
|
||||
PanicAlert("Someone forgot to unlock PPC reg %u (X64 reg %i).", i, RX(i));
|
||||
}
|
||||
|
||||
if (regs[i].away)
|
||||
{
|
||||
if (regs[i].location.IsSimpleReg() || regs[i].location.IsImm())
|
||||
{
|
||||
StoreFromRegister(i, mode);
|
||||
}
|
||||
else
|
||||
{
|
||||
_assert_msg_(DYNA_REC, 0, "Jit64 - Flush unhandled case, reg %u PC: %08x", i, PC);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
int RegCache::NumFreeRegisters()
|
||||
{
|
||||
int count = 0;
|
||||
size_t aCount;
|
||||
const X64Reg* aOrder = GetAllocationOrder(&aCount);
|
||||
for (size_t i = 0; i < aCount; i++)
|
||||
if (!xregs[aOrder[i]].locked && xregs[aOrder[i]].free)
|
||||
if (!m_xregs[aOrder[i]].locked && m_xregs[aOrder[i]].free)
|
||||
count++;
|
||||
return count;
|
||||
}
|
||||
|
||||
// Estimate roughly how bad it would be to de-allocate this register. Higher score
|
||||
// means more bad.
|
||||
float RegCache::ScoreRegister(X64Reg xr)
|
||||
{
|
||||
size_t preg = m_xregs[xr].ppcReg;
|
||||
float score = 0;
|
||||
|
||||
// If it's not dirty, we don't need a store to write it back to the register file, so
|
||||
// bias a bit against dirty registers. Testing shows that a bias of 2 seems roughly
|
||||
// right: 3 causes too many extra clobbers, while 1 saves very few clobbers relative
|
||||
// to the number of extra stores it causes.
|
||||
if (m_xregs[xr].dirty)
|
||||
score += 2;
|
||||
|
||||
// If the register isn't actually needed in a physical register for a later instruction,
|
||||
// writing it back to the register file isn't quite as bad.
|
||||
if (GetRegUtilization()[preg])
|
||||
{
|
||||
// Don't look too far ahead; we don't want to have quadratic compilation times for
|
||||
// enormous block sizes!
|
||||
// This actually improves register allocation a tiny bit; I'm not sure why.
|
||||
u32 lookahead = std::min(m_jit.js.instructionsLeft, 64);
|
||||
// Count how many other registers are going to be used before we need this one again.
|
||||
u32 regs_in_count = CountRegsIn(preg, lookahead).Count();
|
||||
// Totally ad-hoc heuristic to bias based on how many other registers we'll need
|
||||
// before this one gets used again.
|
||||
score += 1 + 2 * (5 - log2f(1 + (float)regs_in_count));
|
||||
}
|
||||
|
||||
return score;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -10,6 +10,8 @@
|
|||
#include "Common/x64Emitter.h"
|
||||
#include "Core/PowerPC/PPCAnalyst.h"
|
||||
|
||||
class Jit64;
|
||||
|
||||
enum FlushMode
|
||||
{
|
||||
FLUSH_ALL,
|
||||
|
|
@ -31,55 +33,31 @@ struct X64CachedReg
|
|||
bool locked;
|
||||
};
|
||||
|
||||
typedef int XReg;
|
||||
typedef int PReg;
|
||||
|
||||
#define NUMXREGS 16
|
||||
|
||||
class RegCache
|
||||
{
|
||||
protected:
|
||||
std::array<PPCCachedReg, 32> regs;
|
||||
std::array<X64CachedReg, NUMXREGS> xregs;
|
||||
|
||||
virtual const Gen::X64Reg* GetAllocationOrder(size_t* count) = 0;
|
||||
|
||||
virtual BitSet32 GetRegUtilization() = 0;
|
||||
virtual BitSet32 CountRegsIn(size_t preg, u32 lookahead) = 0;
|
||||
|
||||
Gen::XEmitter* emit;
|
||||
|
||||
float ScoreRegister(Gen::X64Reg xreg);
|
||||
|
||||
public:
|
||||
RegCache();
|
||||
virtual ~RegCache() {}
|
||||
static constexpr size_t NUM_XREGS = 16;
|
||||
|
||||
explicit RegCache(Jit64& jit);
|
||||
virtual ~RegCache() = default;
|
||||
|
||||
virtual void StoreRegister(size_t preg, const Gen::OpArg& new_loc) = 0;
|
||||
virtual void LoadRegister(size_t preg, Gen::X64Reg new_loc) = 0;
|
||||
virtual Gen::OpArg GetDefaultLocation(size_t reg) const = 0;
|
||||
|
||||
void Start();
|
||||
|
||||
void DiscardRegContentsIfCached(size_t preg);
|
||||
void SetEmitter(Gen::XEmitter* emitter) { emit = emitter; }
|
||||
void FlushR(Gen::X64Reg reg);
|
||||
void FlushR(Gen::X64Reg reg, Gen::X64Reg reg2)
|
||||
{
|
||||
FlushR(reg);
|
||||
FlushR(reg2);
|
||||
}
|
||||
|
||||
void FlushLockX(Gen::X64Reg reg)
|
||||
{
|
||||
FlushR(reg);
|
||||
LockX(reg);
|
||||
}
|
||||
void FlushLockX(Gen::X64Reg reg1, Gen::X64Reg reg2)
|
||||
{
|
||||
FlushR(reg1);
|
||||
FlushR(reg2);
|
||||
LockX(reg1);
|
||||
LockX(reg2);
|
||||
}
|
||||
void SetEmitter(Gen::XEmitter* emitter);
|
||||
|
||||
void Flush(FlushMode mode = FLUSH_ALL, BitSet32 regsToFlush = BitSet32::AllTrue(32));
|
||||
void Flush(PPCAnalyst::CodeOp* op) { Flush(); }
|
||||
|
||||
void FlushR(Gen::X64Reg reg);
|
||||
void FlushR(Gen::X64Reg reg, Gen::X64Reg reg2);
|
||||
|
||||
void FlushLockX(Gen::X64Reg reg);
|
||||
void FlushLockX(Gen::X64Reg reg1, Gen::X64Reg reg2);
|
||||
|
||||
int SanityCheck() const;
|
||||
void KillImmediate(size_t preg, bool doLoad, bool makeDirty);
|
||||
|
||||
|
|
@ -87,19 +65,9 @@ public:
|
|||
// read only will not set dirty flag
|
||||
void BindToRegister(size_t preg, bool doLoad = true, bool makeDirty = true);
|
||||
void StoreFromRegister(size_t preg, FlushMode mode = FLUSH_ALL);
|
||||
virtual void StoreRegister(size_t preg, const Gen::OpArg& newLoc) = 0;
|
||||
virtual void LoadRegister(size_t preg, Gen::X64Reg newLoc) = 0;
|
||||
|
||||
const Gen::OpArg& R(size_t preg) const { return regs[preg].location; }
|
||||
Gen::X64Reg RX(size_t preg) const
|
||||
{
|
||||
if (IsBound(preg))
|
||||
return regs[preg].location.GetSimpleReg();
|
||||
|
||||
PanicAlert("Unbound register - %zu", preg);
|
||||
return Gen::INVALID_REG;
|
||||
}
|
||||
virtual Gen::OpArg GetDefaultLocation(size_t reg) const = 0;
|
||||
const Gen::OpArg& R(size_t preg) const;
|
||||
Gen::X64Reg RX(size_t preg) const;
|
||||
|
||||
// Register locking.
|
||||
|
||||
|
|
@ -107,7 +75,7 @@ public:
|
|||
template <typename T>
|
||||
void Lock(T p)
|
||||
{
|
||||
regs[p].locked = true;
|
||||
m_regs[p].locked = true;
|
||||
}
|
||||
template <typename T, typename... Args>
|
||||
void Lock(T first, Args... args)
|
||||
|
|
@ -120,9 +88,9 @@ public:
|
|||
template <typename T>
|
||||
void LockX(T x)
|
||||
{
|
||||
if (xregs[x].locked)
|
||||
if (m_xregs[x].locked)
|
||||
PanicAlert("RegCache: x %i already locked!", x);
|
||||
xregs[x].locked = true;
|
||||
m_xregs[x].locked = true;
|
||||
}
|
||||
template <typename T, typename... Args>
|
||||
void LockX(T first, Args... args)
|
||||
|
|
@ -134,9 +102,9 @@ public:
|
|||
template <typename T>
|
||||
void UnlockX(T x)
|
||||
{
|
||||
if (!xregs[x].locked)
|
||||
if (!m_xregs[x].locked)
|
||||
PanicAlert("RegCache: x %i already unlocked!", x);
|
||||
xregs[x].locked = false;
|
||||
m_xregs[x].locked = false;
|
||||
}
|
||||
template <typename T, typename... Args>
|
||||
void UnlockX(T first, Args... args)
|
||||
|
|
@ -148,31 +116,22 @@ public:
|
|||
void UnlockAll();
|
||||
void UnlockAllX();
|
||||
|
||||
bool IsFreeX(size_t xreg) const { return xregs[xreg].free && !xregs[xreg].locked; }
|
||||
bool IsBound(size_t preg) const { return regs[preg].away && regs[preg].location.IsSimpleReg(); }
|
||||
bool IsFreeX(size_t xreg) const;
|
||||
bool IsBound(size_t preg) const;
|
||||
|
||||
Gen::X64Reg GetFreeXReg();
|
||||
int NumFreeRegisters();
|
||||
};
|
||||
|
||||
class GPRRegCache final : public RegCache
|
||||
{
|
||||
public:
|
||||
void StoreRegister(size_t preg, const Gen::OpArg& newLoc) override;
|
||||
void LoadRegister(size_t preg, Gen::X64Reg newLoc) override;
|
||||
Gen::OpArg GetDefaultLocation(size_t reg) const override;
|
||||
const Gen::X64Reg* GetAllocationOrder(size_t* count) override;
|
||||
void SetImmediate32(size_t preg, u32 immValue, bool dirty = true);
|
||||
BitSet32 GetRegUtilization() override;
|
||||
BitSet32 CountRegsIn(size_t preg, u32 lookahead) override;
|
||||
};
|
||||
protected:
|
||||
virtual const Gen::X64Reg* GetAllocationOrder(size_t* count) = 0;
|
||||
|
||||
class FPURegCache final : public RegCache
|
||||
{
|
||||
public:
|
||||
void StoreRegister(size_t preg, const Gen::OpArg& newLoc) override;
|
||||
void LoadRegister(size_t preg, Gen::X64Reg newLoc) override;
|
||||
const Gen::X64Reg* GetAllocationOrder(size_t* count) override;
|
||||
Gen::OpArg GetDefaultLocation(size_t reg) const override;
|
||||
BitSet32 GetRegUtilization() override;
|
||||
BitSet32 CountRegsIn(size_t preg, u32 lookahead) override;
|
||||
virtual BitSet32 GetRegUtilization() = 0;
|
||||
virtual BitSet32 CountRegsIn(size_t preg, u32 lookahead) = 0;
|
||||
|
||||
float ScoreRegister(Gen::X64Reg xreg);
|
||||
|
||||
Jit64& m_jit;
|
||||
std::array<PPCCachedReg, 32> m_regs;
|
||||
std::array<X64CachedReg, NUM_XREGS> m_xregs;
|
||||
Gen::XEmitter* m_emitter = nullptr;
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue