This release still fixed the hangs produced by fifo overflow without sacrifice performance.
For example you can test Tutorial moves at the beginning of The last history now is fluid 30/60. Shuffle2: I've delete the hacky line, I think is not necessary anymore. Additional some clean in CommandProcessor. Please test The Last Story and others games affected in the previous commits and give me a feedback.
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@ -119,6 +119,7 @@ public:
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virtual void Video_GatherPipeBursted() = 0;
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virtual void Video_GatherPipeBursted() = 0;
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virtual bool Video_IsPossibleWaitingSetDrawDone() = 0;
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virtual bool Video_IsPossibleWaitingSetDrawDone() = 0;
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virtual bool Video_IsHiWatermarkActive() = 0;
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virtual void Video_AbortFrame() = 0;
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virtual void Video_AbortFrame() = 0;
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virtual readFn16 Video_CPRead16() = 0;
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virtual readFn16 Video_CPRead16() = 0;
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@ -159,6 +160,7 @@ class VideoBackendHardware : public VideoBackend
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void Video_GatherPipeBursted();
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void Video_GatherPipeBursted();
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bool Video_IsPossibleWaitingSetDrawDone();
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bool Video_IsPossibleWaitingSetDrawDone();
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bool Video_IsHiWatermarkActive();
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void Video_AbortFrame();
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void Video_AbortFrame();
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readFn16 Video_CPRead16();
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readFn16 Video_CPRead16();
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@ -96,9 +96,10 @@ void STACKALIGN CheckGatherPipe()
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// move back the spill bytes
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// move back the spill bytes
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memmove(m_gatherPipe, m_gatherPipe + cnt, m_gatherPipeCount);
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memmove(m_gatherPipe, m_gatherPipe + cnt, m_gatherPipeCount);
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// Profile where the FIFO writes are occurring.
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// Profile where the FIFO writes are occurring.
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if (m_gatherPipeCount == 0 && jit && (jit->js.fifoWriteAddresses.find(PC)) == (jit->js.fifoWriteAddresses.end()))
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if (g_video_backend->Video_IsHiWatermarkActive() && jit && (jit->js.fifoWriteAddresses.find(PC)) == (jit->js.fifoWriteAddresses.end()))
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{
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{
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jit->js.fifoWriteAddresses.insert(PC);
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jit->js.fifoWriteAddresses.insert(PC);
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@ -580,13 +580,10 @@ const u8* Jit64::DoJit(u32 em_address, PPCAnalyst::CodeBuffer *code_buf, JitBloc
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FixupBranch noExtException = J_CC(CC_Z);
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FixupBranch noExtException = J_CC(CC_Z);
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TEST(32, M((void *)&ProcessorInterface::m_InterruptCause), Imm32(ProcessorInterface::INT_CAUSE_CP));
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TEST(32, M((void *)&ProcessorInterface::m_InterruptCause), Imm32(ProcessorInterface::INT_CAUSE_CP));
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FixupBranch noCPInt = J_CC(CC_Z);
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FixupBranch noCPInt = J_CC(CC_Z);
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TEST(32, M((void *)&ProcessorInterface::m_InterruptCause), Imm32(ProcessorInterface::INT_CAUSE_VI | ProcessorInterface::INT_CAUSE_PE_TOKEN | ProcessorInterface::INT_CAUSE_PE_FINISH));
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FixupBranch clearInt = J_CC(CC_NZ);
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MOV(32, M(&PC), Imm32(ops[i].address));
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MOV(32, M(&PC), Imm32(ops[i].address));
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WriteExceptionExit();
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WriteExceptionExit();
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SetJumpTarget(clearInt);
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SetJumpTarget(noCPInt);
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SetJumpTarget(noCPInt);
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SetJumpTarget(noExtException);
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SetJumpTarget(noExtException);
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}
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}
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@ -1929,13 +1929,11 @@ static void DoWriteCode(IRBuilder* ibuild, JitIL* Jit, bool UseProfile, bool Mak
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FixupBranch noExtException = Jit->J_CC(CC_Z);
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FixupBranch noExtException = Jit->J_CC(CC_Z);
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Jit->TEST(32, M((void *)&ProcessorInterface::m_InterruptCause), Imm32(ProcessorInterface::INT_CAUSE_CP));
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Jit->TEST(32, M((void *)&ProcessorInterface::m_InterruptCause), Imm32(ProcessorInterface::INT_CAUSE_CP));
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FixupBranch noCPInt = Jit->J_CC(CC_Z);
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FixupBranch noCPInt = Jit->J_CC(CC_Z);
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Jit->TEST(32, M((void *)&ProcessorInterface::m_InterruptCause), Imm32(ProcessorInterface::INT_CAUSE_VI | ProcessorInterface::INT_CAUSE_PE_TOKEN | ProcessorInterface::INT_CAUSE_PE_FINISH));
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FixupBranch clearInt = Jit->J_CC(CC_NZ);
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Jit->MOV(32, M(&PC), Imm32(InstLoc));
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Jit->MOV(32, M(&PC), Imm32(InstLoc));
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Jit->WriteExceptionExit();
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Jit->WriteExceptionExit();
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Jit->SetJumpTarget(clearInt);
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Jit->SetJumpTarget(noCPInt);
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Jit->SetJumpTarget(noCPInt);
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Jit->SetJumpTarget(noExtException);
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Jit->SetJumpTarget(noExtException);
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break;
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break;
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@ -56,6 +56,7 @@ static bool bProcessFifoToLoWatermark = false;
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static bool bProcessFifoAllDistance = false;
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static bool bProcessFifoAllDistance = false;
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volatile bool isPossibleWaitingSetDrawDone = false;
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volatile bool isPossibleWaitingSetDrawDone = false;
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volatile bool isHiWatermarkActive = false;
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volatile bool interruptSet= false;
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volatile bool interruptSet= false;
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volatile bool interruptWaiting= false;
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volatile bool interruptWaiting= false;
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volatile bool interruptTokenWaiting = false;
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volatile bool interruptTokenWaiting = false;
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@ -85,7 +86,7 @@ void DoState(PointerWrap &p)
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p.Do(bProcessFifoToLoWatermark);
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p.Do(bProcessFifoToLoWatermark);
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p.Do(bProcessFifoAllDistance);
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p.Do(bProcessFifoAllDistance);
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p.Do(isHiWatermarkActive);
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p.Do(isPossibleWaitingSetDrawDone);
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p.Do(isPossibleWaitingSetDrawDone);
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p.Do(interruptSet);
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p.Do(interruptSet);
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p.Do(interruptWaiting);
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p.Do(interruptWaiting);
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@ -133,6 +134,7 @@ void Init()
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bProcessFifoToLoWatermark = false;
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bProcessFifoToLoWatermark = false;
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bProcessFifoAllDistance = false;
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bProcessFifoAllDistance = false;
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isPossibleWaitingSetDrawDone = false;
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isPossibleWaitingSetDrawDone = false;
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isHiWatermarkActive = false;
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et_UpdateInterrupts = CoreTiming::RegisterEvent("UpdateInterrupts", UpdateInterrupts_Wrapper);
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et_UpdateInterrupts = CoreTiming::RegisterEvent("UpdateInterrupts", UpdateInterrupts_Wrapper);
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}
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}
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@ -141,7 +143,6 @@ void Read16(u16& _rReturnValue, const u32 _Address)
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{
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{
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INFO_LOG(COMMANDPROCESSOR, "(r): 0x%08x", _Address);
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INFO_LOG(COMMANDPROCESSOR, "(r): 0x%08x", _Address);
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ProcessFifoEvents();
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switch (_Address & 0xFFF)
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switch (_Address & 0xFFF)
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{
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{
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case STATUS_REGISTER:
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case STATUS_REGISTER:
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@ -409,7 +410,6 @@ void Write16(const u16 _Value, const u32 _Address)
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if (!IsOnThread())
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if (!IsOnThread())
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RunGpu();
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RunGpu();
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ProcessFifoEvents();
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}
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}
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void Read32(u32& _rReturnValue, const u32 _Address)
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void Read32(u32& _rReturnValue, const u32 _Address)
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@ -425,7 +425,6 @@ void Write32(const u32 _Data, const u32 _Address)
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void STACKALIGN GatherPipeBursted()
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void STACKALIGN GatherPipeBursted()
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{
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{
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ProcessFifoEvents();
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// if we aren't linked, we don't care about gather pipe data
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// if we aren't linked, we don't care about gather pipe data
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if (!m_CPCtrlReg.GPLinkEnable)
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if (!m_CPCtrlReg.GPLinkEnable)
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{
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{
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@ -487,17 +486,18 @@ void AbortFrame()
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void SetOverflowStatusFromGatherPipe()
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void SetOverflowStatusFromGatherPipe()
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{
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{
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if (!fifo.bFF_HiWatermarkInt) return;
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fifo.bFF_HiWatermark = (fifo.CPReadWriteDistance > fifo.CPHiWatermark);
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fifo.bFF_HiWatermark = (fifo.CPReadWriteDistance > fifo.CPHiWatermark);
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fifo.bFF_LoWatermark = (fifo.CPReadWriteDistance < fifo.CPLoWatermark);
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isHiWatermarkActive = fifo.bFF_HiWatermark && fifo.bFF_HiWatermarkInt && m_CPCtrlReg.GPReadEnable;
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bool interrupt = fifo.bFF_HiWatermark && fifo.bFF_HiWatermarkInt &&
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if (isHiWatermarkActive)
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m_CPCtrlReg.GPLinkEnable && m_CPCtrlReg.GPReadEnable;
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{
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interruptSet = true;
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if (interrupt != interruptSet && interrupt)
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INFO_LOG(COMMANDPROCESSOR,"Interrupt set");
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CommandProcessor::UpdateInterrupts(true);
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ProcessorInterface::SetInterrupt(INT_CAUSE_CP, true);
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}
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}
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}
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void SetCpStatus()
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void SetCpStatus()
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@ -505,7 +505,7 @@ void SetCpStatus()
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// overflow & underflow check
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// overflow & underflow check
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fifo.bFF_HiWatermark = (fifo.CPReadWriteDistance > fifo.CPHiWatermark);
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fifo.bFF_HiWatermark = (fifo.CPReadWriteDistance > fifo.CPHiWatermark);
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fifo.bFF_LoWatermark = (fifo.CPReadWriteDistance < fifo.CPLoWatermark);
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fifo.bFF_LoWatermark = (fifo.CPReadWriteDistance < fifo.CPLoWatermark);
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// breakpoint
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// breakpoint
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if (fifo.bFF_BPEnable)
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if (fifo.bFF_BPEnable)
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@ -540,13 +540,18 @@ void SetCpStatus()
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bool interrupt = (bpInt || ovfInt || undfInt) && m_CPCtrlReg.GPReadEnable;
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bool interrupt = (bpInt || ovfInt || undfInt) && m_CPCtrlReg.GPReadEnable;
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isHiWatermarkActive = ovfInt && m_CPCtrlReg.GPReadEnable;
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if (interrupt != interruptSet && !interruptWaiting)
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if (interrupt != interruptSet && !interruptWaiting)
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{
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{
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u64 userdata = interrupt?1:0;
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u64 userdata = interrupt?1:0;
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if (IsOnThread())
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if (IsOnThread())
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{
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{
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interruptWaiting = true;
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if(!interrupt || bpInt || undfInt)
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CommandProcessor::UpdateInterruptsFromVideoBackend(userdata);
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{
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interruptWaiting = true;
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CommandProcessor::UpdateInterruptsFromVideoBackend(userdata);
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}
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}
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}
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else
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else
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CommandProcessor::UpdateInterrupts(userdata);
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CommandProcessor::UpdateInterrupts(userdata);
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@ -631,8 +636,8 @@ void SetCpControlRegister()
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ProcessorInterface::Fifo_CPUEnd = fifo.CPEnd;
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ProcessorInterface::Fifo_CPUEnd = fifo.CPEnd;
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}
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}
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// If overflown happens process the fifo to LoWatemark
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// If overflown happens process the fifo to LoWatemark
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if (bProcessFifoToLoWatermark)
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//if (bProcessFifoToLoWatermark)
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ProcessFifoToLoWatermark();
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// ProcessFifoToLoWatermark();
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if(fifo.bFF_GPReadEnable && !m_CPCtrlReg.GPReadEnable)
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if(fifo.bFF_GPReadEnable && !m_CPCtrlReg.GPReadEnable)
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{
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{
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@ -31,6 +31,7 @@ namespace CommandProcessor
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extern SCPFifoStruct fifo; //This one is shared between gfx thread and emulator thread.
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extern SCPFifoStruct fifo; //This one is shared between gfx thread and emulator thread.
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extern volatile bool isPossibleWaitingSetDrawDone; //This one is used for sync gfx thread and emulator thread.
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extern volatile bool isPossibleWaitingSetDrawDone; //This one is used for sync gfx thread and emulator thread.
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extern volatile bool isHiWatermarkActive;
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extern volatile bool interruptSet;
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extern volatile bool interruptSet;
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extern volatile bool interruptWaiting;
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extern volatile bool interruptWaiting;
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extern volatile bool interruptTokenWaiting;
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extern volatile bool interruptTokenWaiting;
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@ -250,6 +250,11 @@ bool VideoBackendHardware::Video_IsPossibleWaitingSetDrawDone()
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return CommandProcessor::isPossibleWaitingSetDrawDone;
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return CommandProcessor::isPossibleWaitingSetDrawDone;
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}
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}
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bool VideoBackendHardware::Video_IsHiWatermarkActive()
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{
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return CommandProcessor::isHiWatermarkActive;
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}
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void VideoBackendHardware::Video_AbortFrame()
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void VideoBackendHardware::Video_AbortFrame()
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{
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{
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CommandProcessor::AbortFrame();
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CommandProcessor::AbortFrame();
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@ -180,7 +180,6 @@ void Init()
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void Read16(u16& _uReturnValue, const u32 _iAddress)
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void Read16(u16& _uReturnValue, const u32 _iAddress)
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{
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{
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DEBUG_LOG(PIXELENGINE, "(r16) 0x%08x", _iAddress);
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DEBUG_LOG(PIXELENGINE, "(r16) 0x%08x", _iAddress);
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CommandProcessor::ProcessFifoEvents();
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switch (_iAddress & 0xFFF)
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switch (_iAddress & 0xFFF)
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{
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{
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// CPU Direct Access EFB Raster State Config
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// CPU Direct Access EFB Raster State Config
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@ -334,7 +333,6 @@ void Write16(const u16 _iValue, const u32 _iAddress)
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break;
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break;
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}
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}
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CommandProcessor::ProcessFifoEvents();
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}
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}
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void Write32(const u32 _iValue, const u32 _iAddress)
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void Write32(const u32 _iValue, const u32 _iAddress)
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@ -215,6 +215,12 @@ bool VideoSoftware::Video_IsPossibleWaitingSetDrawDone(void)
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return false;
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return false;
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}
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}
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bool VideoSoftware::Video_IsHiWatermarkActive(void)
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{
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return false;
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}
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void VideoSoftware::Video_AbortFrame(void)
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void VideoSoftware::Video_AbortFrame(void)
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{
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{
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}
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}
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@ -36,7 +36,7 @@ class VideoSoftware : public VideoBackend
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void Video_SetRendering(bool bEnabled);
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void Video_SetRendering(bool bEnabled);
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void Video_GatherPipeBursted();
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void Video_GatherPipeBursted();
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bool Video_IsHiWatermarkActive();
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bool Video_IsPossibleWaitingSetDrawDone();
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bool Video_IsPossibleWaitingSetDrawDone();
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void Video_AbortFrame();
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void Video_AbortFrame();
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