Core: Clean up body/brace placements in JitArm32

Source/Core/Core/PowerPC/JitArm32/Jit.cpp

@@ -108,12 +108,14 @@ static void ImHere()
 		}
 		fprintf(f.GetHandle(), "%08x\n", PC);
 	}
+
 	if (been_here.find(PC) != been_here.end())
 	{
 		been_here.find(PC)->second++;
 		if ((been_here.find(PC)->second) & 1023)
 			return;
 	}
+
 	DEBUG_LOG(DYNA_REC, "I'm here - PC = %08x , LR = %08x", PC, LR);
 	been_here[PC] = 1;
 }
@@ -374,8 +376,10 @@ const u8* JitArm::DoJit(u32 em_address, PPCAnalyst::CodeBuffer *code_buf, JitBlo
 		SetCC();
 		gpr.Unlock(A, C);
 	}
+
 	// Conditionally add profiling code.
-	if (Profiler::g_ProfileBlocks) {
+	if (Profiler::g_ProfileBlocks)
+	{
 		ARMReg rA = gpr.GetReg();
 		ARMReg rB = gpr.GetReg();
 		MOVI2R(rA, (u32)&b->runCount); // Load in to register
@@ -415,7 +419,8 @@ const u8* JitArm::DoJit(u32 em_address, PPCAnalyst::CodeBuffer *code_buf, JitBlo
 			// WARNING - cmp->branch merging will screw this up.
 			js.isLastInstruction = true;
 			js.next_inst = 0;
-			if (Profiler::g_ProfileBlocks) {
+			if (Profiler::g_ProfileBlocks)
+			{
 				// CAUTION!!! push on stack regs you use, do your stuff, then pop
 				PROFILER_VPUSH;
 				// get end tic
@@ -431,6 +436,7 @@ const u8* JitArm::DoJit(u32 em_address, PPCAnalyst::CodeBuffer *code_buf, JitBlo
 			js.next_inst = ops[i + 1].inst;
 			js.next_compilerPC = ops[i + 1].address;
 		}
+
 		if (jo.optimizeGatherPipe && js.fifoBytesThisBlock >= 32)
 		{
 			js.fifoBytesThisBlock -= 32;
@@ -438,6 +444,7 @@ const u8* JitArm::DoJit(u32 em_address, PPCAnalyst::CodeBuffer *code_buf, JitBlo
 			QuickCallFunction(R14, (void*)&GPFifo::CheckGatherPipe);
 			POP(4, R0, R1, R2, R3);
 		}
+
 		if (Core::g_CoreStartupParameter.bEnableDebugging)
 		{
 			// Add run count
@@ -457,6 +464,7 @@ const u8* JitArm::DoJit(u32 em_address, PPCAnalyst::CodeBuffer *code_buf, JitBlo
 			fpr.Unlock(VA);
 			fpr.Unlock(VB);
 		}
+
 		if (!ops[i].skip)
 		{
 				PrintDebug(ops[i].inst, DEBUG_OUTPUT);
@@ -474,6 +482,7 @@ const u8* JitArm::DoJit(u32 em_address, PPCAnalyst::CodeBuffer *code_buf, JitBlo
 				}
 		}
 	}
+
 	if (code_block.m_memory_exception)
 		BKPT(0x500);
 

Source/Core/Core/PowerPC/JitArm32/Jit.h

@@ -74,18 +74,22 @@ public:
 
 	void ClearCache();
 
-	const u8 *GetDispatcher() {
+	const u8 *GetDispatcher()
+	{
 		return asm_routines.dispatcher;
 	}
-	CommonAsmRoutinesBase *GetAsmRoutines() {
+
+	CommonAsmRoutinesBase *GetAsmRoutines()
+	{
 		return &asm_routines;
 	}
 
-	const char *GetName() {
+	const char *GetName()
+	{
 		return "JITARM";
 	}
-	// Run!
 
+	// Run!
 	void Run();
 	void SingleStep();
 

Source/Core/Core/PowerPC/JitArm32/JitArmCache.cpp

@@ -16,20 +16,21 @@
 
 using namespace ArmGen;
 
-	void JitArmBlockCache::WriteLinkBlock(u8* location, const u8* address)
+void JitArmBlockCache::WriteLinkBlock(u8* location, const u8* address)
-	{
+{
 	ARMXEmitter emit(location);
 	emit.B(address);
 	emit.FlushIcache();
-	}
+}
-	void JitArmBlockCache::WriteDestroyBlock(const u8* location, u32 address)
+
-	{
+void JitArmBlockCache::WriteDestroyBlock(const u8* location, u32 address)
+{
 	ARMXEmitter emit((u8 *)location);
 	emit.MOVI2R(R11, address);
 	emit.MOVI2R(R12, (u32)jit->GetAsmRoutines()->dispatcher);
 	emit.STR(R11, R9, PPCSTATE_OFF(pc));
 	emit.B(R12);
 	emit.FlushIcache();
-	}
+}
 
 

Source/Core/Core/PowerPC/JitArm32/JitArm_Branch.cpp

@@ -97,10 +97,12 @@ void JitArm::bx(UGeckoInstruction inst)
 		STR(rA, R9, PPCSTATE_OFF(spr[SPR_LR]));
 		//ARMABI_MOVI2M((u32)&LR, js.compilerPC + 4);
 	}
+
 	// If this is not the last instruction of a block,
 	// we will skip the rest process.
 	// Because PPCAnalyst::Flatten() merged the blocks.
-	if (!js.isLastInstruction) {
+	if (!js.isLastInstruction)
+	{
 		return;
 	}
 
@@ -231,7 +233,8 @@ void JitArm::bcctrx(UGeckoInstruction inst)
 		LDR(rA, R9, PPCSTATE_OFF(spr[SPR_CTR]));
 		BIC(rA, rA, 0x3);
 
-		if (inst.LK_3){
+		if (inst.LK_3)
+		{
 			u32 Jumpto = js.compilerPC + 4;
 			MOVI2R(rB, Jumpto);
 			STR(rB, R9, PPCSTATE_OFF(spr[SPR_LR]));
@@ -285,7 +288,8 @@ void JitArm::bclrx(UGeckoInstruction inst)
 	//AND(32, R(EAX), Imm32(0xFFFFFFFC));
 	LDR(rA, R9, PPCSTATE_OFF(spr[SPR_LR]));
 	BIC(rA, rA, 0x3);
-	if (inst.LK){
+	if (inst.LK)
+	{
 		u32 Jumpto = js.compilerPC + 4;
 		MOVI2R(rB, Jumpto);
 		STR(rB, R9, PPCSTATE_OFF(spr[SPR_LR]));

Source/Core/Core/PowerPC/JitArm32/JitArm_FloatingPoint.cpp

@@ -117,7 +117,8 @@ void JitArm::fctiwx(UGeckoInstruction inst)
 	NEONXEmitter nemit(this);
 	nemit.VORR(vD, vD, V0);
 
-	if (inst.Rc) Helper_UpdateCR1(fpscrReg, rA);
+	if (inst.Rc)
+		Helper_UpdateCR1(fpscrReg, rA);
 
 	STR(fpscrReg, R9, PPCSTATE_OFF(fpscr));
 	gpr.Unlock(rA);
@@ -197,7 +198,8 @@ void JitArm::fctiwzx(UGeckoInstruction inst)
 	NEONXEmitter nemit(this);
 	nemit.VORR(vD, vD, V0);
 
-	if (inst.Rc) Helper_UpdateCR1(fpscrReg, rA);
+	if (inst.Rc)
+		Helper_UpdateCR1(fpscrReg, rA);
 
 	STR(fpscrReg, R9, PPCSTATE_OFF(fpscr));
 	gpr.Unlock(rA);

Source/Core/Core/PowerPC/JitArm32/JitArm_Integer.cpp

@@ -14,7 +14,8 @@
 #include "Core/PowerPC/JitArm32/JitAsm.h"
 #include "Core/PowerPC/JitArm32/JitRegCache.h"
 
-void JitArm::ComputeRC(ARMReg value, int cr) {
+void JitArm::ComputeRC(ARMReg value, int cr)
+{
 	ARMReg rB = gpr.GetReg();
 
 	Operand2 ASRReg(value, ST_ASR, 31);
@@ -25,7 +26,9 @@ void JitArm::ComputeRC(ARMReg value, int cr) {
 
 	gpr.Unlock(rB);
 }
-void JitArm::ComputeRC(s32 value, int cr) {
+
+void JitArm::ComputeRC(s32 value, int cr)
+{
 	ARMReg rB = gpr.GetReg();
 
 	Operand2 ASRReg(rB, ST_ASR, 31);
@@ -51,6 +54,7 @@ void JitArm::ComputeCarry()
 	STR(tmp, R9, PPCSTATE_OFF(spr[SPR_XER]));
 	gpr.Unlock(tmp);
 }
+
 void JitArm::ComputeCarry(bool Carry)
 {
 	ARMReg tmp = gpr.GetReg();
@@ -162,12 +166,35 @@ void JitArm::subfic(UGeckoInstruction inst)
 	// This instruction has no RC flag
 }
 
-u32 Add(u32 a, u32 b) {return a + b;}
+u32 Add(u32 a, u32 b)
-u32 Sub(u32 a, u32 b) {return a - b;}
+{
-u32 Mul(u32 a, u32 b) {return a * b;}
+	return a + b;
-u32 Or (u32 a, u32 b) {return a | b;}
+}
-u32 And(u32 a, u32 b) {return a & b;}
+
-u32 Xor(u32 a, u32 b) {return a ^ b;}
+u32 Sub(u32 a, u32 b)
+{
+	return a - b;
+}
+
+u32 Mul(u32 a, u32 b)
+{
+	return a * b;
+}
+
+u32 Or (u32 a, u32 b)
+{
+	return a | b;
+}
+
+u32 And(u32 a, u32 b)
+{
+	return a & b;
+}
+
+u32 Xor(u32 a, u32 b)
+{
+	return a ^ b;
+}
 
 void JitArm::arith(UGeckoInstruction inst)
 {
@@ -410,8 +437,13 @@ void JitArm::arith(UGeckoInstruction inst)
 				}
 			break;
 		}
-		if (carry) ComputeCarry(hasCarry);
+
-		if (Rc) ComputeRC(gpr.GetImm(dest), 0);
+		if (carry)
+			ComputeCarry(hasCarry);
+
+		if (Rc)
+			ComputeRC(gpr.GetImm(dest), 0);
+
 		return;
 	}
 
@@ -452,7 +484,9 @@ void JitArm::arith(UGeckoInstruction inst)
 				gpr.Unlock(rA);
 			}
 			else
+			{
 				gpr.SetImmediate(d, Imm[1]);
+			}
 		break;
 		case 24:
 		case 25:
@@ -603,8 +637,12 @@ void JitArm::arith(UGeckoInstruction inst)
 			}
 		break;
 	}
-	if (carry) ComputeCarry();
+
-	if (Rc) ComputeRC(gpr.R(dest));
+	if (carry)
+		ComputeCarry();
+
+	if (Rc)
+		ComputeRC(gpr.R(dest));
 }
 
 void JitArm::addex(UGeckoInstruction inst)
@@ -623,7 +661,10 @@ void JitArm::addex(UGeckoInstruction inst)
 	GetCarryAndClear(rA);
 	ADDS(RD, RA, RB);
 	FinalizeCarry(rA);
-	if (inst.Rc) ComputeRC(RD);
+
+	if (inst.Rc)
+		ComputeRC(RD);
+
 	gpr.Unlock(rA);
 }
 
@@ -652,7 +693,9 @@ void JitArm::mulhwux(UGeckoInstruction inst)
 	ARMReg RD = gpr.R(d);
 	ARMReg rA = gpr.GetReg(false);
 	UMULL(rA, RD, RA, RB);
-	if (inst.Rc) ComputeRC(RD);
+
+	if (inst.Rc)
+		ComputeRC(RD);
 }
 
 void JitArm::extshx(UGeckoInstruction inst)
@@ -664,7 +707,10 @@ void JitArm::extshx(UGeckoInstruction inst)
 	if (gpr.IsImm(s))
 	{
 		gpr.SetImmediate(a, (u32)(s32)(s16)gpr.GetImm(s));
-		if (inst.Rc) ComputeRC(gpr.GetImm(a), 0);
+
+		if (inst.Rc)
+			ComputeRC(gpr.GetImm(a), 0);
+
 		return;
 	}
 	ARMReg rA = gpr.R(a);
@@ -682,7 +728,10 @@ void JitArm::extsbx(UGeckoInstruction inst)
 	if (gpr.IsImm(s))
 	{
 		gpr.SetImmediate(a, (u32)(s32)(s8)gpr.GetImm(s));
-		if (inst.Rc) ComputeRC(gpr.GetImm(a), 0);
+
+		if (inst.Rc)
+			ComputeRC(gpr.GetImm(a), 0);
+
 		return;
 	}
 	ARMReg rA = gpr.R(a);
@@ -865,7 +914,9 @@ void JitArm::twx(UGeckoInstruction inst)
 	MOV(RA, inst.TO);
 
 	if (inst.OPCD == 3) // twi
+	{
 		CMP(gpr.R(a), gpr.R(inst.RB));
+	}
 	else // tw
 	{
 		MOVI2R(RB, (s32)(s16)inst.SIMM_16);

Source/Core/Core/PowerPC/JitArm32/JitArm_LoadStore.cpp

@@ -68,7 +68,9 @@ void JitArm::SafeStoreFromReg(bool fastmem, s32 dest, u32 value, s32 regOffset,
 			NOP(1);
 		}
 		else
+		{
 			MOVI2R(R10, (u32)offset, false);
+		}
 
 		if (dest != -1)
 			ADD(R10, R10, RA);

Source/Core/Core/PowerPC/JitArm32/JitArm_LoadStoreFloating.cpp

@@ -89,11 +89,12 @@ void JitArm::lfXX(UGeckoInstruction inst)
 			ADD(rB, rB, RA);
 		}
 		else
+		{
 			ADD(rB, gpr.R(offsetReg), RA);
 		}
+	}
 	else
 	{
-
 		if (zeroA)
 		{
 			if (offsetReg == -1)
@@ -105,8 +106,10 @@ void JitArm::lfXX(UGeckoInstruction inst)
 					ADD(rB, rB, RA);
 				}
 				else
+				{
 					MOVI2R(rB, (u32)offset);
 				}
+			}
 			else
 			{
 				ARMReg RB = gpr.R(offsetReg);
@@ -116,10 +119,12 @@ void JitArm::lfXX(UGeckoInstruction inst)
 					ADD(rB, RB, RA);
 				}
 				else
+				{
 					MOV(rB, RB);
 				}
 			}
 		}
+	}
 	LDR(rA, R9, PPCSTATE_OFF(Exceptions));
 	CMP(rA, EXCEPTION_DSI);
 	FixupBranch DoNotLoad = B_CC(CC_EQ);
@@ -248,11 +253,12 @@ void JitArm::stfXX(UGeckoInstruction inst)
 			ADD(rB, rB, RA);
 		}
 		else
+		{
 			ADD(rB, gpr.R(offsetReg), RA);
 		}
+	}
 	else
 	{
-
 		if (zeroA)
 		{
 			if (offsetReg == -1)
@@ -264,8 +270,10 @@ void JitArm::stfXX(UGeckoInstruction inst)
 					ADD(rB, rB, RA);
 				}
 				else
+				{
 					MOVI2R(rB, (u32)offset);
 				}
+			}
 			else
 			{
 				ARMReg RB = gpr.R(offsetReg);
@@ -275,10 +283,12 @@ void JitArm::stfXX(UGeckoInstruction inst)
 					ADD(rB, RB, RA);
 				}
 				else
+				{
 					MOV(rB, RB);
 				}
 			}
 		}
+	}
 
 	if (update)
 	{
@@ -320,7 +330,6 @@ void JitArm::stfXX(UGeckoInstruction inst)
 			MOV(R1, rB);
 
 			BL(rA);
-
 		}
 		else
 		{
@@ -332,7 +341,6 @@ void JitArm::stfXX(UGeckoInstruction inst)
 			VMOV(D0, v0);
 			MOV(R0, rB);
 #endif
-
 			BL(rA);
 		}
 		POP(4, R0, R1, R2, R3);
@@ -361,8 +369,9 @@ void JitArm::stfs(UGeckoInstruction inst)
 		ADD(rB, rB, RA);
 	}
 	else
+	{
 		MOVI2R(rB, (u32)inst.SIMM_16);
-
+	}
 
 	MOVI2R(rA, (u32)&Memory::Write_U32);
 	PUSH(4, R0, R1, R2, R3);

Source/Core/Core/PowerPC/JitArm32/JitArm_LoadStorePaired.cpp

@@ -77,7 +77,9 @@ void JitArm::psq_lx(UGeckoInstruction inst)
 		ADD(R10, gpr.R(inst.RB), gpr.R(inst.RA));
 	}
 	else
+	{
 		MOV(R10, gpr.R(inst.RB));
+	}
 
 	if (update)
 		MOV(gpr.R(inst.RA), R10);
@@ -128,7 +130,9 @@ void JitArm::psq_st(UGeckoInstruction inst)
 		ADD(R10, gpr.R(inst.RA), R14);
 	}
 	else
+	{
 		MOVI2R(R10, (u32)offset);
+	}
 
 	if (update)
 		MOV(gpr.R(inst.RA), R10);
@@ -171,7 +175,9 @@ void JitArm::psq_stx(UGeckoInstruction inst)
 		ADD(R10, gpr.R(inst.RA), gpr.R(inst.RB));
 	}
 	else
+	{
 		MOV(R10, gpr.R(inst.RB));
+	}
 
 	if (update)
 		MOV(gpr.R(inst.RA), R10);

Source/Core/Core/PowerPC/JitArm32/JitArm_SystemRegisters.cpp

@@ -98,12 +98,14 @@ void JitArm::mtspr(UGeckoInstruction inst)
 	ARMReg RD = gpr.R(inst.RD);
 	STR(RD, R9,  PPCSTATE_OFF(spr) + iIndex * 4);
 }
+
 void JitArm::mftb(UGeckoInstruction inst)
 {
 	INSTRUCTION_START
 	JITDISABLE(bJITSystemRegistersOff);
 	mfspr(inst);
 }
+
 void JitArm::mfspr(UGeckoInstruction inst)
 {
 	INSTRUCTION_START

Source/Core/Core/PowerPC/JitArm32/JitArm_Tables.cpp

@@ -378,9 +378,12 @@ void CompileInstruction(PPCAnalyst::CodeOp & op)
 	JitArm *jitarm = (JitArm *)jit;
 	(jitarm->*dynaOpTable[op.inst.OPCD])(op.inst);
 	GekkoOPInfo *info = op.opinfo;
-	if (info) {
+
+	if (info)
+	{
 #ifdef OPLOG
-		if (!strcmp(info->opname, OP_TO_LOG)){  ///"mcrfs"
+		if (!strcmp(info->opname, OP_TO_LOG)) // "mcrfs"
+		{
 			rsplocations.push_back(jit.js.compilerPC);
 		}
 #endif

Source/Core/Core/PowerPC/JitArm32/JitAsm.h

@@ -14,13 +14,15 @@ private:
 	void GenerateCommon();
 
 public:
-	void Init() {
+	void Init()
+	{
 		AllocCodeSpace(8192);
 		Generate();
 		WriteProtect();
 	}
 
-	void Shutdown() {
+	void Shutdown()
+	{
 		FreeCodeSpace();
 	}
 };

Source/Core/Core/PowerPC/JitArm32/JitFPRCache.cpp

@@ -83,6 +83,7 @@ ARMReg *ArmFPRCache::GetAllocationOrder(int &count)
 ARMReg ArmFPRCache::GetReg(bool AutoLock)
 {
 	for (u8 a = 0; a < NUMARMREG; ++a)
+	{
 		if (ArmRegs[a].free)
 		{
 			// Alright, this one is free
@@ -90,6 +91,8 @@ ARMReg ArmFPRCache::GetReg(bool AutoLock)
 				ArmRegs[a].free = false;
 			return ArmRegs[a].Reg;
 		}
+	}
+
 	// Uh Oh, we have all them locked....
 	_assert_msg_(_DYNA_REC_, false, "All available registers are locked dumb dumb");
 	return D31;
@@ -109,9 +112,11 @@ u32 ArmFPRCache::GetLeastUsedRegister(bool increment)
 {
 	u32 HighestUsed = 0;
 	u8 lastRegIndex = 0;
-	for (u8 a = 0; a < NUMPPCREG; ++a){
+	for (u8 a = 0; a < NUMPPCREG; ++a)
+	{
 		if (increment)
 			++ArmCRegs[a].LastLoad;
+
 		if (ArmCRegs[a].LastLoad > HighestUsed)
 		{
 			HighestUsed = ArmCRegs[a].LastLoad;
@@ -123,11 +128,13 @@ u32 ArmFPRCache::GetLeastUsedRegister(bool increment)
 bool ArmFPRCache::FindFreeRegister(u32 &regindex)
 {
 	for (u8 a = 0; a < NUMPPCREG; ++a)
+	{
 		if (ArmCRegs[a].PPCReg == 33)
 		{
 			regindex = a;
 			return true;
 		}
+	}
 	return false;
 }
 

Source/Core/Core/PowerPC/JitArm32/JitRegCache.cpp

@@ -28,6 +28,7 @@ void ArmRegCache::Init(ARMXEmitter *emitter)
 		ArmRegs[a].free = true;
 	}
 }
+
 void ArmRegCache::Start(PPCAnalyst::BlockRegStats &stats)
 {
 	// Make sure the state is wiped on Start
@@ -71,6 +72,7 @@ ARMReg *ArmRegCache::GetAllocationOrder(int &count)
 ARMReg ArmRegCache::GetReg(bool AutoLock)
 {
 	for (u8 a = 0; a < NUMARMREG; ++a)
+	{
 		if (ArmRegs[a].free)
 		{
 			// Alright, this one is free
@@ -78,6 +80,8 @@ ARMReg ArmRegCache::GetReg(bool AutoLock)
 				ArmRegs[a].free = false;
 			return ArmRegs[a].Reg;
 		}
+	}
+
 	// Uh Oh, we have all them locked....
 	_assert_msg_(_DYNA_REC_, false, "All available registers are locked dumb dumb");
 	return R0;
@@ -92,11 +96,18 @@ void ArmRegCache::Unlock(ARMReg R0, ARMReg R1, ARMReg R2, ARMReg R3)
 			_assert_msg_(_DYNA_REC, !ArmRegs[RegNum].free, "This register is already unlocked");
 			ArmRegs[RegNum].free = true;
 		}
-		if ( R1 != INVALID_REG && ArmRegs[RegNum].Reg == R1) ArmRegs[RegNum].free = true;
+
-		if ( R2 != INVALID_REG && ArmRegs[RegNum].Reg == R2) ArmRegs[RegNum].free = true;
+		if (R1 != INVALID_REG && ArmRegs[RegNum].Reg == R1)
-		if ( R3 != INVALID_REG && ArmRegs[RegNum].Reg == R3) ArmRegs[RegNum].free = true;
+			ArmRegs[RegNum].free = true;
+
+		if (R2 != INVALID_REG && ArmRegs[RegNum].Reg == R2)
+			ArmRegs[RegNum].free = true;
+
+		if (R3 != INVALID_REG && ArmRegs[RegNum].Reg == R3)
+			ArmRegs[RegNum].free = true;
 	}
 }
+
 u32 ArmRegCache::GetLeastUsedRegister(bool increment)
 {
 	u32 HighestUsed = 0;
@@ -113,14 +124,17 @@ u32 ArmRegCache::GetLeastUsedRegister(bool increment)
 	}
 	return lastRegIndex;
 }
+
 bool ArmRegCache::FindFreeRegister(u32 &regindex)
 {
 	for (u8 a = 0; a < NUMPPCREG; ++a)
+	{
 		if (ArmCRegs[a].PPCReg == 33)
 		{
 			regindex = a;
 			return true;
 		}
+	}
 	return false;
 }