Merge pull request #9810 from JosJuice/fprf-cmp-mask
Jits: Fix fcmpX FPRF mask
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commit
aff39af5fb
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@ -401,6 +401,7 @@ union UReg_MSR
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#define FPRF_SHIFT 12
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#define FPRF_SHIFT 12
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#define FPRF_WIDTH 5
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#define FPRF_WIDTH 5
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#define FPRF_MASK (0x1F << FPRF_SHIFT)
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#define FPRF_MASK (0x1F << FPRF_SHIFT)
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#define FPCC_MASK (0xF << FPRF_SHIFT)
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// FPSCR exception flags
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// FPSCR exception flags
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enum FPSCRExceptionFlag : u32
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enum FPSCRExceptionFlag : u32
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@ -7,6 +7,7 @@
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#include "Common/CommonTypes.h"
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#include "Common/CommonTypes.h"
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#include "Common/FloatUtils.h"
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#include "Common/FloatUtils.h"
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#include "Core/PowerPC/Gekko.h"
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#include "Core/PowerPC/Interpreter/Interpreter.h"
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#include "Core/PowerPC/Interpreter/Interpreter.h"
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#include "Core/PowerPC/Interpreter/Interpreter_FPUtils.h"
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#include "Core/PowerPC/Interpreter/Interpreter_FPUtils.h"
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#include "Core/PowerPC/PowerPC.h"
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#include "Core/PowerPC/PowerPC.h"
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@ -169,7 +170,7 @@ void Interpreter::Helper_FloatCompareOrdered(UGeckoInstruction inst, double fa,
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const u32 compare_value = static_cast<u32>(compare_result);
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const u32 compare_value = static_cast<u32>(compare_result);
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// Clear and set the FPCC bits accordingly.
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// Clear and set the FPCC bits accordingly.
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FPSCR.FPRF = (FPSCR.FPRF & ~0xF) | compare_value;
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FPSCR.FPRF = (FPSCR.FPRF & ~FPCC_MASK) | compare_value;
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PowerPC::ppcState.cr.SetField(inst.CRFD, compare_value);
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PowerPC::ppcState.cr.SetField(inst.CRFD, compare_value);
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}
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}
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@ -203,7 +204,7 @@ void Interpreter::Helper_FloatCompareUnordered(UGeckoInstruction inst, double fa
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const u32 compare_value = static_cast<u32>(compare_result);
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const u32 compare_value = static_cast<u32>(compare_result);
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// Clear and set the FPCC bits accordingly.
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// Clear and set the FPCC bits accordingly.
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FPSCR.FPRF = (FPSCR.FPRF & ~0xF) | compare_value;
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FPSCR.FPRF = (FPSCR.FPRF & ~FPCC_MASK) | compare_value;
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PowerPC::ppcState.cr.SetField(inst.CRFD, compare_value);
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PowerPC::ppcState.cr.SetField(inst.CRFD, compare_value);
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}
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}
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@ -631,7 +631,7 @@ void Jit64::FloatCompare(UGeckoInstruction inst, bool upper)
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RegCache::Realize(Ra, Rb);
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RegCache::Realize(Ra, Rb);
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if (fprf)
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if (fprf)
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AND(32, PPCSTATE(fpscr), Imm32(~FPRF_MASK));
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AND(32, PPCSTATE(fpscr), Imm32(~FPCC_MASK));
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if (upper)
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if (upper)
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{
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{
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@ -402,7 +402,7 @@ void JitArm64::fcmpX(UGeckoInstruction inst)
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{
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{
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fpscr_reg = gpr.GetReg();
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fpscr_reg = gpr.GetReg();
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LDR(IndexType::Unsigned, fpscr_reg, PPC_REG, PPCSTATE_OFF(fpscr));
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LDR(IndexType::Unsigned, fpscr_reg, PPC_REG, PPCSTATE_OFF(fpscr));
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ANDI2R(fpscr_reg, fpscr_reg, ~FPRF_MASK);
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ANDI2R(fpscr_reg, fpscr_reg, ~FPCC_MASK);
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}
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}
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FixupBranch pNaN, pLesser, pGreater;
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FixupBranch pNaN, pLesser, pGreater;
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