Arm64Emitter: Add ArithOption with ExtendSpecifier
ARM64 can do perform various types of sign and zero extension on a register value before using it. The Arm64Emitter already had support for this, but it was kinda hidden away. This commit exposes the functionality by making the ExtendSpecifier enum available everywhere and adding a new ArithOption constructor.
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@ -309,6 +309,18 @@ enum class ShiftType
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ROR = 3,
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};
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enum class ExtendSpecifier
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{
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UXTB = 0x0,
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UXTH = 0x1,
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UXTW = 0x2, /* Also LSL on 32bit width */
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UXTX = 0x3, /* Also LSL on 64bit width */
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SXTB = 0x4,
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SXTH = 0x5,
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SXTW = 0x6,
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SXTX = 0x7,
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};
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enum class IndexType
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{
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Unsigned,
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@ -405,18 +417,6 @@ private:
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Width64Bit,
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};
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enum class ExtendSpecifier
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{
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UXTB = 0x0,
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UXTH = 0x1,
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UXTW = 0x2, /* Also LSL on 32bit width */
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UXTX = 0x3, /* Also LSL on 64bit width */
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SXTB = 0x4,
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SXTH = 0x5,
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SXTW = 0x6,
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SXTX = 0x7,
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};
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enum class TypeSpecifier
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{
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ExtendedReg,
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@ -463,6 +463,15 @@ public:
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}
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m_shifttype = ShiftType::LSL;
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}
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ArithOption(ARM64Reg Rd, ExtendSpecifier extend_type, u32 shift = 0)
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{
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m_destReg = Rd;
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m_width = Is64Bit(Rd) ? WidthSpecifier::Width64Bit : WidthSpecifier::Width32Bit;
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m_extend = extend_type;
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m_type = TypeSpecifier::ExtendedReg;
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m_shifttype = ShiftType::LSL;
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m_shift = shift;
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}
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ArithOption(ARM64Reg Rd, ShiftType shift_type, u32 shift)
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{
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m_destReg = Rd;
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