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JitArm64: Track single precision in load/store.

This commit is contained in:
degasus 2016-02-11 09:45:39 +01:00
parent 1e59dc1025
commit ae1b5ff9e8
3 changed files with 7 additions and 15 deletions
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2
Source/Core/Core/PowerPC/JitArm64/JitArm64_BackPatch.cpp
View File

@ -86,7 +86,6 @@ void JitArm64::EmitBackpatchRoutine(u32 flags, bool fastmem, bool do_farcode,
{
m_float_emit.LDR(32, EncodeRegToDouble(RS), X28, addr);
m_float_emit.REV32(8, EncodeRegToDouble(RS), EncodeRegToDouble(RS));
m_float_emit.FCVT(64, 32, EncodeRegToDouble(RS), EncodeRegToDouble(RS));
}
else
{
@ -214,7 +213,6 @@ void JitArm64::EmitBackpatchRoutine(u32 flags, bool fastmem, bool do_farcode,
MOVI2R(X30, (u64)&PowerPC::Read_U32);
BLR(X30);
m_float_emit.INS(32, RS, 0, X0);
m_float_emit.FCVT(64, 32, EncodeRegToDouble(RS), EncodeRegToDouble(RS));
}
else
{

2
Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStoreFloating.cpp
View File

@ -76,7 +76,7 @@ void JitArm64::lfXX(UGeckoInstruction inst)
u32 imm_addr = 0;
bool is_immediate = false;
RegType type = !!(flags & BackPatchInfo::FLAG_SIZE_F64) ? REG_LOWER_PAIR : REG_DUP;
RegType type = !!(flags & BackPatchInfo::FLAG_SIZE_F64) ? REG_LOWER_PAIR : REG_DUP_SINGLE;
gpr.Lock(W0, W30);
fpr.Lock(Q0);

18
Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStorePaired.cpp
View File

@ -62,20 +62,17 @@ void JitArm64::psq_l(UGeckoInstruction inst)
if (js.assumeNoPairedQuantize)
{
VS = fpr.RW(inst.RS, REG_REG);
VS = fpr.RW(inst.RS, REG_REG_SINGLE);
if (!inst.W)
{
ADD(EncodeRegTo64(addr_reg), EncodeRegTo64(addr_reg), X28);
m_float_emit.LD1(32, 1, EncodeRegToDouble(VS), EncodeRegTo64(addr_reg));
m_float_emit.REV32(8, VS, VS);
m_float_emit.FCVTL(64, VS, VS);
}
else
{
m_float_emit.LDR(32, VS, EncodeRegTo64(addr_reg), X28);
m_float_emit.REV32(8, VS, VS);
m_float_emit.FCVT(64, 32, EncodeRegToDouble(VS), EncodeRegToDouble(VS));
}
m_float_emit.REV32(8, EncodeRegToDouble(VS), EncodeRegToDouble(VS));
}
else
{
@ -87,17 +84,14 @@ void JitArm64::psq_l(UGeckoInstruction inst)
LDR(X30, X30, ArithOption(EncodeRegTo64(type_reg), true));
BLR(X30);
VS = fpr.RW(inst.RS, REG_REG);
if (!inst.W)
m_float_emit.FCVTL(64, VS, D0);
else
m_float_emit.FCVT(64, 32, EncodeRegToDouble(VS), D0);
VS = fpr.RW(inst.RS, REG_REG_SINGLE);
m_float_emit.ORR(EncodeRegToDouble(VS), D0, D0);
}
if (inst.W)
{
m_float_emit.FMOV(D0, 0x70); // 1.0 as a Double
m_float_emit.INS(64, VS, 1, Q0, 0);
m_float_emit.FMOV(S0, 0x70); // 1.0 as a Single
m_float_emit.INS(32, VS, 1, Q0, 0);
}
gpr.Unlock(W0, W1, W2, W30);