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JitArm64_FloatingPoint: Use ScopedARM64Reg

This commit is contained in:
Sintendo 2024-06-23 23:18:14 +02:00
parent 9805a8ac0a
commit ac3d3de66d
1 changed files with 158 additions and 169 deletions
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45
Source/Core/Core/PowerPC/JitArm64/JitArm64_FloatingPoint.cpp
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@ -102,15 +102,16 @@ void JitArm64::fp_arith(UGeckoInstruction inst)
const ARM64Reg VC = use_c ? reg_encoder(fpr.R(c, type)) : ARM64Reg::INVALID_REG;
const ARM64Reg VD = reg_encoder(fpr.RW(d, type_out));
ARM64Reg V0Q = ARM64Reg::INVALID_REG;
ARM64Reg V1Q = ARM64Reg::INVALID_REG;
{
Arm64FPRCache::ScopedARM64Reg V0Q = ARM64Reg::INVALID_REG;
Arm64FPRCache::ScopedARM64Reg V1Q = ARM64Reg::INVALID_REG;
ARM64Reg rounded_c_reg = VC;
if (round_c)
{
ASSERT_MSG(DYNA_REC, !inputs_are_singles, "Tried to apply 25-bit precision to single");
V0Q = fpr.GetReg();
V0Q = fpr.GetScopedReg();
rounded_c_reg = reg_encoder(V0Q);
Force25BitPrecision(rounded_c_reg, VC);
}
@ -119,7 +120,7 @@ void JitArm64::fp_arith(UGeckoInstruction inst)
if (fma && inaccurate_fma && VD == VB)
{
if (V0Q == ARM64Reg::INVALID_REG)
V0Q = fpr.GetReg();
V0Q = fpr.GetScopedReg();
inaccurate_fma_reg = reg_encoder(V0Q);
}
@ -128,7 +129,7 @@ void JitArm64::fp_arith(UGeckoInstruction inst)
m_accurate_nans && (VD == VA || (use_b && VD == VB) || (use_c && VD == VC));
if (preserve_d)
{
V1Q = fpr.GetReg();
V1Q = fpr.GetScopedReg();
result_reg = reg_encoder(V1Q);
}
@ -244,11 +245,7 @@ void JitArm64::fp_arith(UGeckoInstruction inst)
for (FixupBranch fixup : nan_fixups)
SetJumpTarget(fixup);
if (V0Q != ARM64Reg::INVALID_REG)
fpr.Unlock(V0Q);
if (V1Q != ARM64Reg::INVALID_REG)
fpr.Unlock(V1Q);
}
if (output_is_single)
{
@ -449,19 +446,20 @@ void JitArm64::FloatCompare(UGeckoInstruction inst, bool upper)
gpr.BindCRToRegister(crf, false);
const ARM64Reg XA = gpr.CR(crf);
ARM64Reg fpscr_reg = ARM64Reg::INVALID_REG;
Arm64GPRCache::ScopedARM64Reg fpscr_reg = ARM64Reg::INVALID_REG;
if (fprf)
{
fpscr_reg = gpr.GetReg();
fpscr_reg = gpr.GetScopedReg();
LDR(IndexType::Unsigned, fpscr_reg, PPC_REG, PPCSTATE_OFF(fpscr));
AND(fpscr_reg, fpscr_reg, LogicalImm(~FPCC_MASK, GPRSize::B32));
}
ARM64Reg V0Q = ARM64Reg::INVALID_REG;
ARM64Reg V1Q = ARM64Reg::INVALID_REG;
{
Arm64FPRCache::ScopedARM64Reg V0Q;
Arm64FPRCache::ScopedARM64Reg V1Q;
if (upper_a)
{
V0Q = fpr.GetReg();
V0Q = fpr.GetScopedReg();
m_float_emit.DUP(singles ? 32 : 64, paired_reg_encoder(V0Q), paired_reg_encoder(VA), 1);
VA = reg_encoder(V0Q);
}
@ -473,18 +471,14 @@ void JitArm64::FloatCompare(UGeckoInstruction inst, bool upper)
}
else
{
V1Q = fpr.GetReg();
V1Q = fpr.GetScopedReg();
m_float_emit.DUP(singles ? 32 : 64, paired_reg_encoder(V1Q), paired_reg_encoder(VB), 1);
VB = reg_encoder(V1Q);
}
}
m_float_emit.FCMP(VA, VB);
if (V0Q != ARM64Reg::INVALID_REG)
fpr.Unlock(V0Q);
if (V1Q != ARM64Reg::INVALID_REG)
fpr.Unlock(V1Q);
}
FixupBranch pNaN, pLesser, pGreater;
FixupBranch continue1, continue2, continue3;
@ -538,7 +532,6 @@ void JitArm64::FloatCompare(UGeckoInstruction inst, bool upper)
if (fprf)
{
STR(IndexType::Unsigned, fpscr_reg, PPC_REG, PPCSTATE_OFF(fpscr));
gpr.Unlock(fpscr_reg);
}
}
@ -572,7 +565,7 @@ void JitArm64::fctiwx(UGeckoInstruction inst)
if (single)
{
const ARM64Reg V0 = fpr.GetReg();
const auto V0 = fpr.GetScopedReg();
if (is_fctiwzx)
{
@ -589,12 +582,10 @@ void JitArm64::fctiwx(UGeckoInstruction inst)
m_float_emit.BIC(16, EncodeRegToDouble(V0), 0x7);
m_float_emit.ORR(EncodeRegToDouble(VD), EncodeRegToDouble(VD), EncodeRegToDouble(V0));
fpr.Unlock(V0);
}
else
{
const ARM64Reg WA = gpr.GetReg();
const auto WA = gpr.GetScopedReg();
if (is_fctiwzx)
{
@ -608,8 +599,6 @@ void JitArm64::fctiwx(UGeckoInstruction inst)
ORR(EncodeRegTo64(WA), EncodeRegTo64(WA), LogicalImm(0xFFF8'0000'0000'0000ULL, GPRSize::B64));
m_float_emit.FMOV(EncodeRegToDouble(VD), EncodeRegTo64(WA));
gpr.Unlock(WA);
}
ASSERT_MSG(DYNA_REC, b == d || single == fpr.IsSingle(b, true),