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DSPLLE - cleaning, small fixes (2 shift opcodes are more correct now (lsr,asr) + some 0x3... opcodes are working better in case they are extended) 

git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@4633 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
Marko Pusljar 2009-12-01 20:38:42 +00:00
parent 4d512ecba7
commit aa2f2dc95c
4 changed files with 65 additions and 68 deletions
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9
Source/Core/DSPCore/Src/DSPIntCCUtil.cpp
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@ -91,17 +91,12 @@ void Update_SR_Register16(s16 _Value, bool carry, bool overflow)
} }
} }
void Update_SR_LZ(s64 value) { void Update_SR_LZ(bool value) {
if (value == 0) if (value == true)
{
g_dsp.r[DSP_REG_SR] |= SR_LOGIC_ZERO; g_dsp.r[DSP_REG_SR] |= SR_LOGIC_ZERO;
}
else else
{
g_dsp.r[DSP_REG_SR] &= ~SR_LOGIC_ZERO; g_dsp.r[DSP_REG_SR] &= ~SR_LOGIC_ZERO;
}
} }
inline int GetMultiplyModifier() inline int GetMultiplyModifier()

2
Source/Core/DSPCore/Src/DSPIntCCUtil.h
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@ -32,7 +32,7 @@ int GetMultiplyModifier();
void Update_SR_Register16(s16 _Value, bool carry = false, bool overflow = false); void Update_SR_Register16(s16 _Value, bool carry = false, bool overflow = false);
void Update_SR_Register64(s64 _Value, bool carry = false, bool overflow = false); void Update_SR_Register64(s64 _Value, bool carry = false, bool overflow = false);
void Update_SR_LZ(s64 value); void Update_SR_LZ(bool value);
inline bool isAddCarry(u64 val, u64 result) { inline bool isAddCarry(u64 val, u64 result) {
return (val > result); return (val > result);

110
Source/Core/DSPCore/Src/DspIntArithmetic.cpp
View File

@ -134,6 +134,8 @@ void movax(const UDSPInstruction& opc)
Update_SR_Register64(acx); Update_SR_Register64(acx);
} }
// 0x3...
// XORR $acD.m, $axS.h // XORR $acD.m, $axS.h
// 0011 00sd 0xxx xxxx // 0011 00sd 0xxx xxxx
// Logic XOR (exclusive or) middle part of accumulator $acD.m with // Logic XOR (exclusive or) middle part of accumulator $acD.m with
@ -141,15 +143,14 @@ void movax(const UDSPInstruction& opc)
// x = extension (7 bits!!) // x = extension (7 bits!!)
void xorr(const UDSPInstruction& opc) void xorr(const UDSPInstruction& opc)
{ {
u8 sreg = (opc.hex >> 9) & 0x1;
u8 dreg = (opc.hex >> 8) & 0x1; u8 dreg = (opc.hex >> 8) & 0x1;
u16 axh = g_dsp.r[DSP_REG_AXH0 + sreg]; u8 sreg = (opc.hex >> 9) & 0x1;
u16 accm = g_dsp.r[DSP_REG_ACM0 + dreg] ^ g_dsp.r[DSP_REG_AXH0 + sreg];
zeroWriteBackLog(); zeroWriteBackLog();
g_dsp.r[DSP_REG_ACM0 + dreg] ^= axh; g_dsp.r[DSP_REG_ACM0 + dreg] = accm;
Update_SR_Register16((s16)accm);
Update_SR_Register16(dsp_get_acc_m(dreg));
} }
// ANDR $acD.m, $axS.h // ANDR $acD.m, $axS.h
@ -159,15 +160,14 @@ void xorr(const UDSPInstruction& opc)
// x = extension (7 bits!!) // x = extension (7 bits!!)
void andr(const UDSPInstruction& opc) void andr(const UDSPInstruction& opc)
{ {
u8 sreg = (opc.hex >> 9) & 0x1;
u8 dreg = (opc.hex >> 8) & 0x1; u8 dreg = (opc.hex >> 8) & 0x1;
u16 axh = g_dsp.r[DSP_REG_AXH0 + sreg]; u8 sreg = (opc.hex >> 9) & 0x1;
u16 accm = g_dsp.r[DSP_REG_ACM0 + dreg] & g_dsp.r[DSP_REG_AXH0 + sreg];
zeroWriteBackLog(); zeroWriteBackLog();
g_dsp.r[DSP_REG_ACM0 + dreg] &= axh; g_dsp.r[DSP_REG_ACM0 + dreg] = accm;
Update_SR_Register16((s16)accm);
Update_SR_Register16(dsp_get_acc_m(dreg));
} }
// ORR $acD.m, $axS.h // ORR $acD.m, $axS.h
@ -177,15 +177,14 @@ void andr(const UDSPInstruction& opc)
// x = extension (7 bits!!) // x = extension (7 bits!!)
void orr(const UDSPInstruction& opc) void orr(const UDSPInstruction& opc)
{ {
u8 sreg = (opc.hex >> 9) & 0x1;
u8 dreg = (opc.hex >> 8) & 0x1; u8 dreg = (opc.hex >> 8) & 0x1;
u16 axh = g_dsp.r[DSP_REG_AXH0 + sreg]; u8 sreg = (opc.hex >> 9) & 0x1;
u16 accm = g_dsp.r[DSP_REG_ACM0 + dreg] | g_dsp.r[DSP_REG_AXH0 + sreg];
zeroWriteBackLog(); zeroWriteBackLog();
g_dsp.r[DSP_REG_ACM0 + dreg] |= axh; g_dsp.r[DSP_REG_ACM0 + dreg] = accm;
Update_SR_Register16((s16)accm);
Update_SR_Register16(dsp_get_acc_m(dreg));
} }
// ANDC $acD.m, $ac(1-D).m // ANDC $acD.m, $ac(1-D).m
@ -195,14 +194,13 @@ void orr(const UDSPInstruction& opc)
// x = extension (7 bits!!) // x = extension (7 bits!!)
void andc(const UDSPInstruction& opc) void andc(const UDSPInstruction& opc)
{ {
u8 D = (opc.hex >> 8) & 0x1; u8 dreg = (opc.hex >> 8) & 0x1;
u16 accm = dsp_get_acc_m(1-D); u16 accm = g_dsp.r[DSP_REG_ACM0 + dreg] & g_dsp.r[DSP_REG_ACM0 + (1 - dreg)];
zeroWriteBackLog(); zeroWriteBackLog();
g_dsp.r[DSP_REG_ACM0+D] &= accm; g_dsp.r[DSP_REG_ACM0 + dreg] = accm;
Update_SR_Register16((s16)accm);
Update_SR_Register16(dsp_get_acc_m(D));
} }
// ORC $acD.m, $ac(1-D).m // ORC $acD.m, $ac(1-D).m
@ -212,14 +210,13 @@ void andc(const UDSPInstruction& opc)
// x = extension (7 bits!!) // x = extension (7 bits!!)
void orc(const UDSPInstruction& opc) void orc(const UDSPInstruction& opc)
{ {
u8 D = (opc.hex >> 8) & 0x1; u8 dreg = (opc.hex >> 8) & 0x1;
u16 accm = dsp_get_acc_m(1-D); u16 accm = g_dsp.r[DSP_REG_ACM0 + dreg] | g_dsp.r[DSP_REG_ACM0 + (1 - dreg)];
zeroWriteBackLog(); zeroWriteBackLog();
g_dsp.r[DSP_REG_ACM0+D] |= accm; g_dsp.r[DSP_REG_ACM0 + dreg] = accm;
Update_SR_Register16((s16)accm);
Update_SR_Register16(dsp_get_acc_m(D));
} }
// XORC $acD.m // XORC $acD.m
@ -229,12 +226,12 @@ void orc(const UDSPInstruction& opc)
void xorc(const UDSPInstruction& opc) void xorc(const UDSPInstruction& opc)
{ {
u8 dreg = (opc.hex >> 8) & 0x1; u8 dreg = (opc.hex >> 8) & 0x1;
u16 res = dsp_get_acc_m(dreg) ^ dsp_get_acc_m(1 - dreg); u16 accm = g_dsp.r[DSP_REG_ACM0 + dreg] ^ g_dsp.r[DSP_REG_ACM0 + (1 - dreg)];
zeroWriteBackLog(); zeroWriteBackLog();
g_dsp.r[DSP_REG_ACM0 + dreg] = res; g_dsp.r[DSP_REG_ACM0 + dreg] = accm;
Update_SR_Register16(res); Update_SR_Register16((s16)accm);
} }
// NOT $acD.m // NOT $acD.m
@ -244,12 +241,12 @@ void xorc(const UDSPInstruction& opc)
void notc(const UDSPInstruction& opc) void notc(const UDSPInstruction& opc)
{ {
u8 dreg = (opc.hex >> 8) & 0x1; u8 dreg = (opc.hex >> 8) & 0x1;
u16 res = dsp_get_acc_m(dreg)^0xffff; u16 accm = g_dsp.r[DSP_REG_ACM0 + dreg] ^ 0xffff;
zeroWriteBackLog(); zeroWriteBackLog();
g_dsp.r[DSP_REG_ACM0 + dreg] = res; g_dsp.r[DSP_REG_ACM0 + dreg] = accm;
Update_SR_Register16(res); Update_SR_Register16((s16)accm);
} }
void orf(const UDSPInstruction& opc) void orf(const UDSPInstruction& opc)
@ -257,7 +254,6 @@ void orf(const UDSPInstruction& opc)
ERROR_LOG(DSPLLE, "orf not implemented"); ERROR_LOG(DSPLLE, "orf not implemented");
} }
// Hermes switched andf and andcf, so check to make sure they are still correct
// ANDCF $acD.m, #I // ANDCF $acD.m, #I
// 0000 001r 1100 0000 // 0000 001r 1100 0000
// iiii iiii iiii iiii // iiii iiii iiii iiii
@ -269,11 +265,9 @@ void andcf(const UDSPInstruction& opc)
u16 imm = dsp_fetch_code(); u16 imm = dsp_fetch_code();
u16 val = dsp_get_acc_m(reg); u16 val = dsp_get_acc_m(reg);
Update_SR_LZ(((val & imm) == imm) ? 0 : 1); Update_SR_LZ(((val & imm) == imm) ? true : false);
} }
// Hermes switched andf and andcf, so check to make sure they are still correct
// ANDF $acD.m, #I // ANDF $acD.m, #I
// 0000 001r 1010 0000 // 0000 001r 1010 0000
// iiii iiii iiii iiii // iiii iiii iiii iiii
@ -286,7 +280,7 @@ void andf(const UDSPInstruction& opc)
u16 imm = dsp_fetch_code(); u16 imm = dsp_fetch_code();
u16 val = dsp_get_acc_m(reg); u16 val = dsp_get_acc_m(reg);
Update_SR_LZ(((val & imm) == 0) ? 0 : 1); Update_SR_LZ(((val & imm) == 0) ? true : false);
} }
// CMPI $amD, #I // CMPI $amD, #I
@ -674,13 +668,14 @@ void asr16(const UDSPInstruction& opc)
// Logically shifts left accumulator $acR by number specified by value I. // Logically shifts left accumulator $acR by number specified by value I.
void lsl(const UDSPInstruction& opc) void lsl(const UDSPInstruction& opc)
{ {
u16 shift = opc.ushift; u8 rreg = (opc.hex >> 8) & 0x01;
u64 acc = dsp_get_long_acc(opc.areg); u16 shift = opc.hex & 0x3f;
u64 acc = dsp_get_long_acc(rreg);
acc <<= shift; acc <<= shift;
if (shift != 0x0)
dsp_set_long_acc(rreg, acc);
dsp_set_long_acc(opc.areg, acc); Update_SR_Register64((s64)acc);
Update_SR_Register64(acc);
} }
// LSR $acR, #I // LSR $acR, #I
@ -689,14 +684,15 @@ void lsl(const UDSPInstruction& opc)
// calculated by negating sign extended bits 0-6. // calculated by negating sign extended bits 0-6.
void lsr(const UDSPInstruction& opc) void lsr(const UDSPInstruction& opc)
{ {
u16 shift = (u16) -(((s8)(opc.ushift << 2)) >> 2); u8 rreg = (opc.hex >> 8) & 0x01;
u64 acc = dsp_get_long_acc(opc.areg); u16 shift = 0x40 - (opc.hex & 0x3f);
// Lop off the extraneous sign extension our 64-bit fake accum causes
acc &= 0x000000FFFFFFFFFFULL; u64 acc = dsp_get_long_acc(rreg);
acc &= 0x000000FFFFFFFFFFULL; // Lop off the extraneous sign extension our 64-bit fake accum causes
acc >>= shift; acc >>= shift;
dsp_set_long_acc(opc.areg, (s64)acc); dsp_set_long_acc(rreg, (s64)acc);
Update_SR_Register64(acc); Update_SR_Register64((s64)acc);
} }
// ASL $acR, #I // ASL $acR, #I
@ -704,15 +700,17 @@ void lsr(const UDSPInstruction& opc)
// Logically shifts left accumulator $acR by number specified by value I. // Logically shifts left accumulator $acR by number specified by value I.
void asl(const UDSPInstruction& opc) void asl(const UDSPInstruction& opc)
{ {
u16 shift = opc.ushift; u8 rreg = (opc.hex >> 8) & 0x01;
u16 shift = opc.hex & 0x3f;
// arithmetic shift u64 acc = dsp_get_long_acc(rreg);
u64 acc = dsp_get_long_acc(opc.areg);
acc <<= shift; acc <<= shift;
dsp_set_long_acc(opc.areg, acc); // arithmetic shift
if (shift != 0x0)
dsp_set_long_acc(rreg, acc);
Update_SR_Register64(acc); Update_SR_Register64((s64)acc);
} }
// ASR $acR, #I // ASR $acR, #I
@ -721,14 +719,14 @@ void asl(const UDSPInstruction& opc)
// value calculated by negating sign extended bits 0-6. // value calculated by negating sign extended bits 0-6.
void asr(const UDSPInstruction& opc) void asr(const UDSPInstruction& opc)
{ {
u16 shift = (u16) -(((s8)(opc.ushift << 2)) >> 2); u8 rreg = (opc.hex >> 8) & 0x01;
u16 shift = 0x40 - (opc.hex & 0x3f);
// arithmetic shift // arithmetic shift
s64 acc = dsp_get_long_acc(opc.areg); s64 acc = dsp_get_long_acc(rreg);
acc >>= shift; acc >>= shift;
dsp_set_long_acc(opc.areg, acc); dsp_set_long_acc(rreg, acc);
Update_SR_Register64(acc); Update_SR_Register64(acc);
} }

6
Source/Plugins/Plugin_DSP_HLE/Src/UCodes/UCode_AXWii.cpp
View File

@ -312,6 +312,10 @@ bool CUCode_AXWii::AXTask(u32& _uMail)
uAddress += 10; uAddress += 10;
break; break;
case 0x0008:
uAddress += 26;
break;
case 0x000a: case 0x000a:
if (_CRC != 0xfa450138) // AXLIST_COMPRESSORTABLE if (_CRC != 0xfa450138) // AXLIST_COMPRESSORTABLE
{ {
@ -381,7 +385,7 @@ bool CUCode_AXWii::AXTask(u32& _uMail)
break; break;
default: default:
ERROR_LOG(DSPHLE,"DSPHLE - AXwii - AXLIST - Unknown CMD: %x",iCommand); INFO_LOG(DSPHLE,"DSPHLE - AXwii - AXLIST - Unknown CMD: %x",iCommand);
// unknown command so stop the execution of this TaskList // unknown command so stop the execution of this TaskList
bExecuteList = false; bExecuteList = false;
break; break;