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Merge pull request #1036 from phire/save-jitil 

Save JitIL! Fix bug so JitIL actually runs again.
This commit is contained in:
Pierre Bourdon 2014-09-11 23:27:59 +02:00
parent c6f3424ab1 1bbc7b4dbb
commit a96618b2e6
1 changed files with 5 additions and 4 deletions
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9
Source/Core/Core/PowerPC/Jit64IL/IR_X86.cpp
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@ -1592,10 +1592,11 @@ static void DoWriteCode(IRBuilder* ibuild, JitIL* Jit, u32 exitAddress)
// 0b0011111100000111, or 0x3F07. // 0b0011111100000111, or 0x3F07.
Jit->MOV(32, R(RSCRATCH), Imm32(0x3F07)); Jit->MOV(32, R(RSCRATCH), Imm32(0x3F07));
Jit->AND(32, R(RSCRATCH), M(((char *)&GQR(quantreg)) + 2)); Jit->AND(32, R(RSCRATCH), M(((char *)&GQR(quantreg)) + 2));
Jit->OR(32, R(RSCRATCH), Imm8(w << 3)); Jit->MOVZX(32, 8, RSCRATCH2, R(RSCRATCH));
Jit->OR(32, R(RSCRATCH2), Imm8(w << 3));
Jit->MOV(32, R(RSCRATCH2), regLocForInst(RI, getOp1(I))); Jit->MOV(32, R(RSCRATCH_EXTRA), regLocForInst(RI, getOp1(I)));
Jit->CALLptr(MScaled(RSCRATCH, SCALE_8, (u32)(u64)(((JitIL *)jit)->asm_routines.pairedLoadQuantized))); Jit->CALLptr(MScaled(RSCRATCH2, SCALE_8, (u32)(u64)(((JitIL *)jit)->asm_routines.pairedLoadQuantized)));
Jit->MOVAPD(reg, R(XMM0)); Jit->MOVAPD(reg, R(XMM0));
RI.fregs[reg] = I; RI.fregs[reg] = I;
regNormalRegClear(RI, I); regNormalRegClear(RI, I);
@ -1644,7 +1645,7 @@ static void DoWriteCode(IRBuilder* ibuild, JitIL* Jit, u32 exitAddress)
Jit->AND(32, R(RSCRATCH), PPCSTATE(spr[SPR_GQR0 + quantreg])); Jit->AND(32, R(RSCRATCH), PPCSTATE(spr[SPR_GQR0 + quantreg]));
Jit->MOVZX(32, 8, RSCRATCH2, R(RSCRATCH)); Jit->MOVZX(32, 8, RSCRATCH2, R(RSCRATCH));
Jit->MOV(32, R(RSCRATCH2), regLocForInst(RI, getOp2(I))); Jit->MOV(32, R(RSCRATCH_EXTRA), regLocForInst(RI, getOp2(I)));
Jit->MOVAPD(XMM0, fregLocForInst(RI, getOp1(I))); Jit->MOVAPD(XMM0, fregLocForInst(RI, getOp1(I)));
Jit->CALLptr(MScaled(RSCRATCH2, SCALE_8, (u32)(u64)(((JitIL *)jit)->asm_routines.pairedStoreQuantized))); Jit->CALLptr(MScaled(RSCRATCH2, SCALE_8, (u32)(u64)(((JitIL *)jit)->asm_routines.pairedStoreQuantized)));
if (RI.IInfo[I - RI.FirstI] & 4) if (RI.IInfo[I - RI.FirstI] & 4)