add some regs to PixelEngine.cpp: not sure, but probably no behavioral differences.
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@3476 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
Shawn Hoffman
parent
2baca7ca3d
commit
a852b6228d
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@ -36,6 +36,67 @@
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namespace PixelEngine
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{
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union UPEZConfReg
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{
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u16 Hex;
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struct
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{
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unsigned ZCompEnable : 1; // Z Comparator Enable
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unsigned Function : 3;
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unsigned ZUpdEnable : 1;
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unsigned : 11;
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};
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};
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union UPEAlphaConfReg
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{
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u16 Hex;
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struct
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{
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unsigned BMMath : 1; // GX_BM_BLEND || GX_BM_SUBSTRACT
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unsigned BMLogic : 1; // GX_BM_LOGIC
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unsigned Dither : 1;
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unsigned ColorUpdEnable : 1;
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unsigned AlphaUpdEnable : 1;
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unsigned DstFactor : 3;
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unsigned SrcFactor : 3;
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unsigned Substract : 1; // Additive mode by default
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unsigned BlendOperator : 4;
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};
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};
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union UPEDstAlphaConfReg
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{
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u16 Hex;
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struct
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{
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unsigned DstAlpha : 8;
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unsigned Enable : 1;
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unsigned : 7;
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};
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};
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union UPEAlphaModeConfReg
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{
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u16 Hex;
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struct
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{
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unsigned Threshold : 8;
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unsigned CompareMode : 8;
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};
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};
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// Not sure about this reg...
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union UPEAlphaReadReg
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{
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u16 Hex;
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struct
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{
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unsigned ReadMode : 3;
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unsigned : 13;
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};
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};
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// fifo Control Register
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union UPECtrlReg
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{
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@ -53,7 +114,13 @@ union UPECtrlReg
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};
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// STATE_TO_SAVE
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static UPECtrlReg g_ctrlReg;
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static UPEZConfReg m_ZConf;
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static UPEAlphaConfReg m_AlphaConf;
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static UPEDstAlphaConfReg m_DstAlphaConf;
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static UPEAlphaModeConfReg m_AlphaModeConf;
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static UPEAlphaReadReg m_AlphaRead;
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static UPECtrlReg m_Control;
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//static u16 m_Token; // token value most recently encountered
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static bool g_bSignalTokenInterrupt;
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static bool g_bSignalFinishInterrupt;
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@ -63,8 +130,14 @@ static int et_SetFinishOnMainThread;
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void DoState(PointerWrap &p)
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{
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p.Do(g_ctrlReg);
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p.Do(m_ZConf);
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p.Do(m_AlphaConf);
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p.Do(m_DstAlphaConf);
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p.Do(m_AlphaModeConf);
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p.Do(m_AlphaRead);
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p.Do(m_Control);
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p.Do(CommandProcessor::fifo.PEToken);
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p.Do(g_bSignalTokenInterrupt);
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p.Do(g_bSignalFinishInterrupt);
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}
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@ -76,7 +149,7 @@ void SetFinish_OnMainThread(u64 userdata, int cyclesLate);
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void Init()
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{
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g_ctrlReg.Hex = 0;
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m_Control.Hex = 0;
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et_SetTokenOnMainThread = CoreTiming::RegisterEvent("SetToken", SetToken_OnMainThread);
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et_SetFinishOnMainThread = CoreTiming::RegisterEvent("SetFinish", SetFinish_OnMainThread);
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@ -84,77 +157,90 @@ void Init()
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void Read16(u16& _uReturnValue, const u32 _iAddress)
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{
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DEBUG_LOG(PIXELENGINE, "(r16): 0x%08x", _iAddress);
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DEBUG_LOG(PIXELENGINE, "(r16) 0x%08x", _iAddress);
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switch (_iAddress & 0xFFF)
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{
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// The return values for these BBOX registers need to be gotten from the bounding box of the object.
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// See http://code.google.com/p/dolphin-emu/issues/detail?id=360#c74 for more details.
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case PE_BBOX_LEFT:
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_uReturnValue = 0x80;
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return;
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case PE_BBOX_RIGHT:
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_uReturnValue = 0xA0;
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return;
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case PE_BBOX_TOP:
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_uReturnValue = 0x80;
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return;
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case PE_BBOX_BOTTOM:
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_uReturnValue = 0xA0;
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return;
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// CPU Direct Access EFB Raster State Config
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case PE_ZCONF:
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_uReturnValue = m_ZConf.Hex;
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INFO_LOG(PIXELENGINE, "(r16) ZCONF");
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break;
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case PE_ALPHACONF:
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// Most games read this early. no idea why.
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_uReturnValue = m_AlphaConf.Hex;
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INFO_LOG(PIXELENGINE, "(r16) ALPHACONF");
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break;
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case PE_DSTALPHACONF:
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_uReturnValue = m_DstAlphaConf.Hex;
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INFO_LOG(PIXELENGINE, "(r16) DSTALPHACONF");
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break;
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case PE_ALPHAMODE:
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_uReturnValue = m_AlphaModeConf.Hex;
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INFO_LOG(PIXELENGINE, "(r16) ALPHAMODE");
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break;
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case PE_ALPHAREAD:
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_uReturnValue = m_AlphaRead.Hex;
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WARN_LOG(PIXELENGINE, "(r16) ALPHAREAD");
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break;
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case PE_CTRL_REGISTER:
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_uReturnValue = g_ctrlReg.Hex;
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INFO_LOG(PIXELENGINE,"\t CTRL_REGISTER : %04x", _uReturnValue);
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return;
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_uReturnValue = m_Control.Hex;
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INFO_LOG(PIXELENGINE, "(r16) CTRL_REGISTER : %04x", _uReturnValue);
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break;
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case PE_TOKEN_REG:
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_uReturnValue = CommandProcessor::fifo.PEToken;
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INFO_LOG(PIXELENGINE,"\t TOKEN_REG : %04x", _uReturnValue);
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return;
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INFO_LOG(PIXELENGINE, "(r16) TOKEN_REG : %04x", _uReturnValue);
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break;
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case PE_ALPHACONF:
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// Most games read this early. no idea why.
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INFO_LOG(PIXELENGINE, "(r16): PE_ALPHACONF");
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return;
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case PE_ZCONF:
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INFO_LOG(PIXELENGINE, "(r16): PE_ZCONF");
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return;
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case PE_DSTALPHACONF:
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INFO_LOG(PIXELENGINE, "(r16): PE_DSTALPHACONF");
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return;
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case PE_ALPHAMODE:
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INFO_LOG(PIXELENGINE, "(r16): PE_ALPHAMODE");
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return;
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case PE_ALPHAREAD:
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WARN_LOG(PIXELENGINE, "(r16): PE_ALPHAREAD");
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// The return values for these BBOX registers need to be gotten from the bounding box of the object.
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// See http://code.google.com/p/dolphin-emu/issues/detail?id=360#c74 for more details.
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case PE_BBOX_LEFT:
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_uReturnValue = 0x80;
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break;
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case PE_BBOX_RIGHT:
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_uReturnValue = 0xA0;
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break;
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case PE_BBOX_TOP:
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_uReturnValue = 0x80;
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break;
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case PE_BBOX_BOTTOM:
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_uReturnValue = 0xA0;
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break;
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default:
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WARN_LOG(PIXELENGINE, "(r16): unknown @ %08x", _iAddress);
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WARN_LOG(PIXELENGINE, "(r16) unknown @ %08x", _iAddress);
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_uReturnValue = 1;
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break;
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}
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_uReturnValue = 0x001;
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}
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void Write32(const u32 _iValue, const u32 _iAddress)
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{
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WARN_LOG(PIXELENGINE, "(w32): 0x%08x @ 0x%08x",_iValue,_iAddress);
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}
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void Write16(const u16 _iValue, const u32 _iAddress)
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{
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switch (_iAddress & 0xFFF)
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{
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// CPU Direct Access EFB Raster State Config
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case PE_ZCONF:
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m_ZConf.Hex = _iValue;
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INFO_LOG(PIXELENGINE, "(w16) ZCONF: %02x", _iValue);
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break;
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case PE_ALPHACONF:
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m_AlphaConf.Hex = _iValue;
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INFO_LOG(PIXELENGINE, "(w16) ALPHACONF: %02x", _iValue);
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break;
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case PE_DSTALPHACONF:
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m_DstAlphaConf.Hex = _iValue;
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INFO_LOG(PIXELENGINE, "(w16) DSTALPHACONF: %02x", _iValue);
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break;
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case PE_ALPHAMODE:
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m_AlphaModeConf.Hex = _iValue;
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INFO_LOG(PIXELENGINE, "(w16) ALPHAMODE: %02x", _iValue);
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break;
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case PE_ALPHAREAD:
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m_AlphaRead.Hex = _iValue;
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INFO_LOG(PIXELENGINE, "(w16) ALPHAREAD: %02x", _iValue);
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break;
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case PE_CTRL_REGISTER:
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{
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@ -163,12 +249,12 @@ void Write16(const u16 _iValue, const u32 _iAddress)
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if (tmpCtrl.PEToken) g_bSignalTokenInterrupt = false;
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if (tmpCtrl.PEFinish) g_bSignalFinishInterrupt = false;
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g_ctrlReg.PETokenEnable = tmpCtrl.PETokenEnable;
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g_ctrlReg.PEFinishEnable = tmpCtrl.PEFinishEnable;
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g_ctrlReg.PEToken = 0; // this flag is write only
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g_ctrlReg.PEFinish = 0; // this flag is write only
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m_Control.PETokenEnable = tmpCtrl.PETokenEnable;
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m_Control.PEFinishEnable = tmpCtrl.PEFinishEnable;
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m_Control.PEToken = 0; // this flag is write only
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m_Control.PEFinish = 0; // this flag is write only
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DEBUG_LOG(PIXELENGINE, "(w16): PE_CTRL_REGISTER: 0x%04x", _iValue);
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DEBUG_LOG(PIXELENGINE, "(w16) CTRL_REGISTER: 0x%04x", _iValue);
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UpdateInterrupts();
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}
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break;
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@ -180,34 +266,32 @@ void Write16(const u16 _iValue, const u32 _iAddress)
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//g_token = _iValue;
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break;
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// CPU Direct Access EFB Raster State Config
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case PE_ZCONF: INFO_LOG(PIXELENGINE, "(w16) ZCONF: %02x", _iValue); break;
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case PE_ALPHACONF: INFO_LOG(PIXELENGINE, "(w16) ALPHACONF: %02x", _iValue); break;
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case PE_DSTALPHACONF: INFO_LOG(PIXELENGINE, "(w16) DSTALPHACONF: %02x", _iValue); break;
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case PE_ALPHAMODE: INFO_LOG(PIXELENGINE, "(w16) ALPHAMODE: %02x", _iValue); break;
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case PE_ALPHAREAD: INFO_LOG(PIXELENGINE, "(w16) ALPHAREAD: %02x", _iValue); break;
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default:
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WARN_LOG(PIXELENGINE, "Write16: unknown %04x @ %08x", _iValue, _iAddress);
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WARN_LOG(PIXELENGINE, "(w16) unknown %04x @ %08x", _iValue, _iAddress);
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break;
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}
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}
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void Write32(const u32 _iValue, const u32 _iAddress)
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{
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WARN_LOG(PIXELENGINE, "(w32) 0x%08x @ 0x%08x IGNORING...",_iValue,_iAddress);
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}
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bool AllowIdleSkipping()
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{
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return !SConfig::GetInstance().m_LocalCoreStartupParameter.bUseDualCore || (!g_ctrlReg.PETokenEnable && !g_ctrlReg.PEFinishEnable);
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return !SConfig::GetInstance().m_LocalCoreStartupParameter.bUseDualCore || (!m_Control.PETokenEnable && !m_Control.PEFinishEnable);
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}
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void UpdateInterrupts()
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{
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// check if there is a token-interrupt
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if (g_bSignalTokenInterrupt & g_ctrlReg.PETokenEnable)
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if (g_bSignalTokenInterrupt & m_Control.PETokenEnable)
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CPeripheralInterface::SetInterrupt(CPeripheralInterface::INT_CAUSE_PE_TOKEN, true);
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else
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CPeripheralInterface::SetInterrupt(CPeripheralInterface::INT_CAUSE_PE_TOKEN, false);
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// check if there is a finish-interrupt
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if (g_bSignalFinishInterrupt & g_ctrlReg.PEFinishEnable)
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if (g_bSignalFinishInterrupt & m_Control.PEFinishEnable)
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CPeripheralInterface::SetInterrupt(CPeripheralInterface::INT_CAUSE_PE_FINISH, true);
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else
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CPeripheralInterface::SetInterrupt(CPeripheralInterface::INT_CAUSE_PE_FINISH, false);
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@ -14,6 +14,7 @@
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// Official SVN repository and contact information can be found at
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// http://code.google.com/p/dolphin-emu/
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#ifndef _PIXELENGINE_H
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#define _PIXELENGINE_H
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@ -23,21 +24,22 @@ class PointerWrap;
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// internal hardware addresses
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enum
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{
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PE_ZCONF = 0x000, // Z Config
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PE_ALPHACONF = 0x002, // Alpha Config
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PE_DSTALPHACONF = 0x004, // Destination Alpha Config
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PE_ALPHAMODE = 0x006, // Alpha Mode Config
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PE_ALPHAREAD = 0x008, // Alpha Read
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PE_CTRL_REGISTER = 0x00a, // Control
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PE_TOKEN_REG = 0x00e, // Token
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PE_BBOX_LEFT = 0x010, // Flip Left
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PE_BBOX_RIGHT = 0x012, // Flip Right
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PE_BBOX_TOP = 0x014, // Flip Top
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PE_BBOX_BOTTOM = 0x016, // Flip Bottom
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PE_ZCONF = 0x00, // Z Config
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PE_ALPHACONF = 0x02, // Alpha Config
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PE_DSTALPHACONF = 0x04, // Destination Alpha Config
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PE_ALPHAMODE = 0x06, // Alpha Mode Config
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PE_ALPHAREAD = 0x08, // Alpha Read
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PE_CTRL_REGISTER = 0x0a, // Control
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PE_TOKEN_REG = 0x0e, // Token
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PE_BBOX_LEFT = 0x10, // Flip Left
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PE_BBOX_RIGHT = 0x12, // Flip Right
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PE_BBOX_TOP = 0x14, // Flip Top
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PE_BBOX_BOTTOM = 0x16, // Flip Bottom
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};
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namespace PixelEngine
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{
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void Init();
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void DoState(PointerWrap &p);
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@ -56,5 +58,3 @@ bool AllowIdleSkipping();
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} // end of namespace PixelEngine
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#endif
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