PowerPC: add enum values for emulator SO and LT shifts
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25a701aa1b
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a68c1bf648
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@ -20,6 +20,9 @@ enum CRBits
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CR_EQ_BIT = 1,
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CR_EQ_BIT = 1,
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CR_GT_BIT = 2,
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CR_GT_BIT = 2,
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CR_LT_BIT = 3,
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CR_LT_BIT = 3,
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CR_EMU_SO_BIT = 59,
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CR_EMU_LT_BIT = 62,
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};
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};
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// Optimized CR implementation. Instead of storing CR in its PowerPC format
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// Optimized CR implementation. Instead of storing CR in its PowerPC format
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@ -46,10 +49,10 @@ struct ConditionRegister
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static u64 PPCToInternal(u8 value)
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static u64 PPCToInternal(u8 value)
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{
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{
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u64 cr_val = 0x100000000;
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u64 cr_val = 0x100000000;
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cr_val |= (u64) !!(value & CR_SO) << 59;
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cr_val |= (u64) !!(value & CR_SO) << CR_EMU_SO_BIT;
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cr_val |= (u64) !(value & CR_EQ);
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cr_val |= (u64) !(value & CR_EQ);
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cr_val |= (u64) !(value & CR_GT) << 63;
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cr_val |= (u64) !(value & CR_GT) << 63;
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cr_val |= (u64) !!(value & CR_LT) << 62;
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cr_val |= (u64) !!(value & CR_LT) << CR_EMU_LT_BIT;
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return cr_val;
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return cr_val;
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}
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}
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@ -64,7 +67,8 @@ struct ConditionRegister
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u32 ppc_cr = 0;
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u32 ppc_cr = 0;
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// LT/SO
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// LT/SO
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ppc_cr |= (cr_val >> 59) & (PowerPC::CR_LT | PowerPC::CR_SO);
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static_assert(CR_EMU_LT_BIT - CR_EMU_SO_BIT == CR_LT_BIT - CR_SO_BIT);
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ppc_cr |= (cr_val >> CR_EMU_SO_BIT) & (PowerPC::CR_LT | PowerPC::CR_SO);
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// EQ
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// EQ
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ppc_cr |= ((cr_val & 0xFFFFFFFF) == 0) << PowerPC::CR_EQ_BIT;
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ppc_cr |= ((cr_val & 0xFFFFFFFF) == 0) << PowerPC::CR_EQ_BIT;
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// GT
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// GT
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@ -13,7 +13,8 @@ void Interpreter::Helper_UpdateCR0(u32 value)
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{
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{
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s64 sign_extended = (s64)(s32)value;
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s64 sign_extended = (s64)(s32)value;
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u64 cr_val = (u64)sign_extended;
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u64 cr_val = (u64)sign_extended;
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cr_val = (cr_val & ~(1ull << 59)) | ((u64)PowerPC::GetXER_SO() << 59);
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cr_val = (cr_val & ~(1ull << PowerPC::CR_EMU_SO_BIT)) |
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((u64)PowerPC::GetXER_SO() << PowerPC::CR_EMU_SO_BIT);
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PowerPC::ppcState.cr.fields[0] = cr_val;
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PowerPC::ppcState.cr.fields[0] = cr_val;
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}
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}
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@ -25,7 +25,7 @@ void Jit64::GetCRFieldBit(int field, int bit, X64Reg out, bool negate)
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switch (bit)
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switch (bit)
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{
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{
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case PowerPC::CR_SO_BIT: // check bit 59 set
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case PowerPC::CR_SO_BIT: // check bit 59 set
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BT(64, CROffset(field), Imm8(59));
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BT(64, CROffset(field), Imm8(PowerPC::CR_EMU_SO_BIT));
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SETcc(negate ? CC_NC : CC_C, R(out));
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SETcc(negate ? CC_NC : CC_C, R(out));
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break;
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break;
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@ -40,7 +40,7 @@ void Jit64::GetCRFieldBit(int field, int bit, X64Reg out, bool negate)
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break;
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break;
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case PowerPC::CR_LT_BIT: // check bit 62 set
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case PowerPC::CR_LT_BIT: // check bit 62 set
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BT(64, CROffset(field), Imm8(62));
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BT(64, CROffset(field), Imm8(PowerPC::CR_EMU_LT_BIT));
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SETcc(negate ? CC_NC : CC_C, R(out));
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SETcc(negate ? CC_NC : CC_C, R(out));
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break;
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break;
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@ -60,8 +60,8 @@ void Jit64::SetCRFieldBit(int field, int bit, X64Reg in)
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switch (bit)
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switch (bit)
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{
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{
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case PowerPC::CR_SO_BIT: // set bit 59 to input
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case PowerPC::CR_SO_BIT: // set bit 59 to input
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BTR(64, R(RSCRATCH2), Imm8(59));
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BTR(64, R(RSCRATCH2), Imm8(PowerPC::CR_EMU_SO_BIT));
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SHL(64, R(in), Imm8(59));
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SHL(64, R(in), Imm8(PowerPC::CR_EMU_SO_BIT));
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OR(64, R(RSCRATCH2), R(in));
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OR(64, R(RSCRATCH2), R(in));
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break;
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break;
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@ -80,8 +80,8 @@ void Jit64::SetCRFieldBit(int field, int bit, X64Reg in)
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break;
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break;
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case PowerPC::CR_LT_BIT: // set bit 62 to input
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case PowerPC::CR_LT_BIT: // set bit 62 to input
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BTR(64, R(RSCRATCH2), Imm8(62));
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BTR(64, R(RSCRATCH2), Imm8(PowerPC::CR_EMU_LT_BIT));
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SHL(64, R(in), Imm8(62));
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SHL(64, R(in), Imm8(PowerPC::CR_EMU_LT_BIT));
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OR(64, R(RSCRATCH2), R(in));
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OR(64, R(RSCRATCH2), R(in));
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break;
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break;
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}
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}
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@ -95,7 +95,7 @@ void Jit64::ClearCRFieldBit(int field, int bit)
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switch (bit)
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switch (bit)
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{
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{
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case PowerPC::CR_SO_BIT:
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case PowerPC::CR_SO_BIT:
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BTR(64, CROffset(field), Imm8(59));
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BTR(64, CROffset(field), Imm8(PowerPC::CR_EMU_SO_BIT));
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break;
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break;
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case PowerPC::CR_EQ_BIT:
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case PowerPC::CR_EQ_BIT:
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@ -110,7 +110,7 @@ void Jit64::ClearCRFieldBit(int field, int bit)
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break;
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break;
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case PowerPC::CR_LT_BIT:
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case PowerPC::CR_LT_BIT:
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BTR(64, CROffset(field), Imm8(62));
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BTR(64, CROffset(field), Imm8(PowerPC::CR_EMU_LT_BIT));
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break;
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break;
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}
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}
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// We don't need to set bit 32; the cases where that's needed only come up when setting bits, not
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// We don't need to set bit 32; the cases where that's needed only come up when setting bits, not
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@ -126,7 +126,7 @@ void Jit64::SetCRFieldBit(int field, int bit)
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switch (bit)
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switch (bit)
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{
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{
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case PowerPC::CR_SO_BIT:
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case PowerPC::CR_SO_BIT:
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BTS(64, R(RSCRATCH), Imm8(59));
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BTS(64, R(RSCRATCH), Imm8(PowerPC::CR_EMU_SO_BIT));
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break;
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break;
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case PowerPC::CR_EQ_BIT:
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case PowerPC::CR_EQ_BIT:
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@ -139,7 +139,7 @@ void Jit64::SetCRFieldBit(int field, int bit)
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break;
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break;
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case PowerPC::CR_LT_BIT:
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case PowerPC::CR_LT_BIT:
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BTS(64, R(RSCRATCH), Imm8(62));
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BTS(64, R(RSCRATCH), Imm8(PowerPC::CR_EMU_LT_BIT));
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break;
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break;
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}
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}
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@ -163,7 +163,7 @@ FixupBranch Jit64::JumpIfCRFieldBit(int field, int bit, bool jump_if_set)
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switch (bit)
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switch (bit)
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{
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{
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case PowerPC::CR_SO_BIT: // check bit 59 set
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case PowerPC::CR_SO_BIT: // check bit 59 set
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BT(64, CROffset(field), Imm8(59));
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BT(64, CROffset(field), Imm8(PowerPC::CR_EMU_SO_BIT));
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return J_CC(jump_if_set ? CC_C : CC_NC, true);
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return J_CC(jump_if_set ? CC_C : CC_NC, true);
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case PowerPC::CR_EQ_BIT: // check bits 31-0 == 0
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case PowerPC::CR_EQ_BIT: // check bits 31-0 == 0
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@ -175,7 +175,7 @@ FixupBranch Jit64::JumpIfCRFieldBit(int field, int bit, bool jump_if_set)
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return J_CC(jump_if_set ? CC_G : CC_LE, true);
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return J_CC(jump_if_set ? CC_G : CC_LE, true);
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case PowerPC::CR_LT_BIT: // check bit 62 set
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case PowerPC::CR_LT_BIT: // check bit 62 set
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BT(64, CROffset(field), Imm8(62));
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BT(64, CROffset(field), Imm8(PowerPC::CR_EMU_LT_BIT));
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return J_CC(jump_if_set ? CC_C : CC_NC, true);
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return J_CC(jump_if_set ? CC_C : CC_NC, true);
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default:
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default:
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@ -322,7 +322,7 @@ void CommonAsmRoutines::GenMfcr()
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// SO: Bit 59 set; set flag bit 0
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// SO: Bit 59 set; set flag bit 0
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// LT: Bit 62 set; set flag bit 3
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// LT: Bit 62 set; set flag bit 3
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SHR(64, R(cr_val), Imm8(59));
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SHR(64, R(cr_val), Imm8(PowerPC::CR_EMU_SO_BIT));
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AND(32, R(cr_val), Imm8(PowerPC::CR_LT | PowerPC::CR_SO));
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AND(32, R(cr_val), Imm8(PowerPC::CR_LT | PowerPC::CR_SO));
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OR(32, R(dst), R(cr_val));
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OR(32, R(dst), R(cr_val));
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}
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}
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@ -22,14 +22,14 @@ FixupBranch JitArm64::JumpIfCRFieldBit(int field, int bit, bool jump_if_set)
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switch (bit)
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switch (bit)
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{
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{
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case PowerPC::CR_SO_BIT: // check bit 59 set
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case PowerPC::CR_SO_BIT: // check bit 59 set
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return jump_if_set ? TBNZ(XA, 59) : TBZ(XA, 59);
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return jump_if_set ? TBNZ(XA, PowerPC::CR_EMU_SO_BIT) : TBZ(XA, PowerPC::CR_EMU_SO_BIT);
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case PowerPC::CR_EQ_BIT: // check bits 31-0 == 0
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case PowerPC::CR_EQ_BIT: // check bits 31-0 == 0
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return jump_if_set ? CBZ(WA) : CBNZ(WA);
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return jump_if_set ? CBZ(WA) : CBNZ(WA);
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case PowerPC::CR_GT_BIT: // check val > 0
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case PowerPC::CR_GT_BIT: // check val > 0
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CMP(XA, ARM64Reg::SP);
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CMP(XA, ARM64Reg::SP);
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return B(jump_if_set ? CC_GT : CC_LE);
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return B(jump_if_set ? CC_GT : CC_LE);
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case PowerPC::CR_LT_BIT: // check bit 62 set
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case PowerPC::CR_LT_BIT: // check bit 62 set
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return jump_if_set ? TBNZ(XA, 62) : TBZ(XA, 62);
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return jump_if_set ? TBNZ(XA, PowerPC::CR_EMU_LT_BIT) : TBZ(XA, PowerPC::CR_EMU_LT_BIT);
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default:
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default:
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ASSERT_MSG(DYNA_REC, false, "Invalid CR bit");
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ASSERT_MSG(DYNA_REC, false, "Invalid CR bit");
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return {};
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return {};
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@ -441,7 +441,7 @@ void JitArm64::crXXX(UGeckoInstruction inst)
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switch (bit)
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switch (bit)
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{
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{
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case PowerPC::CR_SO_BIT:
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case PowerPC::CR_SO_BIT:
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ANDI2R(XA, XA, ~(u64(1) << 59));
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ANDI2R(XA, XA, ~(u64(1) << PowerPC::CR_EMU_SO_BIT));
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break;
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break;
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case PowerPC::CR_EQ_BIT:
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case PowerPC::CR_EQ_BIT:
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@ -454,7 +454,7 @@ void JitArm64::crXXX(UGeckoInstruction inst)
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break;
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break;
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case PowerPC::CR_LT_BIT:
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case PowerPC::CR_LT_BIT:
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ANDI2R(XA, XA, ~(u64(1) << 62));
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ANDI2R(XA, XA, ~(u64(1) << PowerPC::CR_EMU_LT_BIT));
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break;
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break;
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}
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}
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return;
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return;
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@ -476,7 +476,7 @@ void JitArm64::crXXX(UGeckoInstruction inst)
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switch (bit)
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switch (bit)
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{
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{
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case PowerPC::CR_SO_BIT:
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case PowerPC::CR_SO_BIT:
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ORRI2R(XA, XA, u64(1) << 59);
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ORRI2R(XA, XA, u64(1) << PowerPC::CR_EMU_SO_BIT);
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break;
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break;
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case PowerPC::CR_EQ_BIT:
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case PowerPC::CR_EQ_BIT:
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@ -488,7 +488,7 @@ void JitArm64::crXXX(UGeckoInstruction inst)
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break;
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break;
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case PowerPC::CR_LT_BIT:
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case PowerPC::CR_LT_BIT:
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ORRI2R(XA, XA, u64(1) << 62);
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ORRI2R(XA, XA, u64(1) << PowerPC::CR_EMU_LT_BIT);
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break;
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break;
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}
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}
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@ -520,7 +520,7 @@ void JitArm64::crXXX(UGeckoInstruction inst)
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switch (bit)
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switch (bit)
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{
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{
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case PowerPC::CR_SO_BIT: // check bit 59 set
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case PowerPC::CR_SO_BIT: // check bit 59 set
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UBFX(out, XC, 59, 1);
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UBFX(out, XC, PowerPC::CR_EMU_SO_BIT, 1);
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if (negate)
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if (negate)
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EOR(out, out, 0, 0, true); // XC ^ 1
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EOR(out, out, 0, 0, true); // XC ^ 1
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break;
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break;
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@ -536,7 +536,7 @@ void JitArm64::crXXX(UGeckoInstruction inst)
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break;
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break;
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case PowerPC::CR_LT_BIT: // check bit 62 set
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case PowerPC::CR_LT_BIT: // check bit 62 set
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UBFX(out, XC, 62, 1);
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UBFX(out, XC, PowerPC::CR_EMU_LT_BIT, 1);
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if (negate)
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if (negate)
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EOR(out, out, 0, 0, true); // XC ^ 1
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EOR(out, out, 0, 0, true); // XC ^ 1
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break;
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break;
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@ -582,7 +582,7 @@ void JitArm64::crXXX(UGeckoInstruction inst)
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switch (bit)
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switch (bit)
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{
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{
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case PowerPC::CR_SO_BIT: // set bit 59 to input
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case PowerPC::CR_SO_BIT: // set bit 59 to input
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BFI(XB, XA, 59, 1);
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BFI(XB, XA, PowerPC::CR_EMU_SO_BIT, 1);
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break;
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break;
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case PowerPC::CR_EQ_BIT: // clear low 32 bits, set bit 0 to !input
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case PowerPC::CR_EQ_BIT: // clear low 32 bits, set bit 0 to !input
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@ -597,7 +597,7 @@ void JitArm64::crXXX(UGeckoInstruction inst)
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break;
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break;
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case PowerPC::CR_LT_BIT: // set bit 62 to input
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case PowerPC::CR_LT_BIT: // set bit 62 to input
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BFI(XB, XA, 62, 1);
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BFI(XB, XA, PowerPC::CR_EMU_LT_BIT, 1);
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break;
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break;
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}
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}
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@ -625,11 +625,11 @@ void JitArm64::mfcr(UGeckoInstruction inst)
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// SO
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// SO
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if (i == 0)
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if (i == 0)
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{
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{
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UBFX(XA, CR, 59, 1);
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UBFX(XA, CR, PowerPC::CR_EMU_SO_BIT, 1);
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}
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}
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else
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else
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{
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{
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UBFX(XC, CR, 59, 1);
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UBFX(XC, CR, PowerPC::CR_EMU_SO_BIT, 1);
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ORR(XA, XC, XA, ArithOption(XA, ShiftType::LSL, 4));
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ORR(XA, XC, XA, ArithOption(XA, ShiftType::LSL, 4));
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}
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}
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@ -644,7 +644,7 @@ void JitArm64::mfcr(UGeckoInstruction inst)
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CSEL(WA, WC, WA, CC_GT);
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CSEL(WA, WC, WA, CC_GT);
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// LT
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// LT
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UBFX(XC, CR, 62, 1);
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UBFX(XC, CR, PowerPC::CR_EMU_LT_BIT, 1);
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ORR(WA, WA, WC, ArithOption(WC, ShiftType::LSL, 3));
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ORR(WA, WA, WC, ArithOption(WC, ShiftType::LSL, 3));
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}
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}
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